Asymmetric Spacers
A semiconductor device having asymmetric spacers and steps for forming the same are disclosed. The spacers have difference capacitances, with the spacer having a higher capacitance formed over a source region of the device and the spacer having a lower capacitance formed over a drain region of the device. Embodiments of the disclosed invention include spacers made from different materials, having different or substantially equal thicknesses.
Latest IBM Patents:
- AUTO-DETECTION OF OBSERVABLES AND AUTO-DISPOSITION OF ALERTS IN AN ENDPOINT DETECTION AND RESPONSE (EDR) SYSTEM USING MACHINE LEARNING
- OPTIMIZING SOURCE CODE USING CALLABLE UNIT MATCHING
- Low thermal conductivity support system for cryogenic environments
- Partial loading of media based on context
- Recast repetitive messages
This application is related to the following commonly-owned, co-pending United States Patent Application filed on even date herewith, the contents and disclosure of which is expressly incorporated by reference herein in its entirety: U.S. Patent Application Serial No. (FIS920120314US1), for “ANGLED GAS CLUSTER ION BEAM”.
FIELD OF THE INVENTIONThe present invention generally relates to semiconductor devices, and particularly to field effect transistor devices with sidewall spacers and methods for making the same.
BACKGROUNDComplementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits, such as CPUs, memory, storage devices, and the like. At the core of planar FETs, a channel region is formed in a n-doped or p-doped semiconductor substrate on which a gate structure is formed. The overall fabrication process is well known in the art, and includes forming a gate structure over a channel region connecting a source region and a drain region within the substrate on opposite ends of the gate, typically with some vertical overlap between the gate and the source/drain regions. In finFETs, the gate structure may be formed over or around a semiconductor fin on an insulator layer, with the source and the drain region formed on opposite ends of the semiconductor fin. In planar FETs, an insulating spacer structure is formed on opposing sidewalls of the gate over, vertically overlapping a portion of the source/drain region.
As the industry continues to move towards smaller scale devices that operate at faster speeds and with lesser operational costs, it becomes increasingly difficult to retain device operation and efficiency. This is partially because while operational side effects may be negligible at a given scale, they play a more critical role as devices are scaled down. A particular problem is the buildup of parasitic capacitance in FETs and similar structures. The source/drain regions and the gate are both conductors, and are separated by insulating spacers. Therefore, they functions as an unwanted capacitor, contributing to the buildup of parasitic capacitance. Because capacitance is inversely proportional to insulator thickness between two conductors, it increases as transistors become smaller and spaces become thinner. As the parasitic capacitance of a transistor increases, its operability and performance suffer.
Therefore, it is desirable to form a transistor structure that reduces the build up of parasitic capacitance and improves device reliability and efficiency, particularly in scaled-down transistor structures.
SUMMARYAccording to an embodiment of the disclosed invention, a semiconductor device comprises a gate formed on a top surface of a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite the second sidewall, a first spacer formed on and adjacent to the first sidewall of the gate, wherein the first spacer is made of a first material, and a second spacer formed on and adjacent to the second sidewall of the gate, wherein the second spacer is made of a second material different from the first material.
According to a further embodiment of the disclosed invention, a semiconductor device includes a gate formed on a top surface of a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite the second sidewall; a first spacer formed on the gate proximate to the first sidewall, wherein the first spacer is made of a first material; and a second spacer formed on and adjacent to the second sidewall of the gate, wherein the second spacer is made of a second material different from the first material.
According to another embodiment of the disclosed invention, a method for forming a semiconductor device includes the steps of forming a gate onto a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite to the second sidewall; forming a first film layer on and adjacent to the first sidewall of the gate, wherein the first film layer is made from a first material; forming a second film layer made on and adjacent to the second sidewall of the gate, wherein the second film layer is made from a second material different from the first material; and shaping the first film layer to form a first spacer and shaping the second film layer to form a second spacer.
According to a further embodiment of the disclosed invention, a method for forming a semiconductor device, includes forming a gate onto a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite to the second sidewall; forming a first film layer on the gate proximate to the first sidewall, wherein the first film layer is made from a first material; forming a second film layer made on and adjacent to the second sidewall of the gate, wherein the second film layer is made from a second material different from the first material; and shaping the first film layer to form a first spacer and shaping the second film layer to form a second spacer.
Elements of the figures are not necessarily to scale and are not intended to portray specific parameters of the invention. For clarity and ease of illustration, scale of elements may be exaggerated. The detailed description should be consulted for accurate dimensions. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements.
Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
Referring to
Referring now to
In other embodiments, the gate 104 may be formed using a gate-last process, in which case the gate 104 may include a dummy gate layer made of, for example, silicon, and a dummy gate dielectric made of, for example, silicon oxide, intended to serve as a placeholder for the replacement gate formed after later processing steps. The gate 104 is replaced with a true gate dielectric and a gate conductor during subsequent processes.
Further referring to
Referring now to
Further referring to
Referring now to
Although the spacer film layer 202 forms a thicker layer than the spacer film layer 204 in the depicted embodiment, the spacer film layer 202 may in fact be the thinner layer of the two in other embodiments. In other words, it is not necessary that the thicker layer of the two spacer film layers be formed first.
Referring now to
Referring now to
The resulting structure shown in
Further referring to
According to another embodiment of the disclosed invention, one or more intermediary layers may be formed at the interface of one of the spacer 302 or 304 and the respective sidewalls 104b or 104a, prior to the formation of that spacer film layer. For example, an oxide layer may be formed onto the gate 104 and adjacent to the sidewall 104a, and thereafter the spacer 304 may be formed on top of the oxide layer, proximate to the sidewall 104a. According to the disclosed embodiment, the second spacer 302 may be formed on the gate and adjacent to the sidewall 104b.
In a related embodiment, the spacer 304 may be formed using an oxide compound (having, for example, a relative dielectric constant dielectric constant of 3.9), and the spacer 302 may be formed using a second compound having a lower dielectric constant, such as carbon doped-silicon oxide.
Referring now generally to
Referring now specifically to
Referring now to
Referring now to
As described in connection with
According to a related embodiment, the spacer 304 may be formed proximate to the sidewall 104a subsequent to forming an underlying layer using a material such as an oxide, and the spacer 302 may be formed adjacent to the sidewall 104b.
According to the disclosed embodiment, the spacer 302 is made from an oxide compound having a lower dielectric constant relative to the spacer 304, and is formed over the drain side of the gate, whereas the spacer 304 is made from a nitride compound having a relatively higher dielectric constant and is formed over the source side of the gate.
According to a related embodiment, the spacer 304 is made from an oxide compound (having, for example, a relative dielectric constant of 3.9), and the spacer 302 is made from a material having a lower dielectric constant, such as carbon-doped silicon oxide.
Other embodiments of the disclosed invention may use one or more other materials exclusively or in addition to those recited above, including, and without limitation, oxynitrides, and doped materials, such as carbon-doped oxides, nitrides, and oxynitrides, as well as boron-doped nitrides, oxides, and oxynitrides.
Each embodiment of the disclosed invention is advantageous relative to the prior art because it exhibits a higher dielectric constant on its source side, leading to better drive current; and a lower dielectric constant on its drain side, leading to decreased parasitic capacitance and lower power consumption. Each embodiment further allows for additional space in the trench structures formed between serially positioned transistors by using less spacer material on one or both sides of the gate 104. The additional space can be used to form more reliable contacts during subsequent fabrication steps. This benefit becomes more critical as transistors are scaled down even further, limiting the space available for forming effective and reliable contact regions.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable other of ordinary skill in the art to understand the embodiments disclosed herein. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated but fall within the scope of the appended claims.
Claims
1. A semiconductor device comprising:
- a gate formed on a top surface of a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite the second sidewall;
- a first spacer formed on and adjacent to the first sidewall of the gate, wherein the first spacer is made of a first material; and
- a second spacer formed on and adjacent to the second sidewall of the gate, wherein the second spacer is made of a second material different from the first material.
2. The semiconductor device of claim 1, wherein:
- the first spacer is above and/or proximate to a source region;
- the second spacer is above and/or proximate to a drain region;
- the first spacer is thicker than the second spacer; and
- the first spacer is made from a nitride and the second spacer is made from an oxide.
3. The semiconductor device of claim 1, wherein the first material and/or the second material is selected from the group consisting of oxides, nitrides, oxynitrides, carbon-doped oxides, carbon-doped nitrides, and carbon-doped oxynitrides.
4. The semiconductor device of claim 1, wherein the first material is a nitride and the second material is an oxide.
5. The semiconductor device of claim 1, wherein the first spacer has a higher capacitance than the second spacer.
6. The semiconductor device of claim 1, wherein the first material has a higher dielectric constant than the second material.
7. The semiconductor device of claim 1, wherein the first material is a first oxide and the second material is a second oxide having a lower dielectric constant than the first oxide.
8. The semiconductor device of claim 1, wherein the first spacer and the second spacer have different thicknesses.
9. The semiconductor device of claim 8, wherein the first spacer has a thickness of approximately 10 nanometers and the second spacer has a thickness of approximately 5 nanometers.
10. The semiconductor device of claim 1, wherein the first spacer and the second spacer have substantially equal thicknesses.
11. A semiconductor device comprising:
- a gate formed on a top surface of a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite the second sidewall;
- a first spacer formed on the gate proximate to the first sidewall, wherein the first spacer is made of a first material; and
- a second spacer formed on and adjacent to the second sidewall of the gate, wherein the second spacer is made of a second material different from the first material.
12. The semiconductor device of claim 11, wherein the first material and/or the second material is selected from the group consisting of oxides, nitrides, oxynitrides, carbon-doped oxides, carbon-doped nitrides, and carbon-doped oxynitrides.
13. The semiconductor device of claim 11, wherein the first spacer has a higher capacitance that the second spacer.
14. The semiconductor device of claim 11, wherein the first material has a higher dielectric constant than the second material.
15. The semiconductor device of claim 11, wherein the first spacer and the second spacer have different thicknesses.
16. A method for forming a semiconductor device, comprising:
- forming a gate onto a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite to the second sidewall;
- forming a first film layer on and adjacent to the first sidewall of the gate, wherein the first film layer is made from a first material;
- forming a second film layer made on and adjacent to the second sidewall of the gate, wherein the second film layer is made from a second material different from the first material; and
- shaping the first film layer to form a first spacer and shaping the second film layer to form a second spacer.
17. The method of claim 16, wherein:
- the first spacer is formed above and/or proximate to a source region;
- the second spacer is formed above and/or proximate to a drain region;
- the first spacer is thicker than the second spacer; and
- the first spacer is made from a nitride and the second spacer is made from an oxide.
18. The method of claim 16, wherein the first material and/or the second material are selected from the group consisting of oxides, nitrides, oxynitrides, carbon-doped oxides, carbon-doped nitrides, carbon-doped oxynitrides, and boron-doped oxynitrides.
19. The method of claim 16, wherein the first material is a nitride and the second material is an oxide.
20. The method of claim 16, wherein the first spacer has a higher capacitance than the second spacer.
21. The method of claim 16, wherein the first material has a higher dielectric constant than the second material.
22. The method of claim 21, wherein the first material is a first oxide and the second material is a second oxide having a lower dielectric constant than the first oxide.
23. The method of claim 16, wherein the first spacer is formed to have a greater thickness than the second spacer.
24. The method of claim 23, wherein the first spacer is formed at a thickness of approximately 10 nanometers and the second spacer is formed at a thickness of approximately 5 nanometers.
25. A method for forming a semiconductor device, comprising:
- forming a gate onto a substrate, the gate having a first sidewall and a second sidewall, the first sidewall positioned opposite to the second sidewall;
- forming a first film layer on the gate proximate to the first sidewall, wherein the first film layer is made from a first material;
- forming a second film layer made on and adjacent to the second sidewall of the gate, wherein the second film layer is made from a second material different from the first material; and
- shaping the first film layer to form a first spacer and shaping the second film layer to form a second spacer.
26. The method of claim 25, wherein the first material and/or the second material are selected from the group consisting of oxides, nitrides, oxynitrides, carbon-doped oxides, carbon-doped nitrides, carbon-doped oxynitrides, and boron-doped oxynitrides.
27. The method of claim 25, wherein the first material is a nitride and the second material is an oxide.
28. The method of claim 25, wherein the first spacer has a higher capacitance than the second spacer.
29. The method of claim 25, wherein the first material has a higher dielectric constant than the second material.
30. The method of claim 25, wherein the first spacer is formed to have a greater thickness than the second spacer.
Type: Application
Filed: Mar 29, 2013
Publication Date: Oct 2, 2014
Applicant: International Business Machines Corporation (Armonk, NY)
Inventors: Kangguo Cheng (Schenectady, NY), Ali Khakifirooz (Mountain View, CA), Richard S. Wise (Newburgh, NY)
Application Number: 13/853,090
International Classification: H01L 21/28 (20060101); H01L 29/423 (20060101); H01L 29/78 (20060101);