SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES
Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
This application is a divisional of U.S. patent application Ser. No. 13/526,792, filed Jun. 19, 2012, which is a continuation of U.S. patent application Ser. No. 12/781,681, filed May 17, 2010 (now U.S. Pat. No. 8,211,803, issued Jul. 3, 2012), which is a divisional of U.S. patent application Ser. No. 11/933,664, filed Nov. 1, 2007 (now U.S. Pat. No. 7,737,039, issued Jun. 15, 2010), the entire disclosures of each of which are hereby incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
Embodiments of the invention relate to semiconductor processing and, more particularly, to masking techniques.
2. Description of the Related Art
There is a constant demand to decrease the sizes of integrated circuits. This decrease can be facilitated by reducing the sizes and separation distances between the individual elements or electronic devices forming the integrated circuits. This process of reducing the sizes of features and the separation distances between features can increase the density of circuit elements across a substrate and is typically referred to as “scaling.” As a result of the continuing demand for smaller integrated circuits, there is a constant need for methods and structures for scaling.
The appended drawings are schematic, not necessarily drawn to scale, and are meant to illustrate and not to limit embodiments of the invention.
Embodiments of the invention provide methods of forming patterns of isolated features, such as holes or isolated pillars, having a high density. Advantageously, the holes or isolated pillars can be used to form conductive contacts to various features in integrated circuits. For example, contacts can be made to conductive interconnects having a close spacing, or small pitch, e.g., a pitch of about 60 nm or less, or about 30 nm or less. It will be appreciated that pitch is defined as the distance between an identical point in two neighboring interconnects, which are typically spaced apart by a material, such as an insulator. As a result, pitch may be viewed as the sum of the width of a feature and of the width of the space on one side of the feature separating that feature from a neighboring feature.
It will also be appreciated that interconnects with a small pitch present difficulties for forming contacts. Interconnects with small pitches can be formed by pitch multiplication, such as described in U.S. Pat. No. 7,253,118, issued Aug. 7, 2007, entitled PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES, the entire disclosure of which is incorporated by reference herein. Because of the close spacing between interconnects with small pitches, relatively large contacts can cause shorts between neighboring interconnects. Moreover, the relatively large cross-sectional areas of some contacts make difficult the formation of “on pitch” contacts, that is, contacts with the same pitch as the interconnects. Instead, contacts are typically formed staggered, with odd numbered contacts forming one row and even numbered contacts forming another row of contacts. These staggered contacts use space inefficiently due to their staggered nature and, as a result, present an obstacle to further integrated circuit miniaturization and scaling.
Advantageously, one or more embodiments of the invention allow the formation of contacts that are on pitch. The on pitch contacts advantageously are aligned in a row, allowing for a more efficient use of space. Moreover, the advantageously small sizes of the contacts decrease the occurrence of electrical shorts between neighboring interconnects and neighboring contacts.
The contacts can be patterned using a mask defined or derived from spacers. In some embodiments of the invention, a method is provided for increasing the density of patterned features by a multiple of about 1.5 or more. A row of sacrificial mandrels is formed having a linear density Z. The mandrels can be, e.g., free-standing spacers formed in, e.g., a photoresist layer. Additional mask features are defined between the mandrels by forming spacers at sides of the mandrels. The spacers can be formed by blanket depositing spacer material over the mandrels and then etching the spacer material, thereby forming the spacers at the sides of the mandrels. The mandrels are removed, thereby forming a mask pattern using the spacers, the mask pattern having a density of holes of about 1.5Z or more. The contacts are advantageously transferred to a substrate, to, e.g., define conductive contacts to electrical features such as interconnects. It will be appreciated that the substrate can form various electronic devices, including integrated circuits such as memory devices, including nonvolatile memory such as flash memory.
Reference will now be made to the Figures, in which like numerals refer to like parts throughout.
With continued reference to
In step 13, a second selectively definable layer is provided. The second selectively definable layer can be formed over the spacers and then patterned. It will be appreciated that forming contacts typically entails forming a row of contact features. As a result, in some embodiments, only a row of holes formed by the spacers is transferred to an underlying substrate. The second selectively definable layer is used to block pattern transfer of particular parts of the spacer pattern. For example, the second selectively definable layer can be patterned such that only a single row of holes defined be spacers is exposed for pattern transfer to underlying materials.
With continued reference to
The sequence of
In one or more embodiments, the first hard mask layer 120, also referred to as the primary mask layer, is formed of amorphous carbon, e.g., transparent carbon, which has been found to have excellent etch selectivity with other materials of the illustrated imaging or masking stack. Methods for forming amorphous carbon are disclosed in A. Helmbold, D. Meissner, Thin Solid Films, 283 (1996) 196-203, the entire disclosures of which are hereby incorporated herein by reference. In the illustrated embodiment, a second hard mask layer 122 is also formed over the first hard mask layer 120 to protect the first hard mask layer 120 during etching in later steps and/or to enhance the accuracy of forming patterns by photolithography. In one or more embodiments, the second hard mask layer 122 includes an anti-reflective coating (ARC), such as DARC or BARC/DARC, which can aid photolithography by preventing undesired light reflections.
With continued reference to
With reference to
The selectively definable layer 130 can be patterned using photolithography. Due to limitations of typical optical systems, it will be appreciated that conventional photolithographic methods can have difficulties forming free-standing mandrels 131 in isolation. Advantageously, in some embodiments, the first and second blocks 132, 133 and the features 134 can be used to facilitate formation of the mandrels 131.
In some embodiments, the sizes of the mandrels 131 are substantially equal to the minimum feature size formable using the lithographic technique used to pattern the layer 130. In some other embodiments, the mandrels 131 can be formed larger than the minimum feature size formed by photolithography, in order to enhance the accuracy of the patterns formed by photolithography. It will be appreciated that photolithographic techniques typically can more easily and accurately form features having sizes above the size limit of the technique.
Where the sizes and/or shapes of the mandrels 131 are larger or different from that desired, the mandrels 131 are optionally trimmed. The trim reduces the sizes of the mandrels, in addition to rounding the corners of the mandrels.
With reference to
In some embodiments, the pattern in the selectively definable layer 130 can be transferred to one or more underlying layers before depositing the layer 140 of spacer material. For example, in embodiments where exposure and resistance to high temperatures is desired (e.g., where the material for the layer 140 requires a high temperature deposition), the pattern in the selectively definable layer 130 can be transferred to a more high temperature resistant material before deposition of the layer 140. For example, the pattern can be transferred to an additional underlying layer of sufficiently temperature resistant material.
With continued reference to
In step 9 of
In step 11 of
In step 13 of
In some embodiments, only a single row of holes 150, 152 is desired to form on pitch contacts. As a result, the second selectively definable layer 160 is patterned to allow transfer of only the row of holes 150, 152 to underlying layers. As illustrated, the patterned layer 160 leaves the row of holes 150, 152 exposed for pattern transfer.
In step 15, the pattern defined by the spacers 145 and the second selectively definable layer 160 is transferred to underlying materials, e.g., using anisotropic etches selective for the material forming an underling layer relative to other exposed materials. With reference to
With reference to
With reference to
Optionally, before the pattern transfer to the layer 100a, the mask formed by the primary hard mask layer 120 is cleaned. It will be appreciated that the etch used to transfer the pattern of holes 150, 152 to the primary hard mask layer 120 can cause undesired residue or polymerization. A wet organic strip etch can be used to clean the mask formed by the layer 120 by removing the residue or polymerization product before the pattern transfer to the underlying layer 100a.
It will be appreciated that wet organic strip etches may advantageously be applied to remove various exposed materials, such as carbon-based materials. As discussed herein, these organic strip etches include solvent based chemistries. In other embodiments, the strip etches or cleaning steps may include acidic or basic chemistries, as appropriate for the particular materials present and desired for removal, as known in the art.
With reference to
In step 21 of
In step 23 (
In step 25 (
With reference to
In the illustrated embodiment, with continued reference to
In step 29 of
In step 31 of
In step 33 of
With reference to
Thus, it will be appreciated that, in accordance with the embodiments described above, a method for semiconductor processing is provided. The method comprises providing a row of laterally separated mandrels formed of a mandrel material. The row extends along a first axis. First and second laterally spaced blocks of mandrel material are provided on a same plane as the mandrels. The first and second blocks extend a length of the row, and the mandrels are disposed between the first and second blocks. A layer of spacer material is blanket deposited over the mandrels. The layer of spacer material is anisotropically etched to form spacers on sides of the mandrels. The mandrels are selectively removed relative to the spacer material and the remaining spacer material forms a mask pattern. The mask pattern to the substrate to fauns a row of contact vias in the substrate.
In other embodiments, a method for integrated circuit fabrication is provided. The method comprises providing a row of pillars on a level above a substrate. The pillars have a linear density Z. The row of pillars is replaced with a mask having a row of holes. The mask and holes are disposed on the same level as the pillars. The holes have a width of about 60 nm or less. At least some of the holes are disposed at a location formerly occupied by a pillar. The holes having a linear density at least about 1.5 times Z.
In other embodiments, a partially fabricated integrated circuit is provided. The partially fabricated integrated circuit comprises a plurality of pillars extending on a first axis. First and second laterally spaced blocks formed of the same material as the pillars are provided extending at least between a first and a last of the pillars on the first axis. The pillars are disposed between the first and second blocks. Spacers are disposed on sides of the pillars and on sides of the first and the second blocks.
It will be appreciated by those skilled in the art that various omissions, additions, and modifications may be made to the methods and structures described above without departing from the scope of the invention. All such changes are intended to fall within the scope of the invention, as defined by the appended claims.
Claims
1. An integrated circuit structure, comprising:
- a plurality of pillars extending on a first axis over a substrate;
- first and second laterally spaced blocks formed of the same material as the pillars, the first and second blocks extending at least between a first and a last of the pillars on the first axis, wherein the pillars are disposed between and on the same level as the first and second blocks; and
- spacers disposed on sides of the pillars and on sides of the first and the second blocks.
2. The integrated circuit structure of claim 1, wherein the pillars comprise photoresist.
3. The integrated circuit structure of claim 2, wherein the first and second blocks comprise photoresist.
4. The integrated circuit structure of claim 1, wherein the spacers comprise silicon oxide.
5. The integrated circuit structure of claim 1, further comprising at least one hard mask between the substrate and the pillars, the first block, and the second blocks.
6. The integrated circuit structure of claim 5, wherein the at least one hard mask comprises:
- a first hard mask over the substrate; and
- a second hard mask over the first hard mask layer.
7. The integrated circuit structure of claim 6, wherein the first hard mask comprises amorphous carbon.
8. The integrated circuit structure of claim 7, wherein the second hard mask comprises an anti-reflective coating.
9. The integrated circuit structure of claim 1, wherein the first and second blocks comprise laterally extending fingers extending towards the pillars.
10. The integrated circuit structure of claim 9, wherein the fingers are disposed between pairs of the pillars.
11. The integrated circuit structure of claim 1, wherein the pillars form a row of pillars, wherein only one row of pillars is disposed between the first and the second blocks.
12. The integrated circuit structure of claim 11, wherein a width of each of the pillars is about 60 nm or less.
13. The integrated circuit structure of claim 12, wherein the width of each of the pillars is about 30 nm or less.
14. The integrated circuit structure of claim 12, wherein spacers between pairs of neighboring pillars define an opening between each pair of neighboring pillars.
15. The integrated circuit structure of claim 14, wherein a width of the opening is about 60 nm or less.
16. The integrated circuit structure of claim 15, wherein the width of the opening is about 30 nm or less.
17. The integrated circuit structure of claim 1, wherein a distance between the spacers at the sides of the pillars is about 50 nm or less.
18. The integrated circuit structure of claim 1, further comprising a plurality of conductive interconnects below the spacers and the pillars, the pillars vertically aligned with at least some of the conductive interconnects.
19. The integrated circuit structure of claim 1, wherein the integrated circuit structure is a memory device structure.
20. The integrated circuit structure of claim 19, wherein the memory device structure is a flash memory structure.
Type: Application
Filed: Jun 23, 2014
Publication Date: Oct 9, 2014
Inventors: Gurtej Sandhu (Boise, ID), Mark Kiehlbauch (Boise, ID), Steve Kramer (Boise, ID), John Smythe (Boise, ID)
Application Number: 14/311,696
International Classification: H01L 21/768 (20060101); H01L 23/528 (20060101);