SELF-ALIGNED STRUCTURE FOR BULK FinFET
A FinFET structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped; a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and an oxide formed between the bottom portions of the fins.
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This application is a continuation of U.S. patent application Ser. No. 13/860,832 (Attorney docket no. YOR920120148US1), entitled “SELF-ALIGNED STRUCTURE FOR BULK FinFET”, filed Apr. 11, 2013, the disclosure of which is incorporated by reference herein.
BACKGROUNDThe present invention relates to bulk FinFET devices and, more particularly, relates to bulk FinFET devices having uniform high concentration well doping to block the electrical path between the source and drain and minimize the junction leakage current.
In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETS), which are fabricated using conventional lithographic fabrication methods, nonplanar FETs (Field-Effect Transistors) incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor structure is the “FinFET” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels.
More particularly, a FinFET device generally includes one or more parallel silicon fin structures (or simply “fins”). The fins extend between a common source electrode and a common drain electrode. A conductive gate structure “wraps around” three sides of the fins, and may be separated from the fins by a standard gate insulator layer. Fins may be suitably doped to produce the desired FET polarity, as is known in the art, such that a gate channel is formed within the fins adjacent to the gate insulator.
Fin structures (and thus FinFET devices) may be formed on a semiconductor substrate. The semiconductor substrate may be a silicon on insulator (SOI) wafer. The silicon on insulator (SOI) wafer comprises a silicon-comprising material layer overlying a silicon oxide layer. Fin structures are formed from the silicon-comprising material layer. The SOI wafer is supported by a support substrate which may also be silicon or another semiconducting material.
Alternatively, the semiconductor substrate may be a bulk silicon wafer from which the fin structures are formed. The bulk silicon wafer comprises a monolithic block of single crystal silicon. A FinFET device formed from a bulk silicon wafer is referred to herein as a “bulk FinFET device”.
Electrical isolation between adjacent fins and between the source and drain electrodes of unrelated FinFET devices is needed. “Unrelated” as used herein means that the devices are not intended to be coupled together. Electrical current leakage is a parasitic effect, which degrades performance of an integrated circuit.
BRIEF SUMMARYThe various advantages and purposes of the exemplary embodiments as described above and hereafter are achieved by providing a FinFET structure which includes: a bulk semiconductor substrate; a plurality of semiconductor fins extending from the bulk semiconductor substrate, each of the plurality of semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped; a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and an oxide formed between the bottom portions of the fins.
The features of the exemplary embodiments believed to be novel and the elements characteristic of the exemplary embodiments are set forth with particularity in the appended claims. The Figures are for illustration purposes only and are not drawn to scale. The exemplary embodiments, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:
Referring now to
In
Referring now to
Referring now to
Thereafter, a conformal layer of nitride 116 is deposited over the stripes of amorphous silicon 112, as shown in
The conformal layer of nitride 116 is conventionally etched to form sidewall spacers 118, as shown in
Using the spacers 118 as a mask, the bulk silicon substrate 102 is etched to form silicon fins 120 extending from the bulk silicon substrate 102 and stripes of oxide 122 on the silicon fins 120 as shown in
Referring now to
Referring now to
In a subsequent process flow, the fins 202 will receive a gate structure (not shown) wrapping around the fins 202. Prior to forming of the gate structure, the fins 202 of FinFET structure 200 may be doped as will be described in the following description. Some of the doped fins and gate structures formed thereon may result in N-type FinFETs (NFETS) while others of the doped fins and gate structures may result in P-type FinFETs (PFETS). The present exemplary embodiments are applicable to both NFET and PFET devices.
Referring now to
Referring now to
Thereafter, the oxide 406 is stripped using, for example, a wet etch of dilute hydrofluoric acid (dHF) to result in the structure shown in
The FinFET structure 400 then undergoes an epitaxial process to grow either phosphorous-doped silicon (P-silicon) or boron-doped silicon germanium (B—SiGe) on the exposed portions of the silicon fins 404 and the bulk silicon substrate 402. The FinFET structure 400 is contacted with hydrofluoric acid (HF) to remove native oxide then undergoes a 700 to 800° C. prebake to completely purge out the oxygen on the surface. Once that part is completed, SiH4 (or GeH4) and B2H6 or SiH4 and PH3 is flowed into the chamber at a control temperature of 600° C. for about 800 seconds for the epitaxial process at the surface of the silicon to form either epitaxial P-silicon, B-silicon, or B—SiGe. The epitaxial material 414 is shown in
Referring to
The epitaxial material 414 may be stripped by, for example, hydrochloric acid. The bottom portions 418 of the fins 404 become doped after the drive in of the dopants from the epitaxial material 414. The doped portion of the bulk silicon substrate 402 forms a well indicated by reference number 420. The well may have a thickness of about 30 nm. For a PFET device, P-silicon may be used as the epitaxial material 414 and an n+ well 420 is formed. The bulk silicon substrate 402 is p−. For an NFET device, B-silicon germanium or B-silicon may be used as the epitaxial material 414 and a p+ well 420 is formed. The bulk silicon substrate 402 is p−. For this process step, it doesn't matter whether B-silicon or B-silicon germanium is epitaxially deposited since it is the boron dopant that is of interest; the epitaxial layer is removed in a subsequent process step. For both PFET and NFET devices, the dopant concentration in the bottom portions 418 of the fins 404 and well 420 is about 1×1020 atoms/cm3 while for the bulk silicon substrate 402 the dopant concentration is about 1×1016 atoms/cm3. The actual dopant is boron for the NFET device and phosphorous for the PFET device. Normally, boron would be the dopant for a PFET and phosphorous for the NFET but the reverse (boron for NFET and phosphorous for PFET) is desired for the well doping. The structure thus far is shown in
Referring now to
Further processing may now take place to form a gate structure that wraps around each of the fins 404 and additional conventional semiconductor processing steps to complete the FinFET structure 400.
Referring now to
Referring to
The doping layer 612 may be stripped by, for example, ozone plasma ashing. The bottom portions 616 (in contact with the doping material 612) of the fins 604 become doped after the drive in of the dopants from the doping layer 612. The doped portion of the bulk silicon substrate 602 forms a well indicated by reference number 618. The well may have a thickness of about 30 nm. The FinFET structure may be doped in the same manner as the first exemplary embodiment. The structure thus far is shown in
Referring now to
Further processing may now take place to form a gate structure that wraps around each of the fins 604 and additional conventional semiconductor processing steps to complete the FinFET structure 600.
Referring now to
Subsequently, the bottom portions 808 of the silicon fins 804 have been thinned by exposing the FinFET structure 800 to an etchant that anisotropically etches the exposed silicon. For purposes of illustration and not limitation, the etchant may be an etchant comprising a 25 weight percent solution of potassium hydroxide and water. The FinFET structure 800 is exposed to the etchant for a sufficient time to reduce each exposed silicon surface by about 2 to 3 nanometers (nm). The starting thickness of the silicon fins 804 is about 10 nm and after exposure to the etchant, the thickness of the bottom portion 808 is now about 4 to 6 nm. The surface 810 of the bulk silicon substrate 802 is also reduced by about 2 to 3 nm due to exposure to the silicon etchant.
The FinFET structure 800 then undergoes an epitaxial process to grow either phosphorous-doped silicon (P-silicon), boron-doped silicon germanium (B—SiGe) or boron-doped silicon (B—Si) on the exposed bottom portions 808 of the silicon fins 804 and the bulk silicon substrate 802. The epitaxial process is the same as described previously. The epitaxial material 812 is shown in
The epitaxial material 812 may be stripped by, for example, hydrochloric acid. The bottom portions 808 of the fins 804 become doped after the drive in of the dopants from the epitaxial material 812. The doped portion of the bulk silicon substrate 802 forms a well indicated by reference number 820. The well may have a thickness of about 30 nm. The FinFET structure 800 may be doped in the same manner as the first exemplary embodiment. The structure thus far is shown in
The dummy spacer 806 may be conventionally etched as described previously. Thereafter, another layer of oxide 822 may be deposited by a process such as that used to deposit the oxide 406 in
Further processing may now take place to form the gate structure that wraps around each of the fins 804 and additional conventional semiconductor processing steps to complete the FinFET structure 800.
The exemplary embodiments are advantageous in that uniform high concentration well doping is achieved to block the electrical path between the source and drain and minimize the junction leakage current. The third exemplary embodiment is particularly advantageous in that parasitic capacitance is reduced because the proportion of the channel exposed to the well is less due to the thinning of the fins.
It will be apparent to those skilled in the art having regard to this disclosure that other modifications of the exemplary embodiments beyond those embodiments specifically described here may be made without departing from the spirit of the invention. Accordingly, such modifications are considered within the scope of the invention as limited solely by the appended claims.
Claims
1. A FinFET structure comprising:
- a bulk semiconductor substrate;
- a plurality of semiconductor fins extending from the bulk semiconductor substrate, each of the plurality of semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped;
- a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and
- an oxide formed between the bottom portions of the fins.
2. The FinFET structure of claim 1 wherein the bottom portion of each of the plurality of semiconductor fins is thinned compared to the top portion of the plurality of semiconductor fins.
3. The FinFET structure of claim 2 wherein a parasitic capacitance of the FinFET structure is reduced due to the thinned bottom portion of each of the plurality of semiconductor fins.
4. The FinFET structure of claim 1 wherein the semiconductor fins and bulk semiconductor substrate are silicon.
5. The FinFET structure of claim 1 further comprising a gate that wraps around at least one of the semiconductor fins.
6. The FinFET structure of claim 1 wherein each of the plurality of semiconductor fins has a source and a drain and wherein the well blocks the electrical path between the source and drain and minimizes junction leakage current.
7. The FinFET structure of claim 1 wherein the oxide is only in contact with the bulk semiconductor substrate and the bottom portions of the fins.
8. The FinFET structure of claim 1 wherein the oxide is only in contact with the doped portion of the bulk semiconductor substrate and the doped portion of the fins.
Type: Application
Filed: Aug 30, 2013
Publication Date: Oct 16, 2014
Applicant: International Business Machines Corporation (Armonk, NY)
Inventors: Veeraraghavan S. Basker (Schnectady, NY), Effendi Leobandung (Wappingers Falls, NY), Tenko Yamashita (Schenectady, NY), Chun-Chen Yeh (Clifton Park, NY)
Application Number: 14/015,967
International Classification: H01L 29/78 (20060101);