FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES
Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.
The field of the present disclosure relates to the physical and electrical sciences, and more particularly to electronic devices including chip connections that facilitate compliance of the electronic elements thereof to surface morphology and methods of manufacture thereof.
BACKGROUNDFlexible electronic systems including flexible integrated circuit devices are useful for applications wherein such systems must conform to non-planar surfaces. Conventional electronic components such as complementary metal oxide semiconductor (CMOS) circuits are typically fabricated on rigid substrates. Various schemes have been employed for rendering rigid/stiff materials flexible by thinning/removing the substrate, leaving a relatively thin structure. Such schemes employ, for example, chemical and mechanical polishing and etching, layer lift-off, controlled spalling, and other methods. Despite the flexibility of the structures obtained through such schemes, which is due to the relatively small total thicknesses thereof, the structures are not stretchable, having limited mechanical properties, i.e. fracture toughness, of the overall structure in the other two dimensions. A fabrication method for creating stretchable electronic structures has been proposed that includes making small, thin electronic components using lift-off techniques, transferring small electronic chips to a compliant substrate, and subsequently wiring the chips to one another using serpentine metal wires with low Young's modulus. The relatively small chip sizes make the wiring task in sophisticated systems complicated and challenging due to the large number of required electrical connections.
SUMMARYAspects of the present disclosure relate to flexible electronic structures and methods for fabricating such structures.
A first exemplary method includes forming an electronic circuitry layer having first and second circuitry regions on a semiconductor substrate and forming a separator layer separating the first and second circuitry regions of the circuitry layer on the substrate. The method further includes forming a layer comprising electrically insulating material on the circuitry layer, forming an electrical connector layer between the first and second circuitry regions and extending across the separator layer, and removing the separator layer to form a space beneath the electrical connector layer, the space further separating the first and second circuitry regions of the circuitry layer.
A second exemplary method includes obtaining a structure including i) a semiconductor substrate, ii) a circuitry layer comprising first and second circuitry regions deposited on the substrate, the circuitry layer comprising CMOS devices, iii) a separator layer on the substrate that separates the first and second circuitry regions of the circuitry layer, iv) a layer comprising electrically insulating material on the circuitry layer, and v) an electrical connector layer between the first and second circuitry regions and extending across the sacrificial separator layer. The exemplary method further includes thinning the substrate, removing the sacrificial separator layer to form a space above the substrate and beneath the electrical connector layer, and affixing the substrate to a flexible layer.
An exemplary structure includes a semiconductor substrate including an electrically insulating layer, a circuitry layer including first and second CMOS circuitry regions formed on the substrate and adjoining the electrically insulating layer, and a first layer comprising electrically insulating material on the circuitry layer. A separator layer is on the substrate and within the first layer. The separator layer electrically isolates the first and second CMOS circuitry regions. An electrical connector layer electrically connects the first and second circuitry regions. The electrical connector layer is formed within the first layer and extends across the separator layer.
As used herein, “facilitating” an action includes performing the action, making the action easier, helping to carry the action out, or causing the action to be performed. Thus, by way of example and not limitation, instructions executing on one processor might facilitate an action carried out by instructions executing on a remote processor, by sending appropriate data or commands to cause or aid the action to be performed. For the avoidance of doubt, where an actor facilitates an action by other than performing the action, the action is nevertheless performed by some entity or combination of entities.
Substantial beneficial technical effects are provided by the exemplary structures and methods disclosed herein. For example, one or more embodiments may provide one or more of the following advantages:
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- Enables flexible, stretchable electronic structures;
- Electrical connections formed by deposition and patterning as opposed to bonding or soldering;
- Facilitates providing multiple levels of intra-chip electrical connections;
- Monolithic integration of the intrachip connectors facilitates the integration process.
These and other features and advantages of the present disclosure will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable. The flexibility of an electronic structure, such as an integrated circuit, allows it to bend to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. An electronic structure that is also stretchable exhibits tensile strength and can be stretched or squeezed within acceptable limits without failing or breaking The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) in one or more exemplary embodiments and released following transfer of the electronic structure to a flexible substrate.
The fabrication methods and electronic structures disclosed herein are amenable to various CMOS manufacturing techniques familiar to those of skill in the art. It will be appreciated, however, that techniques that vary in some respects from those disclosed herein may be employed for forming other types of electronic devices that benefit from being flexible and stretchable. Referring to
In one exemplary embodiment, the substrate 20 is employed in the fabrication of an electronic structure as shown in
An exemplary CMOS process sequence for fabricating a field effect transistor includes: 1) device isolation (silicon removal to form silicon “islands” defining the device active region and filling trenches formed with dielectric material such as silicon dioxide); 2) gate stack and spacer formation; 3) source/drain formation; 4) silicide formation to form contacts to various device electrodes, and 5) middle and back end of the line metallization steps. Referring again to
A separator layer 40 is formed directly on the substrate. While shown on the insulating layer 24 of the substrate, the separator layer can extend beyond the insulating layer and inside the silicon handle layer 22. A layer 38 of electrically insulating material is formed on the substrate over the circuitry layer 34 and contact layer 36. The layer 38 may be comprised of silicon dioxide, silicon nitride or other suitable materials. In some embodiments, the insulating (BOX) layer 24 and layer 38 are comprised of materials that can be selectively etched with respect to one another. In other embodiments, they are both comprised of the same material, silicon dioxide being one exemplary material. The spacing between chips, which corresponds to the width (Lspace) of the separator layer 40, may be based at least in part on the extent to which the structure obtained by the fabrication process is intended to stretch or contract. While shown as distinct elements for purpose of explanation, the layer 38 of insulating material and the separator layer 40 may, at least in part, be comprised of the same material(s) and formed simultaneously. They may alternatively be formed from different materials to facilitate selective etching. As discussed below, the separator layer 40 is selectively etched with respect to the layer 38 and is accordingly shown as a separate element. In some embodiments, the separator layer includes layers that are not present within the layer 38 of insulating material. The layer 38 of insulating material and the separator layer 40 are formed such that the separator layer is positioned within the layer 38 of insulating material and between the circuitry regions 34A, 34B.
Metallization is a further step in back end of the line processing, as known to those of skill in the art. The metallization step(s) primarily involve deposition, patterning and etching. In an exemplary embodiment, the layer 38 of insulating material is deposited on the substrate, the layer is patterned using a via mask, and vias are formed in the layer using an appropriate etching process such as plasma etching. A layer of metal such as copper or aluminum is deposited over the entire substrate. Using photolithographic techniques, the metal layer is selectively etched. In some embodiments, the metal layers can be formed using electrochemical processes such as electroplating. A first metal layer 42A is accordingly formed in the chip regions, as shown in the exemplary embodiment of
The separator layer is comprised entirely of sacrificial, selectively etchable material(s) in some embodiments and comprises a multi-layer stack of different materials in other embodiments. For example, one or more layers of the separator layer may comprise a low-k dielectric material having a relatively low modulus of elasticity (Young's modulus). Other layer(s) of the separator layer that are intended to be sacrificial may comprise a material having a relatively high Young's modulus such as silicon dioxide (SiO2). The low-k dielectric material is formed on a sacrificial layer in the region containing the wires 44. In such embodiments, the layer(s) of low-k dielectric material is deposited, patterned and etched to form vias. Prior to filling the vias with an electrically conductive material such as copper, a high-k dielectric material is deposited such that the side walls of the vias are coated with the high-k dielectric material. The high-k dielectric material will accordingly coat the metal wires formed during the subsequent metallization process. Hafnium oxide is an exemplary high-k dielectric material suitable for this process.
A further alternative embodiment of a structure formed in the manner described above is illustrated in
The thickness of the relatively rigid handle layer 22 is reduced once a structure such as shown in
Removal of the residual layer 56, for example by etching, without removing the separator layer 40 from the structure shown in
Layers of different materials are deposited on the insulating layer 24 in some embodiments for forming the separator layer 40. In one exemplary embodiment, sacrificial material such as silicon dioxide is initially deposited on the insulating layer 24. Silicon dioxide has a large Young's modulus. A material having a relatively low modulus of elasticity (Young's modulus), substantially lower than that of silicon dioxide, is deposited on the sacrificial portion of the separator layer. This allows the wires (e.g. wires 44, 144) to be formed on and/or within a layer 62 of low-k dielectric material. Examples of low-k dielectrics include spin-on organic low-k polymers such as polyimide, polynorborenes, benzocyclobuten, and PTFE. Removal of the residual layer 56 and the separator layer 40 from such a structure provides a structure as shown in
Referring to
In an alternative embodiment as shown in
In another exemplary embodiment, a structure as shown in
Given the discussion thus far, an exemplary structure has a semiconductor substrate including an electrically insulating layer 24 and a circuitry layer comprising first and second CMOS circuitry regions 34A, 34B formed on the substrate and adjoining the electrically insulating layer. A first layer 38 comprising electrically insulating material adjoins the circuitry layer. A separator layer 40 within the first layer electrically isolates the first and second CMOS circuitry regions. An electrical connector layer electrically connects the first and second circuitry regions. The electrical connector layer is formed within the first layer and extends across the separator layer. A further exemplary structure is obtained by removing the separator layer, leaving the electrical connector layer in place. As shown, for example, in
A first exemplary method includes forming an electronic circuitry layer 34 having first and second circuitry regions 34A, 34B on a semiconductor substrate 20. A separator layer 40 is formed on the substrate that separates the first and second circuitry regions. A layer 38 comprising electrically insulating material is formed on the circuitry layer. An electrical connector layer, including for example wires 44, 144 or 244, is formed between the first and second circuitry regions and extends across the separator layer. The separator layer 40 is removed to form a space 60 beneath the electrical connector layer. The space 60 separates the first and second circuitry regions of the circuitry layer 34. In some embodiments, the wires are suspended in air following formation of the space 60. In other embodiments, the wires are embedded in a material having a low Young's modulus.
A second exemplary method includes obtaining a structure including a semiconductor substrate 20, a circuitry layer 34 comprising first and second circuitry regions 34A, 34B deposited on the substrate, the circuitry layer comprising CMOS devices, a separator layer 40 on the substrate that separates the first and second circuitry regions of the circuitry layer, a layer comprising electrically insulating material on the circuitry layer, one or more metal layers within the electrically insulating material, and an electrical connector layer 44, 144, 244 between the first and second circuitry regions and extending across the sacrificial separator layer. The exemplary method further includes thinning the substrate, removing at least part of the separator layer to form a space 60 beneath the electrical connector layer and within the layer comprising electrically insulating material, and affixing the substrate to a flexible layer. In one or more embodiments, the step of removing at least part of the separator layer 40 is performed subsequent to affixing the substrate to the flexible layer.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Terms such as “top” and “bottom” are used to designate relative positions of elements as opposed to elevation. For example, the “top” surface of a structure can face up, down, or any other direction.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims
1. A method comprising:
- forming an electronic circuitry layer having at least first and second circuitry regions on a semiconductor substrate;
- forming a separator layer separating the first and second circuitry regions of the circuitry layer on the substrate;
- forming a layer comprising electrically insulating material on the circuitry layer;
- forming one or more metal layers in the layer comprising the electrically insulating material;
- forming an electrical connector layer extending across the separator layer using deposition and patterning techniques, and
- removing at least part of the separator layer to form a space beneath the electrical connector layer, the space further separating the first and second circuitry regions of the circuitry layer.
2. The method of claim 1, wherein the electronic circuitry layer comprises a plurality of CMOS devices.
3. The method of claim 2, further including the step of thinning the substrate prior to removing at least part of the separator layer.
4. The method of claim 3, further including the step of affixing the substrate to a flexible polymeric layer subsequent to the steps of thinning the substrate and forming the electrical connector layer.
5. The method of claim 4, wherein the step of removing at least part of the separator layer is performed subsequent to affixing the substrate to the flexible polymeric layer.
6. The method of claim 4, further including the step of forming a plurality of electrical connector layers extending across the separator layer at a plurality of levels using deposition and patterning techniques prior to the step of affixing the substrate to the flexible polymeric layer.
7. The method of claim 1, further including the step of forming etch stop layers in the substrate, the first and second circuitry regions being formed directly above the etch stop layers, and wherein the step of removing the separator layer includes etching a selected portion of the substrate within the etch stop layers and etching the separator layer.
8. The method of claim 1, wherein the step of forming the separator layer further includes forming a sacrificial layer and a layer of low-k dielectric material on the sacrificial layer, the low-k dielectric material having a substantially lower Young's modulus than that of the sacrificial layer, and further wherein the electrical connector layer comprises one or more electrical conductors formed at least partially within the layer of low-k dielectric material.
9. The method of claim 8, further including the steps of forming vias within the layer of low-k dielectric material, depositing a layer of high-k insulating material within the vias, and depositing metal within the vias, the metal deposited within the vias comprising at least part of the electrical connector layer.
10. The method of claim 9, wherein the electronic circuitry layer comprises a plurality of CMOS devices, further including the steps of thinning the substrate prior to removing the separator layer and affixing the substrate to a flexible polymeric layer subsequent to the steps of thinning the substrate and forming the electrical connector layer.
11. A method comprising:
- obtaining a structure comprising a semiconductor substrate, a circuitry layer comprising first and second circuitry regions deposited on the substrate, the circuitry layer comprising CMOS devices, a separator layer on the substrate that separates the first and second circuitry regions of the circuitry layer, a layer comprising electrically insulating material on the circuitry layer, one or more metal layers within the electrically insulating material, and an electrical connector layer between the first and second circuitry regions and extending across the sacrificial separator layer;
- thinning the substrate;
- removing at least part of the separator layer to form a space beneath the electrical connector layer and within the layer comprising electrically insulating material, and
- affixing the substrate to a flexible layer.
12. The method of claim 11, wherein the step of removing at least part of the separator layer is performed subsequent to affixing the substrate to the flexible layer.
13. The method of claim 11, wherein the structure includes a plurality of electrical connector layers extending across the separator layer at a plurality of levels.
14. The method of claim 11, wherein the structure further includes etch stop layers in the substrate, the first and second circuitry regions being located directly above the etch stop layers, and wherein the step of removing at least part of the separator layer includes etching a selected portion of the substrate within the etch stop layers and etching the separator layer.
15. The method of claim 11, wherein the separator layer further includes a layer of sacrificial material and a layer of low-k dielectric material on the layer of sacrificial material, the low-k dielectric material having a substantially lower Young's modulus than that of the layer of sacrificial material, and further wherein the electrical connector layer comprises one or more electrical conductors at least partially within the layer of low-k dielectric material.
16. The method of claim 11, wherein the substrate includes a silicon handle layer and a buried oxide layer on the handle layer, and further wherein the step of thinning the substrate includes thinning the handle layer.
17. The method of claim 11, wherein the electrical connector layer of the structure is at least partially embedded within the separator layer, and further wherein the step of at least partially removing the separator layer causes the electrical connector layer to no longer remain embedded within the separator layer.
18. A structure comprising:
- a semiconductor substrate including an electrically insulating layer;
- a circuitry layer comprising first and second CMOS circuitry regions formed on the substrate and adjoining the electrically insulating layer;
- a first layer comprising electrically insulating material on the circuitry layer;
- a separator layer on the substrate and within the first layer, the separator layer electrically isolating the first and second CMOS circuitry regions;
- an electrical connector layer electrically connecting the first and second circuitry regions, the electrical connector layer being formed within the first layer and extending across the separator layer.
19. The structure of claim 18, wherein the separator layer comprises a sacrificial layer adjoining the substrate and a second layer on the sacrificial layer, the second layer having a substantially lower Young's modulus than the sacrificial layer, the electrical connector layer adjoining the second layer.
20. The structure of claim 18, further including a first and second etch stop regions within the substrate, the first CMOS circuitry region being positioned over the first etch stop region and the second CMOS circuitry region being positioned over the second etch stop region, the separator layer being positioned over a portion of the substrate between the first and second etch stop regions.
Type: Application
Filed: Jun 13, 2013
Publication Date: Dec 18, 2014
Inventors: Stephen W. Bedell (Wappingers Falls, NY), Wilfried E. Haensch (Somers, NY), Bahman Hekmatshoartabari (White Plains, NY), Ghavam G. Shahidi (Pound Ridge, NY), Davood Shahrjerdi (White Plains, NY)
Application Number: 13/917,302
International Classification: H01L 27/12 (20060101); H01L 21/762 (20060101);