PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF
A manufacturing method of a package carrier includes the following steps. Two base metal layers are bonded together. Two supporting layers are laminated onto the base metal layers respectively. Two release metal films are disposed on the supporting layers respectively. Each release metal film includes a first metal film and a second metal film separable from each other. Two first patterned metal layers are formed on the release metal films respectively. Each first patterned metal layer includes a pad pattern. Two dielectric layers are formed on the release metal films respectively and cover the corresponding first patterned metal layers. Each dielectric layer has a conductive via connecting to the corresponding pad pattern. Two second patterned metal layers are formed on the dielectric layers respectively. Each second patterned metal layer at least covers the conductive via. The base metal layers are separated from each other to form two independent package carriers.
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This application claims the priority benefit of Taiwan application serial no. 102135022, filed on Sep. 27, 2013. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates to a package structure and a manufacturing method thereof. More particularly, the invention relates to a package carrier and a manufacturing method thereof.
2. Description of Related Art
Chip package is used for the purpose of protecting an exposed chip, reducing the density of chip contacts, and providing better heat dissipation for the chip. Common methods for disposing a chip to a package carrier include wire bonding and flip chip bonding, etc., by which contacts of the chip can be electrically connected to the package carrier. Therefore, the distribution of the chip contacts can be reconfigured by the package carrier to conform to the contact distribution of an external device at the next level.
Generally speaking, fabrication of the package carrier is to use a core dielectric layer as core material and then alternately stack patterned circuit layers and patterned dielectric layers on the core dielectric layer by means of a fully additive process, a semi-additive process, a subtractive process, or other processes. Consequently, the core dielectric layer is a large proportion in the whole thickness of the package carrier. Naturally, if the thickness of the core dielectric layer cannot be significantly reduced, it will be difficult to reduce the thickness of the package structure.
SUMMARY OF THE INVENTIONThe invention provides a package carrier capable of carrying a chip, and the thickness of a package structure utilizing the package carrier is reduced package thickness.
The invention further provides a manufacturing method for manufacturing the aforementioned package carrier.
The manufacturing method of the package carrier of the invention includes the following steps: first, two base metal layers are bonded together. Then, two supporting layers are laminated onto the two base metal layers respectively. Thereafter, two release metal films are disposed on the two supporting layers respectively, wherein each of the release metal films includes a first metal film and a second metal film that are separable from each other. Next, two first patterned metal layers are formed on the two release metal films respectively. Each of the first patterned metal layers includes a pad pattern. Following that, two dielectric layers are formed on the two release metal films respectively and cover the corresponding first patterned metal layers. Each of the dielectric layers has a conductive via respectively connecting to the corresponding pad pattern. Then, two second patterned metal layers are formed on the two dielectric layers respectively. Each of the second patterned metal layers at least covers a top surface of the corresponding conductive via. Thereafter, the two base metal layers are separated to form two package carriers that are independent from each other.
A package carrier of the invention is capable of carrying a chip, and the package carrier includes a supporting layer, a base metal layer, a release metal film, a first patterned metal layer, a dielectric layer, and a second patterned metal layer. The supporting layer has a first surface and a second surface opposite to the first surface. The base metal layer is disposed on the first surface of the supporting layer. The release metal film is disposed on the second surface of the supporting layer. The release metal film includes a first metal film and a second metal film that are separable from each other, wherein the second metal film is bonded to the supporting layer. The first patterned metal layer is disposed on the release metal film and includes at least one pad pattern. The dielectric layer is disposed on the release metal film and covers the first patterned metal layer. The dielectric layer has at least one conductive via connecting to the corresponding pad pattern. The second patterned metal layer is disposed on the dielectric layer and at least covers a top surface of the corresponding conductive via. The chip is adapted to be disposed on the second patterned metal layer and electrically connected thereto.
Based on the above, the package carriers of the invention are formed by performing the manufacturing method respectively on two bonded base metal layers in a symmetrical way. Thus, after stacking layers are respectively formed on the base metal layers, the bonded base metal layers are separated from each other to obtain two independent package carriers, which effectively saves production time and improves production efficiency. In addition, the dielectric layers are laminated onto the supporting layers and conductive vias and patterned metal layers are formed on the dielectric layers so as to form the stacking layers for carrying and electrically connecting the chips. Moreover, the release metal films are connected between the supporting layers and the patterned metal layers, such that the supporting layers can be easily removed due to the separable characteristics of the release metal films. Therefore, in comparison with the traditional package carrier, the package carrier of the invention helps to reduce the overall thickness of the package structure utilizing the package carrier.
To make the aforementioned and other features and advantages of the invention more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Then, with reference to
Next, with reference to
In addition, in an embodiment of the invention, two etch-stop layers 140, as shown in
Then, with reference to
Next, with reference to
Moreover, in this embodiment, two surface treatment layers 172, as shown in
Of course, in other embodiments, the second patterned metal layers 170 may also be formed by a subtractive process, such as etching, etc. To be more specific, if the width of each circuit of each second patterned metal layer 170 is equal to or greater than 35 μm, for example, a forming method of the second patterned metal layer 170 may, for example, include the following steps: first, two second metal layers are respectively formed on the two dielectric layers 160, wherein each of the second metal layers covers the corresponding dielectric layer 160 entirely. Then, two patterned photoresist layers are formed respectively on the two second metal layers, wherein each of the patterned photoresist layers covers a portion of the corresponding second metal layer and the top surface of the corresponding conductive via 162. Next, the portions of the two second metal layers, not covered by the two patterned photoresist layers, are removed so as to form the second patterned metal layers 170. Of course, it should be understood that this disclosure is not intended to limit the forming method and circuit width of the second patterned metal layer 170 of the invention.
In addition, in this embodiment, two surface treatment layers 172 may be respectively formed on the second metal layers before the patterned photoresist layers are formed on the second metal layers. In this embodiment, the surface treatment layer 172 may include an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel-palladium-gold layer, a chemical plated nickel-palladium-gold layer or an organic solderability preservatives (OSP) layer. However, it should be noted that the invention is not limited thereto. Thereafter, the subsequent patterning processes are performed on the second metal layers as well as the surface treatment layers 172, so as to form the second patterned metal layers 170 and the surface treatment layers 172, as shown in
Then, with reference to
Here, it needs to be mentioned that the package carrier 100 of this embodiment illustrates the manufacturing method of stacking single dielectric layer, however, this disclosure is not intended to limit the number of the stacked layers of the package carrier 100. Persons with ordinary skill in the art would be able to modify and adjust the number of the stacked layers of the package carrier 100 to meet the requirements of the products. Moreover, since the package carriers are manufactured in a symmetrical manner in this embodiment, two independent package carriers can be obtained simultaneously after separation (i.e. after separating the two base metal layers 110), which effectively saves production time and improves production efficiency.
Then, as shown in
In this embodiment, the etch-stop layer 140 is formed on the release metal film 130 before the formation of the first patterned metal layer 150. That is to say, the etch-stop layer 140 is disposed between the first patterned metal layer 150 and the release metal film 130. Therefore, when the etching process is performed to remove the remaining release metal film 130, the etching process would be stopped by the etch-stop layer 140 so that the first patterned metal layer 150 would not be subjected to damage. Finally, the etch-stop layer 140 is removed so as to form a package structure 10, as illustrated in
First, with reference to
In sum, the package carriers of the invention are formed by performing the manufacturing method respectively on two bonded base metal layers in a symmetrical way. Thus, after the manufacturing processes are completed, the bonded base metal layers can be separated to obtain two independent package carriers, which effectively saves production time and improves production efficiency. In addition, the invention laminates the dielectric layers onto the supporting layers and forms conductive vias and patterned metal layers on the dielectric layers so as to form the stack layers for carrying and electrically connecting the chips. Moreover, the release metal films are connected between the supporting layers and the patterned metal layers, such that the supporting layers can be easily removed due to the separation characteristics of the release metal films after the molding process. In comparison with the traditional package carrier that is formed by alternately stacking multiple patterned circuit layers and patterned dielectric layers on the core dielectric layer, the package carrier of the invention helps to reduce the overall thickness of the package structure utilizing the package carrier. Therefore, the invention not only effectively saves production time and improves production efficiency but also decreases the overall thickness of the package structure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention covers modifications and variations of this disclosure provided that they fall within the scope of the following claims and their equivalents.
Claims
1. A manufacturing method of a package carrier, comprising:
- bonding two base metal layers to each other;
- laminating two supporting layers onto the two base metal layers respectively;
- disposing two release metal films on the two supporting layers respectively, wherein each of the release metal films comprises a first metal film and a second metal film that are separable from each other;
- forming two first patterned metal layers on the two release metal films respectively, wherein each of the first patterned metal layers comprises at least one pad pattern;
- forming two dielectric layers on the two release metal films respectively and covering the corresponding first patterned metal layers, wherein each of the dielectric layers comprises at least one conductive via respectively connecting the corresponding pad pattern;
- forming two second patterned metal layers on the two dielectric layers respectively, wherein each of the second patterned metal layers at least covers a top surface of the corresponding conductive via; and
- separating the two base metal layers from each other to form two package carriers independent from each other.
2. The manufacturing method as claimed in claim 1, wherein a thickness of the second metal film is substantially greater than a thickness of the first metal film.
3. The manufacturing method as claimed in claim 1, wherein the step of each of the dielectric layers comprising the at least one conductive via comprises:
- forming at least one via on each of the dielectric layers, wherein each of the at least one via exposes the corresponding pad pattern; and
- forming a conductive layer in each of the at least one via to form the at least one conductive via on each of the dielectric layers.
4. The manufacturing method as claimed in claim 3, wherein a method of forming the conductive layer in each of the at least one via comprises chemical plating or electroplating.
5. The manufacturing method as claimed in claim 1, wherein the step of forming the two second patterned metal layers respectively on the two dielectric layers comprises:
- forming two patterned photoresist layers respectively on the two dielectric layers, wherein each of the patterned photoresist layers exposes a portion of the corresponding dielectric layer and the corresponding conductive via;
- forming the two second patterned metal layers respectively on the exposed portions of the two dielectric layers by using the two patterned photoresist layers as masks; and
- removing the two patterned photoresist layers.
6. The manufacturing method as claimed in claim 5, wherein a thickness of each of the second patterned metal layers is substantially in a range of 15 μm to 35 μm.
7. The manufacturing method as claimed in claim 1, wherein the step of forming the two second patterned metal layers respectively on the two dielectric layers comprises:
- forming two second metal layers respectively on the two dielectric layers;
- forming two patterned photoresist layers respectively on the two second metal layers, wherein each of the patterned photoresist layers covers a portion of the corresponding second metal layer and the corresponding conductive via; and
- removing portions of the two second metal layers, which are not covered by the two patterned photoresist layers, to form the two second patterned metal layers on the two dielectric layers.
8. The manufacturing method as claimed in claim 7, wherein a thickness of each of the second patterned metal layers is substantially equal to or greater than 35 μm.
9. The manufacturing method as claimed in claim 1, further comprising:
- forming two etch-stop layers respectively on the two release metal films before respectively forming the two first patterned metal layers on the two release metal films.
10. The manufacturing method as claimed in claim 9, wherein the two etch-stop layers comprise electroplating nickel layers.
11. The manufacturing method as claimed in claim 1, further comprising:
- forming two patterned solder mask layers respectively on the two dielectric layers and exposing the corresponding second patterned metal layers after respectively forming the two second patterned metal layers on the two dielectric layers.
12. The manufacturing method as claimed in claim 1, further comprising:
- forming two surface treatment layers respectively on the two second patterned metal layers after respectively forming the two second patterned metal layers on the two dielectric layers.
13. The manufacturing method as claimed in claim 12, wherein each of the surface processing layers comprises an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel-palladium-gold layer, a chemical plated nickel-palladium-gold layer or an organic solderability preservatives (OSP) layer.
14. A package carrier, capable of carrying a chip, comprising:
- a supporting layer having a first surface and a second surface opposite to the first surface;
- a base metal layer disposed on the first surface of the supporting layer;
- a release metal film disposed on the second surface of the supporting layer and comprising a first metal film and a second metal film that are separable from each other, wherein the second metal film is bonded to the supporting layer;
- a first patterned metal layer disposed on the release metal film and comprising at least one pad pattern;
- a dielectric layer disposed on the release metal film and covering the first patterned metal layer, wherein the dielectric layer has at least one conductive via connecting to the corresponding pad pattern; and
- a second patterned metal layer disposed on the dielectric layer and at least covering a top surface of the corresponding conductive via, wherein the chip is adapted to be disposed on and electrically connected to the second patterned metal layer.
15. The package carrier as claimed in claim 14, wherein a thickness of the second metal film is substantially greater than a thickness of the first metal film.
16. The package carrier as claimed in claim 14, further comprising an etch-stop layer disposed between the release metal film and the patterned metal layer.
17. The package carrier as claimed in claim 16, wherein the etch-stop layer comprises an electroplated nickel layer.
18. The package carrier as claimed in claim 14, further comprising a surface processing layer covering a top surface of the patterned metal layer.
19. The package carrier as claimed in claim 18, wherein the surface processing layer comprises an electroplated gold layer, an electroplated silver layer, a reduced gold layer, a reduced silver layer, an electroplated nickel-palladium-gold layer, a chemical plated nickel-palladium-gold layer or an organic solderability preservatives (OSP) layer.
20. The package carrier as claimed in claim 14, further comprising a solder mask layer disposed on the dielectric layer and exposing the second patterned metal layer.
Type: Application
Filed: Dec 5, 2013
Publication Date: Apr 2, 2015
Patent Grant number: 9578750
Applicant: SUBTRON TECHNOLOGY CO., LTD. (Hsinchu County)
Inventor: Shih-Hao Sun (Hsinchu County)
Application Number: 14/097,269
International Classification: H05K 1/02 (20060101); H05K 3/00 (20060101);