Semiconductor device having SiO.sub.x N.sub.y gate insulating film

In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface. Hydrogen is introduced into the active layer. A thin film comprising SiO.sub.x N.sub.y is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiO.sub.x N.sub.y. Also, a thin film comprising SiO.sub.x N.sub.y is formed under the active layer. The active layer includes a metal element at a concentration of 1.times.10.sup.15 to 1.times.10.sup.19 cm.sup.-3 and hydrogen at a concentration of 2.times.10.sup.19 to 5.times.10.sup.21 cm.sup.-3.

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Claims

1. A semiconductor device comprising:

a first thin film comprising SiO.sub.x N.sub.y formed on a substrate;
an active layer comprising a silicon film, formed on the first thin film;
a gate insulating film comprising a silicon oxide film, formed over the active layer; and
a second thin film comprising SiO.sub.x N.sub.y formed between the active layer and the gate insulating film.

2. The device of claim 1 wherein the active layer includes a metal element for promoting crystallization at a concentration of 1.times.10.sup.15 to 1.times.10.sup.19 cm.sup.-3 and oxygen at a concentration of 2.times.10.sup.19 to 5.times.10.sup.21 cm.sup.-3.

3. The device of claim 2 wherein the metal element includes nickel.

4. The device of claims 1 wherein the first and second thin films include chlorine at a concentration of 1.times.10.sup.15 to 1.times.10.sup.20 cm.sup.-3.

5. The device of claim 4 wherein the active layer includes a metal element for promoting crystallization at a concentration of 1.times.10.sup.15 to 1.times.10.sup.19 cm.sup.-3 and oxygen at a concentration of 2.times.10.sup.19 to 5.times.10.sup.21 cm.sup.-3.

6. A semiconductor device comprising:

a substrate having a first insulating film comprising silicon, oxygen and nitrogen;
a semiconductor layer formed on said first insulating film, said semiconductor layer including source, drain and channel regions;
a second insulating film comprising silicon, oxygen and nitrogen formed on said semiconductor layer; and
a gate electrode over said semiconductor layer with said second insulating film interposed therebetween.

7. A semiconductor device according to claim 6 wherein said gate electrode comprises doped silicon.

8. A semiconductor device according to claim 6 wherein said gate electrode comprises metal.

9. A semiconductor device according to claim 6 further comprising a silicon oxide film interposed between said second insulating film and said gate electrode.

10. A semiconductor device according to claim 6 wherein said semiconductor layer comprises silicon.

Referenced Cited
U.S. Patent Documents
4633284 December 30, 1986 Hansell et al.
5147826 September 15, 1992 Liu et al.
5275851 January 4, 1994 Fonash et al.
5311040 May 10, 1994 Hiramatsu et al.
5313075 May 17, 1994 Zhang et al.
5563426 October 8, 1996 Zhang et al.
5569936 October 29, 1996 Zhang et al.
Other references
  • A.V. Dvurechenskii et al., "Transport Phenomena in Amorphous Silicon Doped by Ion Implantation of 3d Metals", Akademikian Lavrentev Prospekt 13, 630090 Novosibirsk 90, USSR, pp. 635-640, 1990. T. Hempel et al., "Needle-Like Crystallization of Ni Doped Amorphous Silicon Thin Films", Solid State Communications, vol. 85, No. 11, pp. 921-924, 1993. "Crystallized Si Films By Low-Temperature Rapid Thermal Annealing of Amorphous Silicon", R. Kakkad, J. Smith, W.S. Lau, S.J. Fonash, J. Appl. Phys. 65 (5), Mar. 1, 1989, 1989 American Institute of Physics, pp. 2069-2072. "Polycrystalline Silicon Thin Film Transistors on Corning 7059 Glass Substrates Using Short Time, Low Temperature Processing", G. Liu, S.J. Fonash, App. Phys. Lett. 62 (20), May 17, 1993, 1993 American Institute of Physics, pp. 2554-2556. "Selective Area Crystallization of Amorphous Silicon Films by Low-Temperature Rapid Thermal Annealing", Gang Liu and S.J. Fonash, Appl. Phys. Lett. 55 (7), Aug. 14, 1989, American Institute of Physics, pp. 660-662. "Low Temperature Selective Crystallization of Amorphous Silicon", R. Kakkad, G. Liu, S.J. Fonash, Journal of Non-Crystalline Solids, vol. 115, (1989), pp. 66-68.
Patent History
Patent number: 5894138
Type: Grant
Filed: Feb 5, 1998
Date of Patent: Apr 13, 1999
Inventor: Satoshi Teramoto (Atsugi-shi, Kanagawa-ken 243)
Primary Examiner: Minh Loan Tran
Attorneys: Sixbey, Friedman, Leedom & Ferguson, PC, Sixbey, Friedman, Leedom & Ferguson, PC
Application Number: 9/19,295