Vertical Transistor Patents (Class 257/302)
  • Patent number: 11302697
    Abstract: A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: April 12, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Andrew J. Walker, Dafna Beery, Peter Cuevas, Amitay Levi
  • Patent number: 11239369
    Abstract: A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: February 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 11227865
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device can be a recessed access device (RAD) transistor, which includes a substrate, a word line disposed in the substrate and surrounded by a dielectric liner, an isolation layer disposed in the substrate to cap the word line, and an insulative plug penetrating through the isolation layer and extending into the word line.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: January 18, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Wei Huang
  • Patent number: 11227932
    Abstract: Aspects of the disclosure provide a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11189721
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: November 30, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Sameer Pendharkar, Guru Mathur
  • Patent number: 11183629
    Abstract: A method for fabricating an electronic device comprising a semiconductor memory is described. The method comprises forming material layers over a substrate; forming a hard mask pattern over the material layers, the hard mask pattern including an amorphous carbon layer; forming a capping protective layer including a portion on sidewalls of the hard mask pattern; and etching the material layers using the hard mask pattern as an etch barrier.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Ga-Young Ha
  • Patent number: 11164876
    Abstract: Systems, apparatuses, and methods related to atom implantation for passivation of pillar material are described. An example apparatus includes a pillar of a semiconductor device. The pillar may include a first portion (e.g., a passivation material) formed from silicon nitride and an underlying second portion formed from a conductive material. A region of the first portion opposite from an interface between the first portion and the underlying second portion may be implanted with atoms of an element different from silicon (Si) and nitrogen (N) to enhance passivation of the implanted region.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Russell A. Benson
  • Patent number: 11158627
    Abstract: Disclosed is an electronic circuit. The electronic circuit includes a first transistor device and a clamping circuit. The first transistor device includes a control node and a load path between a first load node and a second load node, and the clamping circuit includes a second transistor device and a drive circuit. The second transistor device includes a control node and a load path connected in parallel with the load path of the first transistor device, and the drive circuit includes a capacitor coupled between the second load node of the first transistor device, and a first resistor coupled between the control node of the second transistor device and a further circuit node.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Gerhard Noebauer
  • Patent number: 11139391
    Abstract: An IGBT device comprises a super-junction structure arranged in a drift region and formed by a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed. Device cell structures of the IGBT device are formed in an N-type epitaxial layer at the tops of super-junction cells. Each device cell structure comprises a body region, a gate structure and an emitter region. N-type isolation layers having a doping concentration greater than that of the N-type epitaxial layer are formed between the bottom surfaces of the body regions and the top surfaces of the P-type pillars and are used for isolating the body regions from the P-type pillars. The super-junction structure and the N-type isolation layers can increase the current density of the device, decrease the on-state voltage drop of the device and reduce the turn-off loss of the device.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: October 5, 2021
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jiye Yang, Junjun Xing, Jia Pan, Hao Li, Yi Lu, Longjie Zhao, Xukun Zhang, Xuan Huang, Chong Chen
  • Patent number: 11133316
    Abstract: The disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first and a second polysilicon layers on the substrate, a third polysilicon layer between the first and the second polysilicon layers, a first isolation layer adjacent with the first to the third polysilicon layers, a gate dielectric layer and a gate conductive layer in the third polysilicon layer, a second isolation layer on the gate conductive layer and the third polysilicon layer, a third isolation layer on the first the second isolation layers, a bit line via contact through the first and the third isolation layers, and a conductive layer on the bit line via contact and the third isolation layer. The third polysilicon layer has a concave portion between the first and the second polysilicon layers.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: September 28, 2021
    Assignee: Hexas Technology Corp.
    Inventors: Chen-Chih Wang, Yeu-Yang Wang
  • Patent number: 11101165
    Abstract: A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 24, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
  • Patent number: 11094792
    Abstract: A manufacturing method of a split gate structure includes steps of forming a mask oxide layer on the substrate, performing photolithography and etching on the mask oxide layer and the substrate, forming a trench, removing the mask oxide layer, forming a bottom oxide layer on a bottom part and a side wall of the trench and a surface of the substrate, forming a silicon nitride layer on the trench, removing a part of the bottom oxide layer, forming a gate oxide layer on part of the side wall and the surface, forming a gate poly layer on the trench, removing the silicon nitride layer, forming an inter-poly oxide layer on the gate poly layer, and forming a shield poly layer on the trench, thereby benefiting the increasing of the thickness of the inter-poly oxide layer, so that the advantages of improving the characteristics of the split gate structure are achieved.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 17, 2021
    Assignee: MOSEL VITELIC INC.
    Inventors: Shih-Chi Lai, Hung-Chih Chung, Hsien-Yi Cheng, Chia-Ming Kuo
  • Patent number: 11081490
    Abstract: Some embodiments include an integrated assembly having active-region-pillars. Each of the active-region-pillars has contact regions. The contact regions include a pair of storage-element-contact-regions, and include a digit-line-contact-region between the storage-element-contact-regions. The active-region-pillars include silicon. Wordlines are along the active-region-pillars and extend along a first direction. Cobalt silicide is directly against the silicon of one or more of the contact regions. Metal-containing material is directly against the cobalt silicide. Digit-lines are electrically coupled with the digit-line-contact-regions and extend along a second direction which crosses the first direction. Storage-elements are electrically coupled with the storage-element-contact-regions. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Arzum F. Simsek-Ege
  • Patent number: 11056579
    Abstract: Semiconductor devices and fabrication methods are provided. A semiconductor device includes a substrate, a source and drain material layer formed on the substrate. The source and drain material layer contains a first trench there-through. The semiconductor device further includes a mask layer formed on the source and drain material layer containing a second trench there-through. The second trench has a cross-section area larger than the first trench and covers the first trench. The semiconductor device further includes a channel material layer conformally formed on a bottom and sidewalls of each of the first trench and the second trench and a gate structure conformally formed on the channel material layer, on the bottom and the sidewalls of each of the first trench and the second trench. The gate structure has a recess and the recess has a symmetrical step structure.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 6, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Hai Yang Zhang, Zhuo Fan Chen
  • Patent number: 11043500
    Abstract: Some embodiments include an integrated assembly having a first deck, and having a second deck over the first deck. A first true digit line has a first region along the first deck, and has a second region along the second deck. A first complementary digit line has a first region along the first deck, and has a second region along the second deck. The first true digit line is comparatively compared to the first complementary digit line through SENSE AMPLIFIER circuitry. A second digit line has a first region along the first deck and laterally adjacent the first region of the first complementary digit line, and has a second region along the second deck and laterally adjacent the second region of the first true digit line.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jiyun Li
  • Patent number: 11018250
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Andrew Christopher Graeme Wood
  • Patent number: 11004980
    Abstract: Disclosed are a thin film transistor and a manufacturing method therefor, an array substrate, a display panel and a display device. The thin film transistor includes a base substrate; a first electrode on the base substrate; a second electrode on the first electrode; an active layer provided on the base substrate and connecting the first electrode with the second electrode; and a gate electrode on the base substrate. The base substrate includes an upper surface facing towards the first electrode, the active layer includes a first side surface extending in a direction intersecting the upper surface of the base substrate, the first side surface connects the first electrode with the second electrode, and the gate electrode surrounds the first side surface.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: May 11, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Hehe Hu
  • Patent number: 11004935
    Abstract: The present invention discloses a rugged power semiconductor field effect transistor structure, and through a special design, it solves the problem that the activation under a transient condition may result in failures on the device, so that there is no parasitic BJT, and thus the device is more rugged.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 11, 2021
    Inventor: Wai Yee Liu
  • Patent number: 10964686
    Abstract: In a method of manufacturing a semiconductor device, selectively forming a first semiconductor region and a fourth semiconductor region to be away from each other in a surface layer of a first principal surface of a semiconductor substrate at a same impurity implantation and impurity diffusion process, selectively forming a second semiconductor region in the first semiconductor region and selectively forming a fifth semiconductor region in the fourth semiconductor region at a same impurity implantation and impurity diffusion process, and selectively forming a third semiconductor region that penetrates the first semiconductor region in a depth direction and selectively forming a sixth semiconductor region that penetrates the fourth semiconductor region in the depth direction at a same impurity implantation and impurity diffusion process.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: March 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiaki Toyoda, Hideaki Katakura
  • Patent number: 10950608
    Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 16, 2021
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Jung-Min Moon, Tae-Kyun Kim, Seok-Hee Lee
  • Patent number: 10950545
    Abstract: A semiconductor structure includes a three-dimensional stacked transistor structure including first and second field-effect transistors of a first type at a first vertical level and third and fourth field-effect transistors of a second type at a second vertical level disposed over the first vertical level. The semiconductor structure also includes a first gate structure shared between the first and second field-effect transistors at the first vertical level, a second gate structure shared between the third and fourth field-effect transistors at the second vertical level, and a gate contact shared by the first and second gate structures. The wherein the first and second gate structures are vertically aligned with another in a layout of the three-dimensional stacked transistor structure between source drain/regions of the first, second, third and fourth field-effect transistors.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dongbing Shao, Chen Zhang, Zheng Xu, Tenko Yamashita
  • Patent number: 10950722
    Abstract: Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: March 16, 2021
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John H. Zhang, Carl Radens, Lawrence A. Clevenger, Yiheng Xu
  • Patent number: 10937896
    Abstract: A semiconductor device includes a substrate and a fin structure. The fin structure includes a first semiconductor layer on the substrate, and a stack of one or more semiconductor layer structures. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer, the first and second semiconductor layers having a same semiconductor compound.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 2, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Haiyang Zhang, Yan Wang
  • Patent number: 10908035
    Abstract: According to one embodiment, a pressure sensor is disclosed. The pressure sensor includes a substrate, and a first capacitor element. The first capacitor element includes a lower electrode provided on the substrate, an upper electrode disposed above the lower electrode, and a film provided over the lower electrode and upper electrode. The lower electrode and the upper electrode are between the substrate and the film. An absolute value of an amount of change in an electrostatic capacitance between the lower electrode and the upper electrode with respect to unit change in an ambient temperature of the first capacitor element is substantially zero.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: February 2, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Masunishi, Naofumi Nakamura, Hiroaki Yamazaki, Tomohiro Saito, Fumitaka Ishibashi, Yoshihiko Kurui, Tomohiko Nagata
  • Patent number: 10892262
    Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 12, 2021
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Jung-Min Moon, Tae-Kyun Kim, Seok-Hee Lee
  • Patent number: 10872972
    Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
  • Patent number: 10861974
    Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: December 8, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Patent number: 10811535
    Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: October 20, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10804397
    Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 13, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10790357
    Abstract: Vertical field effect transistors (VFETs) having a gradient threshold voltage and an engineered channel are provided. The engineered channel includes a vertical dog-bone shaped channel structure that is composed of silicon having a germanium content that is 1 atomic percent or less and having a lower portion having a first channel width, a middle portion having a second channel width that is less than the first channel width, and an upper portion having the first channel width. Due to the quantum confinement effect, the middle portion of the vertical dog-bone shaped channel structure has a higher threshold voltage than the lower portion and the upper portion of the vertical dog-bone shaped channel structure. Hence, the at least one vertical dog-bone shaped channel structure has an asymmetric threshold voltage profile. Also, the VFET containing the vertical dog-bone shaped channel structure has improved electrical characteristics and device performance.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Takashi Ando, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee
  • Patent number: 10777469
    Abstract: Semiconductor devices and methods of forming the same include forming a doped dielectric layer on a semiconductor fin. The doped dielectric layer is annealed to drive dopants from the doped dielectric layer into the semiconductor fin. A gate stack is formed on the semiconductor fin.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Junli Wang, Brent A. Anderson, Xin Miao
  • Patent number: 10777674
    Abstract: To suppress breakage of a diode. A semiconductor device comprises a stacked body and a first electrode. The stacked body includes a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, and a fourth nitride semiconductor layer that are stacked in sequence. The first electrode is in contact with a surface of the first nitride semiconductor layer that is opposite to a surface in contact with the second nitride semiconductor layer. The semiconductor device includes a transistor forming region and a diode forming region adjacent to the transistor forming region. The transistor forming region includes a first groove, a second electrode, and a third electrode. The first groove has a bottom portion located in the second nitride semiconductor layer. The second electrode is formed on a surface of the first groove.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 15, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takaki Niwa, Toru Oka
  • Patent number: 10720421
    Abstract: In a circuit portion, a p+-type diffusion region penetrates, in the depth direction, an n?-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p++-type contact region, an n+-type diffusion region, and a p+-type diffusion region are selectively provided in a p+-type diffusion region on the front side of the base substrate. The p+-type diffusion region penetrates the p?-type diffusion region in the depth direction, on the outer periphery of the p?-type diffusion region. An n+-type source region, the p+-type diffusion region, the p++-type contact region, and the n+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiaki Toyoda, Hideaki Katakura
  • Patent number: 10714476
    Abstract: A semiconductor device includes: channel patterns disposed on a substrate; a pair of source/drain patterns disposed at first and second sides of each of the channel patterns; and a gate electrode disposed around the channel patterns, wherein the gate electrode includes a first recessed top surface between adjacent channel patterns, wherein the channel patterns are spaced apart from the substrate, and wherein the gate electrode is disposed between the substrate and the channel patterns.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmin Kim, Dongwon Kim
  • Patent number: 10714399
    Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a substrate, and forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins providing channels for the one or more vertical transport field-effect transistors. The method also includes forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack including a gate dielectric formed over the plurality of fins, a work function metal layer formed over the gate dielectric, and a gate conductor formed over the work function metal layer. The gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, ChoongHyun Lee, Hemanth Jagannathan
  • Patent number: 10672905
    Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Brent A. Anderson, ChoongHyun Lee, Hemanth Jagannathan
  • Patent number: 10672670
    Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Brent A. Anderson, ChoongHyun Lee
  • Patent number: 10615277
    Abstract: Vertical field effect transistor complementary metal oxide semiconductor (VFET CMOS) structures and methods of fabrication include a single mask level for forming the dual source/drains in both the NFET region and the PFET region. The VFET CMOS structures and methods of fabrication further include equal epi-to-channel distances in both the NFET region and PFET regions.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10593798
    Abstract: A vertical transistor and a method of creating the same are provided. The vertical transistor has a substrate and a gate comprising a two-dimensional (2D) material on top of the substrate. There is a spacer on top of the gate. There is a gate dielectric comprising (i) a first portion on top of the spacer, (ii) a second portion extending down to a first side surface of the spacer and a side surface of the gate, and (iii) a third portion on top of the substrate. There is a channel comprising three portions. There is a first electrode on top of the first portion of the channel and a second electrode on top of the third portion of the channel.
    Type: Grant
    Filed: August 5, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jianshi Tang, Qing Cao
  • Patent number: 10573745
    Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10553493
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, including forming a doped layer on a substrate, forming one or more vertical fins on the doped layer, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from at least one of the one or more vertical fins by the thickness of the protective layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10535759
    Abstract: Semiconductor devices and fabrication methods are provided. A fabrication method includes: forming a source and drain material layer over a substrate; forming a mask layer over the source and drain material layer and including a first trench exposing a portion of the source and drain material layer; forming a protective layer on sidewalls of the first trench; forming a second trench in the source and drain material layer using the mask layer and the protective layer as an etch mask; removing the protective layer after the second trench is formed; forming a channel material layer and a gate structure on the channel material layer after the protective layer is removed; and removing the mask layer after the channel material layer and the gate structure are formed. The channel material layer is on the sidewalls and the bottom of the first trench and the second trench.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: January 14, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Hai Yang Zhang, Zhuo Fan Chen
  • Patent number: 10522666
    Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 31, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
  • Patent number: 10522686
    Abstract: A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 31, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10475673
    Abstract: Various embodiments provide a reaction chamber including a support, a receptacle, and a sponge. The support includes a plurality of bars that are spaced from each other by a plurality of openings. Each of the bars has side surfaces that are slanted or tilted downward such that melted material may readily flow through the openings. The support is covered with a coating of silicon carbide to prevent materials from adhering to the support. The receptacle underlies the support and is configured to collect any melted material that is drained through the openings of the support. The sponge is positioned in the receptacle and under the support. The sponge is configured to absorb any melted material that is collected by the receptacle.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: November 12, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ruggero Anzalone, Nicolo Frazzetto, Aldo Raciti, Marco Antonio Salanitri, Giuseppe Abbondanza, Giuseppe D'Arrigo
  • Patent number: 10475907
    Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
  • Patent number: 10468525
    Abstract: Vertical field effect transistor complementary metal oxide semiconductor (VFET CMOS) structures and methods of fabrication include a single mask level for forming the dual source/drains in both the NFET region and the PFET region. The VFET CMOS structures and methods of fabrication further include equal epi-to-channel distances in both the NFET region and PFET regions.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10453941
    Abstract: A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 22, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura, Nozomu Harada
  • Patent number: 10431682
    Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 1, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES, INC.
    Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh
  • Patent number: 10424663
    Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan