Vertical Transistor Patents (Class 257/302)
  • Patent number: 11917815
    Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyosub Kim, Keunnam Kim, Dongoh Kim, Bongsoo Kim, Euna Kim, Chansic Yoon, Kiseok Lee, Hyeonok Jung, Sunghee Han, Yoosang Hwang
  • Patent number: 11848048
    Abstract: Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ahmed Nayaz Noemaun, Chandra S. Danana, Durga P. Panda, Luca Laurin, Michael J. Irwin, Rekha Chithra Thomas, Sara Vigano, Stephen W. Russell, Zia A. Shafi
  • Patent number: 11848287
    Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: December 19, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-su Lee, Hong Sik Chae, Youn Soo Kim, Tae Kyun Kim, Youn Joung Cho
  • Patent number: 11843054
    Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: December 12, 2023
    Assignee: Intel Corporation
    Inventors: Van H. Le, Seung Hoon Sung, Benjamin Chu-Kung, Miriam Reshotko, Matthew Metz, Yih Wang, Gilbert Dewey, Jack Kavalieros, Tahir Ghani, Nazila Haratipour, Abhishek Sharma, Shriram Shivaraman
  • Patent number: 11843055
    Abstract: A transistor comprising threshold voltage control gates. The transistor also comprises active control gates adjacent opposing first sides of a channel region, the threshold voltage control gates adjacent opposing second sides of the channel region, and a dielectric region between the threshold voltage control gates and the channel region and between the active control gates and the channel region. A semiconductor device comprising memory cells comprising the transistor is also disclosed, as are systems comprising the memory cells, methods of forming the semiconductor device, and methods of operating a semiconductor device.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: December 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Kirk D. Prall, Haitao Liu, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11830945
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second electrode, a gate electrode, second semiconductor regions of a second conductivity type, third semiconductor regions of the first conductivity type, and a third electrode. The second electrode is provided in a plurality in second and third directions. Each second electrode opposes a portion of the first semiconductor region in the second and third directions with an insulating layer interposed. The gate electrode is provided around each second electrode. The first semiconductor region includes first regions provided respectively around the second electrodes and the second region provided around the first regions in the second and third directions. Impurity concentration of the first conductivity type in each of the first regions is higher than impurity concentration of the first conductivity type in the second region.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: November 28, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kentaro Ichinoseki, Tatsuya Nishiwaki, Shingo Sato
  • Patent number: 11817451
    Abstract: Some embodiments of the disclosure provide a semiconductor device. The semiconductor device includes: a doped substrate; a barrier layer, disposed on the doped substrate; a channel layer, disposed between the doped substrate and the barrier layer; and a doped semiconductor structure, disposed in the doped substrate, where a band gap of the barrier layer is greater than a band gap of the channel layer, and the doped substrate and the doped semiconductor structure have different polarities.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: November 14, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Qiyue Zhao, Chuan He
  • Patent number: 11749744
    Abstract: A semiconductor device is provided. The semiconductor device includes a bottom source/drain; a top source/drain; a fin provided between the bottom source/drain and the top source/drain, the fin including a first fin structure and a second fin structure that are symmetric to each other in a plan view. Each of the first and second fin structures includes a main fin extending laterally in a first direction, and first and second extension fins extending laterally from the main fin in a second direction perpendicular to the first direction. The main fin extends laterally in the first direction beyond where the first and second extension fins connect to the main fin.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: September 5, 2023
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Lan Yu, Dechao Guo, Junli Wang, Ruqiang Bao, Ruilong Xie
  • Patent number: 11735416
    Abstract: A method includes forming a first amorphous material, forming a second amorphous material over and in contact with the first material, removing a portion of the second material and the first material to form pillars, and exposing the materials to a temperature between a crystallization temperature of the first material and a crystallization temperature of the second material. The first material and the second material each comprise at least one element selected from the group consisting of silicon and germanium. The second material exhibits a crystallization temperature different than a crystallization temperature of the first material. Semiconductor structures, memory devices, and systems are also disclosed.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: August 22, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ashonita A. Chavan, Durai Vishak Nirmal Ramaswamy, Michael Mutch, Sameer Chhajed
  • Patent number: 11711916
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: July 25, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Patent number: 11682668
    Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: June 20, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Suketu Arun Parikh, Sanjay Natarajan
  • Patent number: 11665888
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: May 30, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
  • Patent number: 11637110
    Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: April 25, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jihye Kim, Jaehoon Lee, Jiyoung Kim, Bongtae Park, Jaejoo Shim
  • Patent number: 11616066
    Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: March 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyosub Kim, Keunnam Kim, Dongoh Kim, Bongsoo Kim, Euna Kim, Chansic Yoon, Kiseok Lee, Hyeonok Jung, Sunghee Han, Yoosang Hwang
  • Patent number: 11615955
    Abstract: A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: March 28, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Bo-Yu Yang, Minghwei Hong, Jueinai Kwo, Yen-Hsun Lin, Keng-Yung Lin, Hsien-Wen Wan, Chao Kai Cheng, Kuan Chieh Lu
  • Patent number: 11600726
    Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; bit lines, located on the base, and a material of the bit line including a metal semiconductor compound; semiconductor channels, each including a first doped region, a channel region and a second doped region arranged in sequence, and the first doped region being in contact with the bit line; a first dielectric layer, covering sidewall surfaces of the first doped regions, and a first interval being provided between parts of the first dielectric layer covering sidewalls of adjacent first doped regions on a same bit line; an insulating layer, covering sidewall surfaces of the channel regions; word lines, covering a sidewall surface of the insulating layer away from the channel regions, and a second interval being provided between adjacent word lines.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: March 7, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qinghua Han
  • Patent number: 11594533
    Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron Lilak, Patrick Morrow, Anh Phan, Ehren Mannebach, Jack T. Kavalieros
  • Patent number: 11581317
    Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Srinivas Pulugurtha, Richard J. Hill, Yunfei Gao, Nicholas R. Tapias, Litao Yang, Haitao Liu
  • Patent number: 11569218
    Abstract: Provided is a layout structure capable of reducing the parasitic capacitance between storage nodes of an SRAM cell using vertical nanowire (VNW) FETs. In the SRAM cell, a first storage node is connected to top electrodes of some transistors, and a second storage node is connected to bottom electrodes of other transistors. Accordingly, the first and second storage nodes have fewer regions adjacent to each other in a single layer.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: January 31, 2023
    Assignee: SOCIONEXT INC.
    Inventor: Yoshinobu Yamagami
  • Patent number: 11502204
    Abstract: Provided is a semiconductor device of the embodiment including: an oxide semiconductor layer; a gate electrode; a first electrode electrically connected to one portion of the oxide semiconductor layer, the first electrode including a first region, second region, a third region, and a fourth region, the first region disposed between the first portion and the second region, the first region disposed between the third region and the fourth region, the first region containing at least one element of In, Zn, Sn or Cd, and oxygen, the second region containing at least one metal element of Ti, Ta, W, or Ru, the third region and the fourth region containing the at least one metal element and oxygen, the third region and the fourth region having an atomic concentration of oxygen higher than that of the second region; and a second electrode electrically connected to another portion of the oxide semiconductor layer.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: November 15, 2022
    Assignee: Kioxia Corporation
    Inventors: Akifumi Gawase, Atsuko Sakata
  • Patent number: 11495495
    Abstract: A method of manufacturing a semiconductor device includes forming a base layer on a substrate. A structure layer is Conned on the base layer. The structure layer includes at least one material layer. A structure pattern is formed on the base layer. The structure pattern includes a first trench extending in a first direction and a second trench having a cross portion extending in a second direction that is perpendicular to the first direction. The second trench is connected to the first trench. The structure pattern further includes a base pattern having a recess portion recessed downward from a surface of the base layer at the cross portion of the second trench.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: November 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Geun-Won Lim, Myung-Keun Lee, Seok-Cheon Baek, Kyeong-Jin Park
  • Patent number: 11456294
    Abstract: Some embodiments of the disclosure provide a semiconductor device. The semiconductor device includes: a doped substrate; a barrier layer, disposed on the doped substrate; a channel layer, disposed between the doped substrate and the barrier layer; and a doped semiconductor structure, disposed in the doped substrate, where a band gap of the barrier layer is greater than a band gap of the channel layer, the doped substrate and the doped semiconductor structure have different polarities, and the doped substrate includes a doped silicon substrate.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: September 27, 2022
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Qiyue Zhao, Chuan He, Zuer Chen
  • Patent number: 11437384
    Abstract: The present disclosure provides a semiconductor memory device and a method for manufacturing the semiconductor memory device. The method includes steps of: providing a substrate including a storage area and a peripheral area, wherein the storage area has a contact plug, a bit line structure adjacent to the contact plug, an air gap between the bit line structure and the contact plug, a barrier layer conformally overlaying the bit line structure, and a landing pad above the barrier layer; forming a trench between the storage area and the peripheral area; filling the trench with a nitride material; forming a first oxide layer above the nitride material in the trench and on the landing pad; forming a nitride layer above the first oxide layer; and forming a second oxide layer above the nitride layer.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: September 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Jr-Chiuan Wang, Rou-Wei Wang, Wei-Yu Chen
  • Patent number: 11362209
    Abstract: In a general aspect, an apparatus, can include a trench disposed within a semiconductor region of a substrate. The trench can be lined with a gate dielectric and including an electrode disposed within the trench. The apparatus can include a polysilicon layer disposed above the trench. The trench can have an end portion disposed below an opening in the polysilicon layer. The end portion of the trench can be disposed between a first side of the opening and a second side of the opening.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 14, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Reiki Fujimori
  • Patent number: 11355179
    Abstract: The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: June 7, 2022
    Inventors: Tomoaki Atsumi, Junpei Sugao
  • Patent number: 11355503
    Abstract: A device includes at least three memory cells. For each cell, there is a first doped semiconductor area and a switch coupling the cell to the first area. First doped semiconductor zones connect the first areas together. A memory can include a number of the devices. For example, the cells can be arranged in a matrix, each device defining a row of the matrix.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: June 7, 2022
    Assignee: STMICROELECTRONICS SA
    Inventors: Stephane Denorme, Philippe Candelier
  • Patent number: 11302697
    Abstract: A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: April 12, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Andrew J. Walker, Dafna Beery, Peter Cuevas, Amitay Levi
  • Patent number: 11239369
    Abstract: A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: February 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 11227865
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device can be a recessed access device (RAD) transistor, which includes a substrate, a word line disposed in the substrate and surrounded by a dielectric liner, an isolation layer disposed in the substrate to cap the word line, and an insulative plug penetrating through the isolation layer and extending into the word line.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: January 18, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Wei Huang
  • Patent number: 11227932
    Abstract: Aspects of the disclosure provide a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11189721
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: November 30, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Sameer Pendharkar, Guru Mathur
  • Patent number: 11183629
    Abstract: A method for fabricating an electronic device comprising a semiconductor memory is described. The method comprises forming material layers over a substrate; forming a hard mask pattern over the material layers, the hard mask pattern including an amorphous carbon layer; forming a capping protective layer including a portion on sidewalls of the hard mask pattern; and etching the material layers using the hard mask pattern as an etch barrier.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Ga-Young Ha
  • Patent number: 11164876
    Abstract: Systems, apparatuses, and methods related to atom implantation for passivation of pillar material are described. An example apparatus includes a pillar of a semiconductor device. The pillar may include a first portion (e.g., a passivation material) formed from silicon nitride and an underlying second portion formed from a conductive material. A region of the first portion opposite from an interface between the first portion and the underlying second portion may be implanted with atoms of an element different from silicon (Si) and nitrogen (N) to enhance passivation of the implanted region.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Russell A. Benson
  • Patent number: 11158627
    Abstract: Disclosed is an electronic circuit. The electronic circuit includes a first transistor device and a clamping circuit. The first transistor device includes a control node and a load path between a first load node and a second load node, and the clamping circuit includes a second transistor device and a drive circuit. The second transistor device includes a control node and a load path connected in parallel with the load path of the first transistor device, and the drive circuit includes a capacitor coupled between the second load node of the first transistor device, and a first resistor coupled between the control node of the second transistor device and a further circuit node.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Gerhard Noebauer
  • Patent number: 11139391
    Abstract: An IGBT device comprises a super-junction structure arranged in a drift region and formed by a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed. Device cell structures of the IGBT device are formed in an N-type epitaxial layer at the tops of super-junction cells. Each device cell structure comprises a body region, a gate structure and an emitter region. N-type isolation layers having a doping concentration greater than that of the N-type epitaxial layer are formed between the bottom surfaces of the body regions and the top surfaces of the P-type pillars and are used for isolating the body regions from the P-type pillars. The super-junction structure and the N-type isolation layers can increase the current density of the device, decrease the on-state voltage drop of the device and reduce the turn-off loss of the device.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: October 5, 2021
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jiye Yang, Junjun Xing, Jia Pan, Hao Li, Yi Lu, Longjie Zhao, Xukun Zhang, Xuan Huang, Chong Chen
  • Patent number: 11133316
    Abstract: The disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first and a second polysilicon layers on the substrate, a third polysilicon layer between the first and the second polysilicon layers, a first isolation layer adjacent with the first to the third polysilicon layers, a gate dielectric layer and a gate conductive layer in the third polysilicon layer, a second isolation layer on the gate conductive layer and the third polysilicon layer, a third isolation layer on the first the second isolation layers, a bit line via contact through the first and the third isolation layers, and a conductive layer on the bit line via contact and the third isolation layer. The third polysilicon layer has a concave portion between the first and the second polysilicon layers.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: September 28, 2021
    Assignee: Hexas Technology Corp.
    Inventors: Chen-Chih Wang, Yeu-Yang Wang
  • Patent number: 11101165
    Abstract: A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 24, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
  • Patent number: 11094792
    Abstract: A manufacturing method of a split gate structure includes steps of forming a mask oxide layer on the substrate, performing photolithography and etching on the mask oxide layer and the substrate, forming a trench, removing the mask oxide layer, forming a bottom oxide layer on a bottom part and a side wall of the trench and a surface of the substrate, forming a silicon nitride layer on the trench, removing a part of the bottom oxide layer, forming a gate oxide layer on part of the side wall and the surface, forming a gate poly layer on the trench, removing the silicon nitride layer, forming an inter-poly oxide layer on the gate poly layer, and forming a shield poly layer on the trench, thereby benefiting the increasing of the thickness of the inter-poly oxide layer, so that the advantages of improving the characteristics of the split gate structure are achieved.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 17, 2021
    Assignee: MOSEL VITELIC INC.
    Inventors: Shih-Chi Lai, Hung-Chih Chung, Hsien-Yi Cheng, Chia-Ming Kuo
  • Patent number: 11081490
    Abstract: Some embodiments include an integrated assembly having active-region-pillars. Each of the active-region-pillars has contact regions. The contact regions include a pair of storage-element-contact-regions, and include a digit-line-contact-region between the storage-element-contact-regions. The active-region-pillars include silicon. Wordlines are along the active-region-pillars and extend along a first direction. Cobalt silicide is directly against the silicon of one or more of the contact regions. Metal-containing material is directly against the cobalt silicide. Digit-lines are electrically coupled with the digit-line-contact-regions and extend along a second direction which crosses the first direction. Storage-elements are electrically coupled with the storage-element-contact-regions. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Arzum F. Simsek-Ege
  • Patent number: 11056579
    Abstract: Semiconductor devices and fabrication methods are provided. A semiconductor device includes a substrate, a source and drain material layer formed on the substrate. The source and drain material layer contains a first trench there-through. The semiconductor device further includes a mask layer formed on the source and drain material layer containing a second trench there-through. The second trench has a cross-section area larger than the first trench and covers the first trench. The semiconductor device further includes a channel material layer conformally formed on a bottom and sidewalls of each of the first trench and the second trench and a gate structure conformally formed on the channel material layer, on the bottom and the sidewalls of each of the first trench and the second trench. The gate structure has a recess and the recess has a symmetrical step structure.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 6, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Hai Yang Zhang, Zhuo Fan Chen
  • Patent number: 11043500
    Abstract: Some embodiments include an integrated assembly having a first deck, and having a second deck over the first deck. A first true digit line has a first region along the first deck, and has a second region along the second deck. A first complementary digit line has a first region along the first deck, and has a second region along the second deck. The first true digit line is comparatively compared to the first complementary digit line through SENSE AMPLIFIER circuitry. A second digit line has a first region along the first deck and laterally adjacent the first region of the first complementary digit line, and has a second region along the second deck and laterally adjacent the second region of the first true digit line.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jiyun Li
  • Patent number: 11018250
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Andrew Christopher Graeme Wood
  • Patent number: 11004935
    Abstract: The present invention discloses a rugged power semiconductor field effect transistor structure, and through a special design, it solves the problem that the activation under a transient condition may result in failures on the device, so that there is no parasitic BJT, and thus the device is more rugged.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 11, 2021
    Inventor: Wai Yee Liu
  • Patent number: 11004980
    Abstract: Disclosed are a thin film transistor and a manufacturing method therefor, an array substrate, a display panel and a display device. The thin film transistor includes a base substrate; a first electrode on the base substrate; a second electrode on the first electrode; an active layer provided on the base substrate and connecting the first electrode with the second electrode; and a gate electrode on the base substrate. The base substrate includes an upper surface facing towards the first electrode, the active layer includes a first side surface extending in a direction intersecting the upper surface of the base substrate, the first side surface connects the first electrode with the second electrode, and the gate electrode surrounds the first side surface.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: May 11, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Hehe Hu
  • Patent number: 10964686
    Abstract: In a method of manufacturing a semiconductor device, selectively forming a first semiconductor region and a fourth semiconductor region to be away from each other in a surface layer of a first principal surface of a semiconductor substrate at a same impurity implantation and impurity diffusion process, selectively forming a second semiconductor region in the first semiconductor region and selectively forming a fifth semiconductor region in the fourth semiconductor region at a same impurity implantation and impurity diffusion process, and selectively forming a third semiconductor region that penetrates the first semiconductor region in a depth direction and selectively forming a sixth semiconductor region that penetrates the fourth semiconductor region in the depth direction at a same impurity implantation and impurity diffusion process.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: March 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiaki Toyoda, Hideaki Katakura
  • Patent number: 10950722
    Abstract: Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: March 16, 2021
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John H. Zhang, Carl Radens, Lawrence A. Clevenger, Yiheng Xu
  • Patent number: 10950545
    Abstract: A semiconductor structure includes a three-dimensional stacked transistor structure including first and second field-effect transistors of a first type at a first vertical level and third and fourth field-effect transistors of a second type at a second vertical level disposed over the first vertical level. The semiconductor structure also includes a first gate structure shared between the first and second field-effect transistors at the first vertical level, a second gate structure shared between the third and fourth field-effect transistors at the second vertical level, and a gate contact shared by the first and second gate structures. The wherein the first and second gate structures are vertically aligned with another in a layout of the three-dimensional stacked transistor structure between source drain/regions of the first, second, third and fourth field-effect transistors.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dongbing Shao, Chen Zhang, Zheng Xu, Tenko Yamashita
  • Patent number: 10950608
    Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 16, 2021
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Jung-Min Moon, Tae-Kyun Kim, Seok-Hee Lee
  • Patent number: 10937896
    Abstract: A semiconductor device includes a substrate and a fin structure. The fin structure includes a first semiconductor layer on the substrate, and a stack of one or more semiconductor layer structures. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer, the first and second semiconductor layers having a same semiconductor compound.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 2, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Haiyang Zhang, Yan Wang
  • Patent number: 10908035
    Abstract: According to one embodiment, a pressure sensor is disclosed. The pressure sensor includes a substrate, and a first capacitor element. The first capacitor element includes a lower electrode provided on the substrate, an upper electrode disposed above the lower electrode, and a film provided over the lower electrode and upper electrode. The lower electrode and the upper electrode are between the substrate and the film. An absolute value of an amount of change in an electrostatic capacitance between the lower electrode and the upper electrode with respect to unit change in an ambient temperature of the first capacitor element is substantially zero.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: February 2, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Masunishi, Naofumi Nakamura, Hiroaki Yamazaki, Tomohiro Saito, Fumitaka Ishibashi, Yoshihiko Kurui, Tomohiko Nagata