With High Dielectric Constant Insulator (e.g., Ta 2 O 5 ) Patents (Class 257/310)
  • Patent number: 10636795
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: April 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Patent number: 10629756
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Chewn-Pu Jou, Min-Chie Jeng
  • Patent number: 10600788
    Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
  • Patent number: 10535727
    Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
  • Patent number: 10522692
    Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10516031
    Abstract: A method of fabricating a semiconductor device includes depositing a contact etch stop layer (CESL) over a dummy gate electrode, a source/drain (S/D) region and an isolation feature. The method further includes performing a first CMP to expose the dummy gate electrode. The method further includes removing an upper portion of the CESL. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the dummy gate electrode.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
  • Patent number: 10505039
    Abstract: A method of forming a semiconductor structure is disclosed, comprising providing a substrate, forming at least a gate trench extending along a first direction in the substrate, forming a gate dielectric layer conformally covering the gate trench, forming a sacrificial layer on the gate dielectric layer and completely filling the gate trench, forming a plurality of openings through the sacrificial layer in the gate trench thereby exposing a portion of the gate dielectric layer, forming a dielectric material in the openings, performing an etching back process to remove a portion of the dielectric material until the dielectric material only remains at a lower portion of each of the openings thereby obtaining a plurality of intervening structures, removing the sacrificial layer, and forming a gate metal filling the gate trench, wherein the intervening structures are disposed between the gate metal and the gate dielectric layer.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: December 10, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee
  • Patent number: 10504826
    Abstract: An electronics package is disclosed that comprises a multilayer interconnect structure including a plurality of insulating substrate layers each having a plurality of microvias formed therein, a plurality of conductive wiring layers positioned on the plurality of insulating substrate layers, and a plurality of conductive microvias in the plurality of microvias to, wherein a bottom wiring layer includes a plurality of first terminal pads that are positioned on a bottom surface of the multilayer interconnect structure. The electronics package also comprises an electrical component coupled to the bottom surface of the multilayer interconnect structure, the electrical component including first I/O pads aligned with the first terminal pads and second I/O pads aligned to regions of the multilayer interconnect structure without first terminal pads.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 10, 2019
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Kaustubh Ravindra Nagarkar
  • Patent number: 10431679
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and at least a gate trench extending along a first direction formed in the substrate. A gate dielectric layer is formed conformally covering the gate trench. A gate metal is formed on the gate dielectric layer and filling the gate trench. A plurality of intervening structures are arranged along the first direction in a lower portion of the gate trench and disposed between the gate metal and the gate dielectric layer.
    Type: Grant
    Filed: April 1, 2018
    Date of Patent: October 1, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee
  • Patent number: 10321575
    Abstract: An integrated circuit (IC) module that includes an integrated circuit (IC) package, a plurality of first solder interconnects coupled to the IC package, an interposer coupled to the IC package through the plurality of first solder interconnects a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. The interposer includes an encapsulation layer, a first passive component at least partially embedded in the encapsulation layer, and a plurality of interconnects coupled to the first passive component. The encapsulation layer includes a mold and/or an epoxy fill. The first passive component is configured to operate as an electronic voltage regulator (EVR) for the IC module. In some implementations, the interposer is a fan out interposer.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: June 11, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Yue Li, Charles David Paynter, Ryan David Lane, Ruey Kae Zang
  • Patent number: 10262856
    Abstract: Methods for integrating transition metal oxide (TMO) layers into a compound semiconductor device structure via selective oxidation of transition metal nitride (TMN) layers within the structure.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 16, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: David J. Meyer, Brian P. Downey, Daniel S. Green
  • Patent number: 10100202
    Abstract: A coated article is provided with a low-emissivity (low-E) coating on a glass substrate. The low-E coating includes an infrared (IR) reflecting layer between at least a pair of dielectric layers. The IR reflecting layer may be of silver or the like. The coating is designed so as to provide a highly transparent coated article that is thermally stable upon optional heat treatment and which can be made to have a low emissivity in a consistent manner. The coating is designed to have improved IR reflecting layer quality, and thus reduced tolerances with respect to manufacturability of desired emissivity values. The coated article may be used in monolithic window applications, IG window applications, or the like.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 16, 2018
    Assignees: Guardian Europe S.a.r.l., Guardian Industries UK Ltd.
    Inventors: Bernd Disteldorf, Anton Dietrich, Robert Baker, Stuart Silvester, Eduardo Sanz
  • Patent number: 10099964
    Abstract: A dielectric composition, a dielectric element, an electronic component and a laminated electronic component are disclosed. In various embodiment, the dielectric composition includes a main component represented by (BiaNabSrcLnd)TiO3, wherein Ln is at least one element selected from the group consisting of: La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho and Yb, and wherein a, b, c and d satisfy the following: 0<a<0.50, 0<b<0.50, 0<c?0.80, 0<d?0.20, and 0.90?a+b+c+d?1.05.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: October 16, 2018
    Assignee: EPCOS AG
    Inventor: Goushi Tauchi
  • Patent number: 10090407
    Abstract: To restrict alloy formation between a hydrogen-absorbing layer of titanium or the like and an electrode of aluminum or the like, provided is a semiconductor device. The semiconductor device may include a semiconductor substrate. The semiconductor device may include a first layer that is formed above the semiconductor substrate. The first layer may contain a hydrogen-absorbing first metal. The semiconductor device may include a second layer that is formed above the first layer. The second layer may contain a second metal differing from the first metal. The semiconductor device may include an Si-containing layer that is formed between the first layer and the second layer and contains silicon. The second layer may further include silicon. The Si-containing layer may have a higher silicon concentration than the second layer. The second metal may be aluminum. The first metal may be titanium.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: October 2, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tsukasa Tashima, Kazuhiro Kitahara
  • Patent number: 10038067
    Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Suyog Gupta, Bahman Hekmatshoartabari
  • Patent number: 10020359
    Abstract: Capacitors and methods of forming the same include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Hemanth Jagannathan, Paul C. Jamison, John Rozen
  • Patent number: 9997606
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a bilayer buried insulator over a substrate, forming an extremely thin silicon-on-insulator (ETSOI) over the bilayer buried insulator, forming a dummy gate, and forming a source/drain next to the dummy gate, the source/drain defining a raised source/drain region. The method further includes depositing a dielectric material over the raised source/drain regions, removing the dummy gate to define a recess, implanting a species within a first layer of the bilayer buried insulator, and depositing a gate dielectric and a conducting material within the recess. The method further includes removing the substrate, etching the implanted portion of the first layer of the bilayer buried insulator to expose a surface of a second layer of the bilayer buried insulator, and forming a back gate over the exposed second layer, the back gate self-aligned to the ETSOI channel.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Patent number: 9997415
    Abstract: A semiconductor device includes a substrate, first and second metals, and a second semiconductor material. The substrate includes a first semiconductor material and has first and second substrate portions. The first metal is reacted with the first substrate portion of the substrate. The second semiconductor material is above the second substrate portion of the substrate and is different from the first semiconductor material. The second metal is reacted with the second semiconductor material.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 9972721
    Abstract: A method of forming a semiconductor device is disclosed including providing a semiconductor-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulating layer positioned on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulating layer, providing at least one metal-oxide semiconductor gate structure positioned above the semiconductor layer comprising a gate electrode and a spacer formed adjacent to the gate electrode, selectively removing an upper portion of the semiconductor layer so as to define recessed portions of the semiconductor layer and epitaxially forming raised source/drain regions on the recessed portions of the semiconductor layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Marcel Richter, Ardechir Pakfar, Armin Muehlhoff
  • Patent number: 9941212
    Abstract: An advanced metal conductor structure and a method for constructing the structure are described. A pattern is provided in a dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is created over the patterned dielectric. A ruthenium layer disposed over the adhesion promoting layer is deposited. A nitridation process is performed on the ruthenium layer to produce a nitridized ruthenium layer. Using a physical vapor deposition process, a cobalt layer is deposited disposed over the nitridized ruthenium layer. A thermal anneal is performed which reflows the cobalt layer to fill the set of features to form a set of metal conductor structures. In another aspect of the invention, an integrated circuit device is formed using the method.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 9871198
    Abstract: A method for manufacturing a resistive memory device is disclosed and comprises following steps. Firstly, a bottom electrode is formed over a substrate. Next, an oxidation process is performed to the bottom electrode to form a metal oxide layer, wherein a hydrogen plasma and an oxygen plasma are provided during the oxidation process. Then, a top electrode is formed on the metal oxide layer.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: January 16, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 9862646
    Abstract: A dielectric composition containing a complex oxide represented by the formula of A?B?C2?O?+?+5? as the main component, wherein A represents Ba, B represents at least one element selected from the group consisting of Ca and Sr, C represents at least one element selected from the group consisting of Ta and Nb, and ?, ? and ? meet the following conditions, i.e., ?+?+?=1.000, 0.000<??0.375, 0.625??<1.000, 0.000???0.375.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 9, 2018
    Assignee: TDK CORPORATION
    Inventors: Shohei Fujii, Raitarou Masaoka, Hiroki Uchiyama, Maiko Shirokawa
  • Patent number: 9761437
    Abstract: Provided are: forming an oxycarbonitride film, an oxycarbide film or an oxide film on a substrate by alternately performing a specific number of times: forming a first layer containing the specific element, nitrogen and carbon, on the substrate, by alternately performing a specific number of times, supplying a first source containing the specific element and a halogen-group to the substrate in a processing chamber, and supplying a second source containing the specific element and an amino-group to the substrate in the processing chamber; and forming a second layer by oxidizing the first layer by supplying an oxygen-containing gas, and an oxygen-containing gas and a hydrogen-containing gas to the substrate in the processing chamber.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: September 12, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yosuke Ota, Yoshiro Hirose
  • Patent number: 9755026
    Abstract: A method of forming a semiconductor device includes forming a sacrificial gate pattern on an active pattern, forming spacers on opposite sidewalls of the sacrificial gate pattern, forming an interlayer insulating layer on the active pattern and the spacers, removing the sacrificial gate pattern to form a gate trench that exposes a region of the active pattern, forming a gate dielectric layer on the region of the active pattern exposed by the gate trench, performing a first heat treatment at a pressure of less than 1 atm to remove impurities in the interlayer insulating layer, performing a second heat treatment on the gate dielectric layer at a temperature greater than a temperature of the first heat treatment, and forming a gate electrode in the gate trench.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Su Yoo, WeonHong Kim, Moonkyun Song, Minjoo Lee, Soojung Choi
  • Patent number: 9728401
    Abstract: Embodiments of methods for treating dielectric layers are provided herein. In some embodiments, a method of treating a dielectric layer disposed on a substrate supported in a process chamber includes: (a) exposing the dielectric layer to an active radical species formed in a plasma for a first period of time; (b) heating the dielectric layer to a peak temperature of about 900 degrees Celsius to about 1200 degrees Celsius; and (c) maintaining the peak temperature for a second period of time of about 1 second to about 20 seconds.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: August 8, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Heng Pan, Matthew Scott Rogers, Christopher S. Olsen
  • Patent number: 9640544
    Abstract: An integrated circuit such as a NAND flash memory includes a dielectric layer overlying transistors (e.g. NAND flash memory cells) that are formed along a surface of a substrate and a hydrogen absorption structure overlying the dielectric layer, the hydrogen absorption structure extending over the transistors, the hydrogen absorption structure being electrically isolated from the transistors.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: May 2, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Arata Okuyama, Ryo Urakawa, Hiroshi Omi
  • Patent number: 9627198
    Abstract: An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H2O) included in the oxide semiconductor layer is diffused into the silicon oxide layer. Further, a mixed region is provided between the oxide semiconductor layer and the silicon oxide layer. The mixed region includes oxygen, silicon, and at least one kind of metal element that is included in the oxide semiconductor.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 18, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Masahiro Takahashi, Hideyuki Kishida, Junichiro Sakata
  • Patent number: 9595668
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to memory devices having a resistance switching element, and to methods of operating such memory devices. In one aspect, a memory cell includes a first electrode and a second electrode formed of one of a metallic material or a semiconducting material. The memory cell additionally includes a resistance switching element formed between the first electrode and the second electrode. The memory cell additionally includes a tunnel rectifier formed between the resistance-switching element and the first electrode. The tunnel rectifier includes a multi-layer tunnel stack comprising at least two dielectric layers each having a dielectric constant (ki), a conduction band offset (?i), and a thickness, wherein one of the dielectric layers has a higher dielectric constant, a lower conduction band offset and a higher thickness compared to any other dielectric layer of the multi-layer tunnel stack.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: March 14, 2017
    Assignee: IMEC vzw
    Inventor: Bogdan Govoreanu
  • Patent number: 9595576
    Abstract: An encapsulated ferroelectric capacitor or ferroelectric memory cell includes encapsulation materials adjacent to a ferroelectric capacitor, a ferroelectric oxide (FEO) layer over the encapsulated ferroelectric capacitor, and an FEO encapsulation layer over the ferroelectric oxide to provide protection from hydrogen induced degradation.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: March 14, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Tom E. Davenport
  • Patent number: 9595533
    Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 14, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
  • Patent number: 9590117
    Abstract: A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: March 7, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Naoki Yasuda
  • Patent number: 9478508
    Abstract: A semiconductor structure having a semiconductor layer having an active device therein. A dielectric structure is disposed over the semiconductor layer, such dielectric structure having open ended trench therein. An electrical interconnect level is disposed in the trench and electrically connected to the active device. A plurality of stacked metal layers is disposed in the trench. The stacked metal layers have disposed on bottom and sidewalls thereof conductive barrier metal layers.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: October 25, 2016
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, John P. Bettencourt, Thomas E. Kazior, Kelly P. Ip
  • Patent number: 9466660
    Abstract: A semiconductor structure may include a first electrode over a substrate, a high-K dielectric material over the first electrode, and a second electrode over the high-K dielectric material, wherein at least one of the first electrode and the second electrode may include a material selected from the group consisting of a molybdenum nitride (MoaNb) material, a molybdenum oxynitride (MoOxNy) material, a molybdenum oxide (MoOx) material, and a molybdenum-based alloy material comprising molybdenum and nitrogen.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: October 11, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Matthew N. Rocklein, Kotha Sai Madhukar Reddy, Vassil Antonov, Vishwanath Bhat
  • Patent number: 9464352
    Abstract: A method for forming an oxide film by plasma-assisted cyclic processing, includes: (i) supplying a precursor to a reaction space wherein a substrate is placed; (ii) applying a first RF power to the reaction space for a first period of time without supplying a precursor; and (iii) applying a second RF power to the reaction space for a second period of time without supplying the precursor, wherein the first RF power is lower than the second RF power, and/or the first period of time is shorter than the second period of time.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: October 11, 2016
    Assignee: ASM IP Holding B.V.
    Inventors: Ryu Nakano, Naoki Inoue, Kunitoshi Namba
  • Patent number: 9437658
    Abstract: A monolithic, three-dimensional memory device includes a substrate and a plurality of electrically conductive word lines over a major surface of the substrate. An electrically conductive bit line extends in a direction substantially perpendicular to the major surface of the substrate and adjacent to each of the plurality of word lines, and a non-volatile memory element material is located between the bit line and each of the plurality of word lines. A plurality of middle electrodes comprising an electrically conductive material are located between the bit line and each of the plurality of word lines, wherein the plurality of middle electrodes are discrete electrodes which are isolated from one another in at least the second direction.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: September 6, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yukihiro Sakotsubo
  • Patent number: 9343331
    Abstract: A method of manufacturing a semiconductor device provided with a stack of a first film substantially free of oxygen and a second film disposed above the first film and comprising a metal oxide containing an uneasily etched material is disclosed. The method includes etching the second film by a first process using a first etch gas containing a boron trichloride containing gas and by a second process following the first process using a second etch gas containing an inert gas. In the second process, the second etch gas is used while a bias power is controlled to be equal to or greater than an etching threshold energy of the second film.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: May 17, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhisa Matsuda, Toshiyuki Sasaki, Mitsuhiro Omura
  • Patent number: 9337786
    Abstract: Tube amplifier assembly including a tube assembly having a support frame and a vacuum tube secured to the support frame. The support frame includes a ground wall that is electrically conductive and configured to be coupled to ground. The tube amplifier assembly also includes a supply cable electrically coupled to the vacuum tube. The tube amplifier assembly also includes a multi-layer decoupling capacitor having a first insulation layer, a power electrode, a second insulation layer, and a ground plate. The first insulation layer is interleaved between the ground wall and the power electrode, and the second insulation layer is interleaved between the power electrode and the ground plate. The supply cable is electrically coupled to the power electrode, and the ground plate is mounted to and electrically coupled to the ground wall of the support frame.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: May 10, 2016
    Assignee: General Electric Company
    Inventor: Bert Holmgren
  • Patent number: 9331009
    Abstract: A chip electronic component may be capable of improving connectivity between internal coils formed on upper and lower surfaces of an insulating substrate and preventing loss of inductance due to the areas of via pads by decreasing sizes of the outermost via electrodes and decreasing sizes of the via pad.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: May 3, 2016
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Woon Chul Choi, Yong Sam Lee, Hwan Soo Lee
  • Patent number: 9299369
    Abstract: An apparatus for magnetic recording having a barrier layer. One embodiment includes a magnetic head having an array of sensors, each of the sensors having a media facing surface. A barrier layer is positioned above at least the media facing surfaces of the sensors. The barrier layer includes at least one at least partially polycrystalline layer.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Robert G. Biskeborn, Calvin S. Lo
  • Patent number: 9269785
    Abstract: The present disclosure provides a semiconductor device comprising a substrate, an undoped HfO2 layer formed over the substrate and a TiN layer formed on the HfO2 layer. Herein, the undoped HfO2 layer is at least partially ferroelectric. In illustrative methods for forming a semiconductor device, an undoped amorphous HfO2 layer is formed over a semiconductor substrate and a TiN layer is formed on the undoped amorphous HfO2 layer. A thermal annealing process is performed for at least partially inducing a ferroelectric phase in the undoped amorphous HfO2 layer.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: February 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Johannes Mueller, Dina H. Triyoso, Robert Binder, Joachim Metzger, Patrick Polakowski
  • Patent number: 9190208
    Abstract: This disclosure provides systems, methods, and apparatus for metal-insulator-metal capacitors on glass substrates. In one aspect, an apparatus may include a glass substrate, with the glass substrate defining at least one via in the glass substrate. A first electrode layer may be disposed over surfaces of the glass substrate, including surfaces of the at least one via. A dielectric layer may be disposed on the first electrode layer. A second electrode layer may be disposed on the dielectric layer, with the dielectric layer electrically isolating the first electrode layer from the second electrode layer.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: November 17, 2015
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Jon Bradley Lasiter, Ravindra V. Shenoy, Donald William Kidwell, Victor Louis Arockiaraj Pushparaj, Kwan-yu Lai, Ana Rangelova Londergan
  • Patent number: 9178012
    Abstract: A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Veeraraghavan S. Basker, Richard Q. Williams
  • Patent number: 9129894
    Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: September 8, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Imran Hashim, Tony Chiang, Vidyut Gopal, Yun Wang
  • Patent number: 9123563
    Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Audrey Hsiao-Chiu Hsu, Fu-Kai Yang, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsin-Ying Lin
  • Patent number: 9082747
    Abstract: Provided are a semiconductor device manufacturing method by which a semiconductor device in which a threshold voltage is suppressed from changing can be manufactured, a substrate processing method and apparatus, a non-transitory computer-readable recording medium, and the semiconductor device. The semiconductor device manufacturing method includes forming an amorphous first oxide film including a first element on a substrate, and modifying the first oxide film to an amorphous second oxide film including the first element and a second element different from the first element by adding the second element to the first oxide film. The first element includes at least one element selected from a group consisting of aluminum, yttrium and lanthanum. A concentration of the second element in the second oxide film is controlled to be lower than that of the first element in the second oxide film.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: July 14, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Arito Ogawa
  • Patent number: 9035273
    Abstract: A resistive switching memory device is provided with first to third electrodes. The first electrode forms a Schottky barrier which can develop a rectifying property and resistance change characteristics at an interface between the first electrode and an oxide semiconductor. The third electrode is made of a material which provides an ohmic contact with the oxide semiconductor. A control voltage is applied between the first and second electrodes, and a driving voltage is applied between the first and third electrodes.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: May 19, 2015
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Sakyo Hirose
  • Patent number: 9023699
    Abstract: The present disclosure provides a resistive random access memory (RRAM) cell. The RRAM cell includes a transistor, a bottom electrode adjacent to a drain region of the transistor and coplanar with the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the drain region.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang
  • Patent number: 9013045
    Abstract: BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: April 21, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Yiming Huai, Jing Zhang, Ebrahim Abedifard
  • Patent number: 9000506
    Abstract: A nonvolatile memory element which inhibits deterioration of an oxygen concentration profile of a variable resistance layer due to a thermal budget and is able to stably operate at low voltages, and a method for manufacturing the nonvolatile memory element are provided. The nonvolatile memory element includes a first electrode layer formed above a substrate, a variable resistance layer disposed on the first electrode layer, and a second electrode layer disposed on the variable resistance layer, and the variable resistance layer has a two-layer structure in which an oxygen- and/or nitrogen-deficient tantalum oxynitride layer and a tantalum oxide layer are stacked.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 7, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takeki Ninomiya, Takumi Mikawa, Yukio Hayakawa
  • Patent number: 8969938
    Abstract: An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination of which is accompanied with appropriate etch.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam Shahidi