Having High Dielectric Constant Insulator (e.g., Ta2o5, Etc.) Patents (Class 438/240)
  • Patent number: 11335817
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han Lin, Chao-Ching Chang, Yi-Ming Lin, Yen-Ting Chou, Yen-Chang Chen, Sheng-Chan Li, Cheng-Hsien Chou
  • Patent number: 11329125
    Abstract: A capacitor comprises at least one primary trench in a substrate, extending in a first direction, and at least one secondary trench in the substrate, extending in a second direction different from the first direction. The capacitor further comprises a first dielectric material separating the substrate from the first capacitor plate of a plurality of capacitor plates, and a second dielectric material separating the first capacitor plate from a second capacitor plate of the plurality of capacitor plates, wherein the first dielectric material, the second dielectric material, the first capacitor plate and the second capacitor plate are at least partially within the at least one primary trench and the at least one secondary trench in the substrate.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Feng Kuo, Chung-Chuan Tseng, Chia-Ping Lai
  • Patent number: 11315939
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Patent number: 11309383
    Abstract: A semiconductor structure, and a method of making the same includes a multiple electrode stacked capacitor containing a sequence of first metal layers interleaved with second metal layers. A quad-layer stack separates each of the first metal layers from each of the second metal layers, the quad-layer dielectric stack includes a first dielectric layer made of Al2O3, a second dielectric layer made of HfO2, a third dielectric layer made of Al2O3, and a fourth dielectric layer made of HfO2.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: April 19, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kisik Choi, Takashi Ando, Paul Charles Jamison, John Greg Massey, Eduard Albert Cartier
  • Patent number: 11271013
    Abstract: To provide a highly reliable semiconductor device that is suitable for miniaturization and an increase in density. The semiconductor device includes a first insulator over a substrate, a transistor including an oxide semiconductor over the first insulator, a second insulator over the transistor, and a third insulator over the second insulator. The first insulator and the third insulator have a barrier property with respect to oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor is enclosed with the first insulator and the third insulator that are in contact with each other in an edge of a region where the transistor is positioned.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: March 8, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11201055
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, forming a high-? dielectric layer directly on the semiconductor layer as formed, and annealing the semiconductor layer, the high-dielectric layer, and the substrate. The semiconductor layer is a Group III-V compound semiconductor.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: December 14, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chien-Hua Fu, Keng-Yung Lin, Yen-Hsun Lin, Kuanhsiung Chen, Juei-Nai Kwo, Minghwei Hong
  • Patent number: 11189224
    Abstract: An electroluminescent device includes a light-emitting element, a drive transistor that supplies a driving current corresponding to a gradation voltage to the light-emitting element, a first conductive layer that is electrically connected to a gate of the drive transistor, and a second conductive layer that is supplied a fixed potential and that is disposed on a same layer as the first conductive layer. The first conductive layer and the second conductive layer are disposed apart and electrically insulated from one another, and in plan view, the first conductive layer is surrounded by the second conductive layer.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 30, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hitoshi Ota, Ryoichi Nozawa
  • Patent number: 11189479
    Abstract: A method of forming an electronic device is disclosed. The method comprises forming a barrier layer on a silicon layer, and depositing a silicon oxide layer on the barrier layer. The formation of the barrier layer on the silicon layer minimizes parasitic oxidation of the underlying silicon layer and minimizes defects in the silicon layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: November 30, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Benjamin Colombeau, Johanes F. Swenberg, Steven C. H. Hung
  • Patent number: 11177298
    Abstract: Provided is a TFT driving backplane including, in top-to-bottom order, a sub-data line, a first insulating layer, a top capacitor plate, a second insulating layer and a bottom capacitor plate. In one side of the top capacitor plate is provided a notch filled upward by the first insulating layer provided with a first via extending vertically downward to the bottom capacitor plate. By moving the position where the sub-data line and the bottom capacitor plate are connected away from the top capacitor plate, holing is not required to be performed at the center of the capacitor and two-step opening alignment is avoided. Consequently, the requirement for alignment precision in photolithography is less critical, and the deviation due to two-step opening alignment is prevented. Meanwhile, by designing the margin and the one-way deviation, the short circuit in the capacitor can be avoided, and the effective capacitive area can be increased.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 16, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jiaxiang Zhao, Wenjin Cheng, Keran Jia
  • Patent number: 11049864
    Abstract: An apparatus comprises first electrodes vertically extending through an isolation material, a second electrode horizontally intervening between two or more of the first electrodes laterally neighboring one another, and a dielectric structure horizontally and vertically intervening between the second electrode and the two or more of the first electrodes. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 10991701
    Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Eric Blomiley
  • Patent number: 10941488
    Abstract: A pressurization type method for manufacturing elementary metal may include a metal precursor gas pressurization dosing operation of, in a state where an outlet of a chamber having a substrate is closed, increasing a pressure in the chamber by providing a metal precursor gas consisting of metal precursors, thereby adsorbing the metal precursors onto the substrate, a main purging operation of purging a gas after the metal precursor gas pressurization dosing operation, a reaction gas dosing operation of providing a reaction gas to reduce the metal precursors adsorbed on the substrate to elementary metal, after the main purging operation, and a main purging operation of purging a gas after the reaction gas dosing operation.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: March 9, 2021
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Myung Mo Sung, Kyu-Seok Han, Hongbum Kim
  • Patent number: 10903218
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Patent number: 10901022
    Abstract: An electrostatic detecting device adapted to an object. The electrostatic detecting device includes a substrate, a sensing electrode, a dielectric layer and a ground electrode. The substrate has a first surface and a second surface opposite to the first surface. The sensing electrode is disposed on the first surface and has a sensing surface. The sensing surface faces away from the first surface and configured to face the object. The dielectric layer having a dielectric constant greater than 1 is disposed on the second surface. The ground electrode is disposed apart from the sensing electrode by a spacing. The dielectric layer is disposed between the sensing electrode and the ground electrode.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: January 26, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Mean-Jue Tung, Shi-Yuan Tong, Yu-Ting Huang
  • Patent number: 10886362
    Abstract: A tri-layer dielectric stack is provided for a metal-insulator-metal capacitor (MIMCAP). Also, a metal-insulator-metal capacitor (MIMCAP) is provided having three or more electrodes. The tri-layer dielectric stack includes a first layer formed from a first metal oxide electrical insulator. The tri-layer dielectric stack further includes a second layer, disposed over the first layer, formed from ZrO2. The tri-layer dielectric stack also includes a third layer, disposed over the second layer, formed from a second metal oxide electrical insulator.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Eduard A. Cartier, Hemanth Jagannathan, Paul C. Jamison
  • Patent number: 10833092
    Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Alessandro Calderoni, Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Ashonita A. Chavan
  • Patent number: 10832940
    Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli
  • Patent number: 10833148
    Abstract: Capacitors and methods of forming the same include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Hemanth Jagannathan, Paul C. Jamison, John Rozen
  • Patent number: 10796212
    Abstract: An electronic system for identifying an article can include a printed memory having a plurality of contact pads electrically coupled to a plurality of landing pads positioned on a first side of a printed circuit board (PCB) substrate. The plurality of landing pads can be electrically coupled to a plurality of endless, concentric contact lines positioned on a second side of the PCB substrate through a plurality of vias that extend through a thickness of the PCB substrate and a plurality of traces that electrically couple the plurality of vias with the plurality of landing pads. To perform a memory operation on the printed memory, contact probes of a reader are physically and electrically contacted with the plurality of concentric contact lines. In some implementations, the memory operation can be performed on the printed memory irrespective of a rotational orientation of the printed memory relative to the reader.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: October 6, 2020
    Assignee: XEROX CORPORATION
    Inventors: Amit Trivedi, Kamran Uz Zaman, Karl Edwin Kurz
  • Patent number: 10707320
    Abstract: A method of forming a semiconductor device includes forming a hafnium-containing layer over a semiconductor layer, simultaneously performing a thermal annealing process and applying an electrical field to the hafnium-containing layer to form a ferroelectric hafnium-containing layer, and forming a gate electrode over the ferroelectric hafnium-containing layer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming Lin, Kai Tak Lam, Sai-Hooi Yeong, Chi On Chui, Ziwei Fang
  • Patent number: 10644100
    Abstract: The present disclosure relates to the field of semiconductor Integrated Circuit (IC) manufacture, and provides an InGaAs-based double-gate PMOS Field Effect Transistor (FET). The FET includes a bottom gate electrode, a bottom gate dielectric layer, a bottom gate interface control layer, an InGaAs channel layer, an upper interface control layer, a highly doped P-type GaAs layer, an ohmic contact layer, source/drain metal electrodes, a top gate dielectric layer and a top gate electrode. The source/drain metal electrodes are located on opposite sides of the ohmic contact layer. A gate trench structure is etched to an upper surface of the interface control layer between the source and drain metal electrodes. The top gate dielectric layer uniformly covers an inner surface of the gate trench structure, and the top gate electrode is provided on the top gate dielectric layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 5, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Shengkai Wang, Honggang Liu, Bing Sun, Hudong Chang
  • Patent number: 10629614
    Abstract: A semiconductor memory device includes a substrate defined with a first cell region, a slimming region extending from the first cell region in a first direction and a second cell region extending from the slimming region in the first direction; first and second electrode structures each including electrodes which are stacked on the substrate, and disposed to be separated from each other in a second direction crossing with the first direction, with a slit interposed therebetween; and a plurality of step-shaped holes disposed in the slimming region along the first direction, and respectively formed in the first and second electrode structures. Each of the step-shaped holes includes first step structures which face each other in the first direction, are symmetrical to each other and are separated by the slit and second step structures which face each other in the second direction and are symmetrical to each other.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: April 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Sung-Lae Oh
  • Patent number: 10611868
    Abstract: An object of the present invention is to provide a ferroelectric memory element which has a low driving voltage and which can be formed by coating. The present invention provides a ferroelectric memory element including at least: a first conductive film; a second conductive film; and a ferroelectric layer provided between the first conductive film and the second conductive film; wherein the ferroelectric layer contains ferroelectric particles and an organic component, and wherein the ferroelectric particles have an average particle size of from 30 to 500 nm.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 7, 2020
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Junji Wakita, Hiroji Shimizu, Shota Kawai, Seiichiro Murase
  • Patent number: 10559649
    Abstract: A capacitor structure is described. A metal insulator metal capacitor in an integrated circuit device includes a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is disposed over the extended top face of the bottom capacitor plate. A top capacitor plate is disposed in a top, remainder portion of the trench on top of the high-k dielectric layer.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Theodorus E Standaert
  • Patent number: 10388585
    Abstract: A semiconductor device includes: a semiconductor substrate; a gate electrode on the semiconductor substrate; a SiN film on the semiconductor substrate and the gate electrode; and an oxide film on the SiN film, wherein the oxide film is an atomic layer deposition film including atomic layers alternately deposited.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: August 20, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takayuki Hisaka, Masahiro Totsuka, Tasuku Sumino
  • Patent number: 10381455
    Abstract: A diffusion barrier system may prevent migration of gold, oxygen, or both on a plurality of ohmic contacts. The diffusion barrier system may include a first barrier system or a second barrier system. Each barrier system may include a first metallization layer, a second metallization layer, and a third metallization layer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: August 13, 2019
    Assignee: United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: Robert Okojie
  • Patent number: 10219373
    Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface. Methods include soaking a substrate surface comprising hydroxyl-terminations with a silylamine to form silyl ether-terminations and depositing a film onto a surface other than the silyl ether-terminated surface.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: February 26, 2019
    Assignee: Applied Materials, Inc.
    Inventors: David Thompson, Mark Saly, Bhaskar Jyoti Bhuyan
  • Patent number: 10134586
    Abstract: A technique includes forming a laminated film on a substrate by performing a cycle a predetermined number of times. The cycle includes forming a first film which contains at least a predetermined element and oxygen, and forming a second film which contains at least the predetermined element, oxygen and carbon. The first film and the second film are laminated to form the laminated film.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: November 20, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takafumi Nitta, Satoshi Shimamoto, Yoshiro Hirose
  • Patent number: 10103026
    Abstract: A method of forming a material layer includes providing a substrate into a reaction chamber, providing a source material onto a substrate, the source material being a precursor of a metal or semimetal having a ligand, providing an ether-based modifier on the substrate, purging an inside of the reaction chamber, and reacting a reaction material with the source material to form the material layer.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: October 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-min Moon, Youn-soo Kim, Han-jin Lim, Yong-jae Lee, Se-hoon Oh, Hyun-jun Kim, Jin-sun Lee
  • Patent number: 9916980
    Abstract: A method of forming a layer on a substrate is provided by providing the substrate with a hardmask material. The hardmask material is infiltrated with infiltration material during N infiltration cycles by: a) providing a first precursor to the hardmask material on the substrate in the reaction chamber for a first period T1; b) removing a portion of the first precursor for a second period T2; and, c) providing a second precursor to the hardmask material on the substrate for a third period T3, allowing the first and second precursor to react with each other forming the infiltration material.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 13, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Werner Knaepen, Jan Willem Maes, Bert Jongbloed, Krzysztof Kamil Kachel, Dieter Pierreux, David Kurt De Roest
  • Patent number: 9899209
    Abstract: An electrically conductive thin film including a plurality of nanosheets including a doped titanium oxide represented by Chemical Formula 1 and having a layered crystal structure: (A?Ti1??)O2+???Chemical Formula 1 wherein, in Chemical Formula 1, ? is greater than 0, A is at least one dopant metal selected from Nb, Ta, V, W, Cr, and Mo, and ? is greater than 0 and less than 1. Also, an electronic device including the electrically conductive thin film.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doh Won Jung, Hee Jung Park, Yoon Chul Son, Yun Sung Woo, Jongmin Lee, Yong Hee Cho, Kyoung-Seok Moon, Jae-Young Choi, Kimoon Lee
  • Patent number: 9647208
    Abstract: Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Brian S. Doyle, Charles C. Kuo, Robert S. Chau, Eric R. Dickey, Michael Stephen Bowen, Sey-Shing Sun
  • Patent number: 9559300
    Abstract: In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 31, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki Ode, Takeshi Yamaguchi, Takeshi Takagi, Toshiharu Tanaka, Masaki Yamato
  • Patent number: 9484419
    Abstract: Provided are an oxide thin film, a method for post-treating an oxide thin film and an electronic apparatus. An oxide thin film is an oxide thin film with a single layer including a metal oxide, and the physical properties of the oxide thin film may change in the thickness direction thereof.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: November 1, 2016
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Hyun Jae Kim, Young Jun Tak, Doo Hyun Yoon, Sung Pyo Park, Heesoo Lee
  • Patent number: 9461242
    Abstract: A magnetic cell includes a free region between an intermediate oxide region (e.g., a tunnel barrier) and a secondary oxide region. Both oxide regions may be configured to induce magnetic anisotropy (“MA”) with the free region, enhancing the MA strength of the free region. A getter material proximate to the secondary oxide region is formulated and configured to remove oxygen from the secondary oxide region, reducing an oxygen concentration and an electrical resistance of the secondary oxide region. Thus, the secondary oxide region contributes only minimally to the electrical resistance of the cell core. Embodiments of the present disclosure therefore enable a high effective magnetoresistance, low resistance area product, and low programming voltage along with the enhanced MA strength. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: October 4, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Witold Kula
  • Patent number: 9406883
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first electrode over the semiconductor substrate. The first electrode has a ring-shaped cross section. The semiconductor device structure also includes a resistance-switching layer over the first electrode and a second electrode over the resistance-switching layer.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Ching-Pei Hsieh, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 9385130
    Abstract: In order to achieve the reduction of contact resistance by forming a metal silicide layer with a sufficient thickness in an interface between a polycrystalline silicon plug and an upper conductive plug, the polycrystalline silicon plug contains germanium, which is ion-implanted before forming the metal silicide layer.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: July 5, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Yoichi Fukushima
  • Patent number: 9287134
    Abstract: Methods of selectively etching titanium oxide relative to silicon oxide, silicon nitride and/or other dielectrics are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and/or a chlorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium oxide. The plasmas effluents react with exposed surfaces and selectively remove titanium oxide while very slowly removing other exposed materials. A direction sputtering pretreatment is performed prior to the remote plasma etch and enables an increased selectivity as well as a directional selectivity. In some embodiments, the titanium oxide etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: March 15, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Lin Xu, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9269707
    Abstract: In IC chips for display device driving, an operational amplifier is widely used in input and output circuits, and a capacitor in a medium withstanding voltage chip is used as a compensation capacitor. As for this product area, cost competitiveness is very important. Therefore, a MIS capacitor with good area efficiency is widely used. However, unlike a so-called varactor widely used in a VCO circuit, a characteristic of as small a voltage dependence of the capacitor as possible is used. Therefore, an additional process is added to reduce the voltage dependence of the capacitor, but there is a problem of an increase in process cost. A semiconductor substrate side capacitor electrode in a MIS capacitor within a first conduction type medium withstanding voltage chip used in an I/O circuit or the like on a semiconductor integrated circuit device is formed in a first conduction type low withstanding voltage well region.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: February 23, 2016
    Assignee: Synaptics Display Devices GK
    Inventors: Masatoshi Taya, Kunihiko Kato
  • Patent number: 9231204
    Abstract: Embodiments include low voltage embedded memory having conductive oxide and electrode stacks. A material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Brian S. Doyle, Charles C. Kuo, Robert S. Chau, Eric R. Dickey, Michael Stephen Bowen, Sey-Shing Sun
  • Patent number: 9224644
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: December 29, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sandip Niyogi, Amol Joshi, Chi-I Lang, Salil Mujumdar
  • Patent number: 9218993
    Abstract: Provided is a method of forming a tantalum oxide-based film having good step coverage while controlling an oxygen concentration in the film. The method includes forming a tantalum nitride layer on a substrate by supplying a source gas including a tantalum and a nitriding agent into a process chamber wherein the substrate is accommodated under a condition where a chemical vapor deposition (CVD) reaction is caused; oxidizing the tantalum nitride layer by supplying an oxidizing agent into the process chamber under a condition where an oxidation reaction of the tantalum nitride layer by the oxidizing agent is unsaturated; and forming on the substrate a conductive tantalum oxynitride film wherein an oxygen is stoichiometrically insufficient with respect to the tantalum and a nitrogen by alternately repeating forming the tantalum nitride layer on the substrate and oxidizing the tantalum nitride layer a plurality of times.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: December 22, 2015
    Assignee: HITACHI KOKUSAI ELECTRIC, INC.
    Inventors: Kazuhiro Harada, Hideharu Itatani
  • Patent number: 9177784
    Abstract: Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: November 3, 2015
    Assignee: ASM IP Holdings B.V.
    Inventors: Petri Raisanen, Michael Givens, Mohith Verghese
  • Patent number: 9159829
    Abstract: Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 9099300
    Abstract: Disclosed is a multilayer insulator, a metal-insulator-metal (MIM) capacitor with the same, and a fabricating method thereof. The capacitor includes: a first electrode; an insulator disposed on the first electrode, the insulator including: a laminate structure in which an aluminum oxide (Al2O3) layer and a hafnium oxide (HfO2) layer are laminated alternately in an iterative manner and a bottom layer and a top layer are formed of the same material; and a second electrode disposed on the insulator.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: August 4, 2015
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Kwan-Soo Kim, Soon-Wook Kim
  • Patent number: 9093636
    Abstract: Electronic apparatus, systems, and methods include a resistive random access memory cell having an oxygen gradient in a variable resistive region of the resistive random access memory cell and methods of forming the resistive random access memory cell. Oxygen can be incorporated into the resistive random access memory cell by ion implantation. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: July 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Swapnil Lengade, Dale W. Collins, Durai Vishak Nirmal Ramaswamy, Yongjun Jeff Hu
  • Patent number: 9071222
    Abstract: A microacoustic component includes an active layer and an electrode. The electrode includes a first metal layer facing the active layer, a second metal layer facing away from the active layer, and a third layer arranged between the first metal layer and the second metal layer. The third layer serves as a diffusion barrier.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: June 30, 2015
    Assignee: EPCOS AG
    Inventors: Andreas Link, Gudrun Henn, Rainer Braun
  • Patent number: 9054225
    Abstract: An embodiment of an electronic device integrated in a chip of semiconductor material and an embodiment of a corresponding production method are proposed. The electronic device includes a capacitor having a first conductive plate, a second conductive plate, and an insulating layer for insulating the first plate from the second plate. In an embodiment of the disclosure, at least a selected one between the first plate and the second plate has a non-uniform thickness.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: June 9, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Antonio Di Franco
  • Patent number: 9048186
    Abstract: A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: June 2, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo Bin Huang, Hsin-Chien Lu, Ryan Chia-Jen Chen, Chi-Ming Yang, Chyi Shyuan Chern, Chin-Hsiang Lin
  • Publication number: 20150132905
    Abstract: The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 14, 2015
    Inventors: Ta-Chuan Liao, Chien-Kuo Yang, Felix Ying-Kit Tsui, Shih-Hsien Chen, Liang-Tai Kuo, Chun-Yao Ko