Semiconductor device and method for fabricating the same
A semiconductor device and a method of fabricating a semiconductor device is provided. The semiconductor device can include a semiconductor substrate; an interlayer dielectric layer having a damascene pattern formed on the semiconductor substrate; a diffusion barrier formed in the damascene pattern and made of a trivalent material; a seed layer formed on the diffusion barrier; and a copper interconnection formed on the seed layer. In one embodiment, the trivalent material is CoFeB.
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The present application claims the benefit under 35 U.S.C. §119 of Korean Patent Application No. 10-2006-073474, filed Aug. 3, 2006, which is hereby incorporated by reference in its entirety.
BACKGROUNDIn general, a metal interconnection is used to electrically interconnect devices in a semiconductor device. Aluminum (Al), aluminum alloy, and tungsten (W) are often used as the material for a metal interconnection.
However, since semiconductor devices are highly integrated, it is difficult to use such metals because of their low melting points and high specific resistances. Copper (Cu), gold (Au), silver (Ag), cobalt (Co), chromium (Cr), and nickel (Ni) all have excellent conductivity and can be used as the material for a metal interconnection. Particularly, copper and copper alloy, which have low specific resistivity, excellent reliability for electron migration (EM) and stress migration (SM), and low production cost, have been widely used.
Metal interconnections using copper are often formed using a damascene process. The damascene process forms a trench in an insulating layer through a photo process and an etching process and then fills a conductive material in the trench, such as W, Al, or Cu. Next, the majority of the conductive material is removed, leaving a required interconnection using an etch-back or chemical mechanical polishing (CMP) method, thereby forming an interconnection having the shape corresponding to the trench.
However, copper is not suitable for a dry etching process and does not easily adhere to SiO2. Copper also has low thermo-dynamical stability and low resistance against corrosion. Furthermore, copper may serve as a deep level dopant that is diffused into silicon to produce acceptor and donor states in a band gap, thereby causing a leakage current or malfunction of a device.
Thus, there exists a need in the art for an effective diffusion barrier layer that can be used with copper.
BRIEF SUMMARYEmbodiments of the present invention provide a semiconductor device, wherein an amorphous layer is used as a diffusion barrier for preventing diffusion of copper, to enhance the performance of the semiconductor.
According to an embodiment, a semiconductor device is provided, including a semiconductor substrate, an interlayer dielectric layer having a damascene pattern formed on the semiconductor substrate, a diffusion barrier formed in the damascene pattern and made of a trivalent material, such as CoFeB, a seed layer formed on the diffusion barrier, and a copper interconnection formed on the seed layer.
Another embodiment of the present invention provides a method of fabricating a semiconductor device, which includes: forming an interlayer dielectric layer on a semiconductor substrate, and forming a damascene pattern in the interlayer dielectric layer; depositing a trivalent material, such as CoFeB, in a predetermined thickness on the interlayer dielectric layer, thereby forming a diffusion barrier; depositing a seed layer on the diffusion barrier; and filling a copper interconnection in the damascene pattern.
Embodiments of the present invention are described below with reference to the accompanying drawings.
Referring to
Each of the materials shows a peak in the graph of
As shown in
Here, the peak of the intensity at about 41 degrees is shown by a property of IrMn.
In the structure in which Ta, Cu, IrMn, Cu and CoFeB are stacked, sputtering is performed in an order of CoFeB, Cu, IrMn, Cu and Ta. This structure helps determine whether or not the diffusion of Cu is prevented by identifying that Cu is observed in only a predetermined time zone as sputtering time increases.
After forming the stacked structure, it can be seen in
Fe and Co are sputtered in an interval within 0.5 minute of initial sputtering, and Cu is extremely weakly sputtered. Thus, diffusion of Cu is inhibited by the CoFeB. Based on these tests, it can be seen that amorphous trivalent materials can provide improved diffusion barriers for copper. In an embodiment, CoFeB is used as a diffusion barrier of Cu. In an alternative embodiment, CoFeN, which is an amorphous trivalent material, is used as a diffusion barrier for Cu.
In an embodiment, the present invention provides a method of fabricating a semiconductor device using a trivalent material such as CoFeB as a diffusion barrier layer.
Referring to
Referring to
The diffusion barrier 4 can be formed by depositing a trivalent material through a physical vapor deposition (PVD) method. In an embodiment the trivalent material is CoFeB. In another embodiment, the trivalent material is CoFeN. In many embodiments using CoFeB as the diffusion barrier 4, the composition ratio of the CoFeB is set as cobalt (Co) (in the range of about 30% to about 70%): iron (Fe) (in the range of about 70% to about 30%): boron (B) (in the range of about 5 to about 10%). The diffusion barrier 4 can have a thickness of 500 Å to 1000 Å.
The composition ratio of Co and Fe is high relative to that of B in the CoFeB for the purpose of enhancing electric conductivity for connection between layers in the semiconductor device.
Referring to
Referring to
Referring to
In many embodiments, the material used for the diffusion barrier 4 is a trivalent amorphous material. Trivalent amorphous materials provide an improved barrier against copper diffusion in semiconductor devices. In an embodiment, the diffusion barrier 4 is CoFeB. In another embodiment, the diffusion barrier is CoFeN.
Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification do not necessarily all refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is to be understood that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments.
Although the invention has been described with reference to certain embodiments, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure and the appended claims. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Claims
1. A semiconductor device comprising:
- a semiconductor substrate;
- an interlayer dielectric layer having a damascene pattern on the semiconductor substrate;
- a diffusion barrier comprising a trivalent material formed in the damascene pattern;
- a seed layer formed on the diffusion barrier; and
- a copper interconnection formed on the seed layer;
- wherein the diffusion barrier comprises CoFeN.
2. The semiconductor device according to claim 1, wherein the diffusion barrier comprises an amorphous trivalent material.
3. The semiconductor device according to claim 1, wherein the diffusion barrier has a thickness of about 500 Å to about 1000 Å.
4. A method of fabricating a semiconductor device, comprising:
- forming an interlayer dielectric layer on a semiconductor substrate;
- forming a damascene pattern in the interlayer dielectric layer;
- depositing a trivalent material on the interlayer dielectric layer to form a diffusion barrier;
- depositing a seed layer on the diffusion barrier; and
- filling a copper interconnection in the damascene pattern;
- wherein the diffusion barrier comprises CoFeN.
5. The method according to claim 4, wherein the diffusion barrier comprises an amorphous trivalent material.
6. The method according to claim 4, wherein the diffusion barrier has a thickness of about 500 Å to about 1000 Å
7008871 | March 7, 2006 | Andricacos et al. |
20020160698 | October 31, 2002 | Sato et al. |
20030164302 | September 4, 2003 | Uzoh et al. |
20050045486 | March 3, 2005 | Sahoda et al. |
20050126919 | June 16, 2005 | Kubota et al. |
20060170068 | August 3, 2006 | Ren et al. |
10-2004-0059490 | February 2006 | KR |
10-2004-0111154 | June 2006 | KR |
Type: Grant
Filed: Jul 25, 2007
Date of Patent: Jan 27, 2009
Patent Publication Number: 20080029891
Assignee: Dongbu Hitek Co., Ltd. (Seoul)
Inventor: Sung Joong Joo (Seo-gu)
Primary Examiner: Marcos D. Pizarro
Assistant Examiner: Igwe U. Anya
Attorney: Saliwanchik, Lloyd & Saliwanchik
Application Number: 11/782,698
International Classification: H01L 23/48 (20060101); H01L 23/52 (20060101); H01L 29/40 (20060101);