Abstract: Apparatuses and methods to provide electronic devices having metal films are provided. Some embodiments of the disclosure utilize a metallic tungsten layer as a liner that is filled with a metal film comprising cobalt. The metallic tungsten layer has good adhesion to the cobalt leading to enhanced cobalt gap-fill performance.

Abstract: Disclosed in the present disclosure are a cleaning machine and a cleaning method. The cleaning machine includes: a wet cleaning module, configured to execute a wet cleaning process on a wafer; a dry cleaning module, configured to execute a dry cleaning process on the wafer; a conveying module, configured to input the wafer into the wet cleaning module or the dry cleaning module, or output the wafer from the wet cleaning module or the dry cleaning module; a transferring module, configured to transfer the wafer from the wet cleaning module to the dry cleaning module or transfer the wafer from the dry cleaning module to the wet cleaning module; and a processing module, configured to extract gas from the transferring module.

Abstract: A conductive contact structure of a solar cell is provided, includes a substrate; a semiconductor region; and an electrode. The semiconductor region is disposed on or in the substrate. The electrode is disposed in the semiconductor region. The electrode includes a seed layer in contact with the semiconductor region. The seed layer includes an alloy material, and includes a main component and an improved component. The main component is one or more metals having an average refractive index lower than 2 and a wavelength in a range of 850-1200 nm, and the improved component includes any one or more of Mo, Ni, Ti, W, Cr, Mn, Pd, Bi, Nb, Ta, Pa, Si, and V.

Abstract: The present application discloses a method for fabricating a semiconductor device with graphene layers The method includes providing a substrate; forming a first passivation layer above the substrate; forming a redistribution layer on the first passivation layer; forming a first adjustment layer on the redistribution layer; forming a pad layer on the first adjustment layer; forming a second adjustment layer between the pad layer and the first adjustment layer; forming a second passivation layer on the first passivation layer; wherein the first adjustment layer and the second adjustment layer are formed of graphene.

Abstract: A system for three-dimensional printing is disclosed. The system comprises: a rotary tray configured to rotate about a vertical axis; a printing head, each having a plurality of separated nozzles; and a controller configured for controlling the inkjet printing head to dispense, during the rotation, droplets of building material in layers, such as to print a three-dimensional object on the tray.

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: A copper electroplating solution comprising a copper salt, a source of halide ions, and a linear or branched polyhydroxyl. The copper electroplating solution is used to deposit copper having a high density of nanotwinned columnar copper grains on a substrate. The linear or branched polyhydroxyl may comprise a reaction product between 2,3-epoxy-1-propanol and aminic alcohol or ammonium alcohol.

Abstract: A semiconductor structure may include a metal line, a via above and in electrical contact with the metal lines, and a dielectric layer positioned along a top surface of the metal lines. A top surface of the dielectric layer may be below the dome shaped tip of the via. A top portion of the via may include a dome shaped tip. The semiconductor structure may include a liner positioned along the top surface of the dielectric layer and a top surface of the dome shaped tip of the via. The liner may be made of tantalum nitride or titanium nitride. The dielectric layer may be made of a low-k material. The metal line and the via may be made of ruthenium. The metal line may be made of molybdenum.

Abstract: A method of manufacturing a semiconductor package which is at least in part covered by an electromagnetic interference shielding layer. The method includes at least these steps: i. providing the semiconductor package and an ink composition having at least a compound comprising at least one metal precursor and at least one organic compound; ii. applying at least a part of the ink composition onto the semiconductor package, wherein a precursor layer is formed; and iii. treating the precursor layer with an irradiation of a peak wavelength in the range from 100 nm to 1 mm. Further disclosed is a semiconductor package comprising an electromagnetic interference shielding layer comprising at least one metal, wherein the semiconductor package is obtainable by the aforementioned method. Still further disclosed are a semiconductor package comprising an electromagnetic interference shielding layer having a specific conductance and thickness, and uses of an ink composition.

Abstract: A stabilized elementary metal structure is disclosed. The stabilized elementary metal structure may include an elementary metal having at least one layer and having a two-dimensional layer structure, and an organic molecular layer provided on at least one of a top surface and a bottom surface of the elementary metal.

Abstract: A substrate processing apparatus includes a substrate holder configured to horizontally hold and rotate a substrate which has a recess and a base metal layer exposed from a bottom surface of the recess; and a pre-cleaning liquid supply configured to supply a pre-cleaning liquid such as dicarboxylic acid or tricarboxylic acid onto the substrate being held and rotated by the substrate holder, to thereby pre-clean the base metal layer. A temperature of the pre-cleaning liquid on the substrate is equal to or higher than 40° C.

Abstract: A substrate, a display panel, and a substrate manufacturing method are proposed. The substrate includes a base layer; partitioning walls located on the base layer and dividing the base layer into a plurality of pixel regions, and patterns located in each of the pixel regions of the base layer, and guiding spread of a liquid drop discharged to the base layer.

Abstract: A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

Abstract: Additive manufacturing processes, such as powder bed fusion of thermoplastic particulates, may be employed to form printed objects in a range of shapes. It is sometimes desirable to form conductive traces upon the surface of printed objects. Conductive traces and similar features may be introduced during additive manufacturing processes by incorporating a metal precursor in a thermoplastic printing composition, converting a portion of the metal precursor to discontinuous metal islands using laser irradiation, and performing electroless plating. Suitable printing compositions may comprise a plurality of thermoplastic particulates comprising a thermoplastic polymer, a metal precursor admixed with the thermoplastic polymer, and optionally a plurality of nanoparticles disposed upon an outer surface of each of the thermoplastic particulates, wherein the metal precursor is activatable to form metal islands upon exposure to laser irradiation. Melt emulsification may be used to form the thermoplastic particulates.

Abstract: A cleaning device. The cleaning device includes: a base body, a spray head, and a main worktable and a first auxiliary worktable that are provided on the base body; a nozzle of the spray head is provided facing a mounting surface of the main worktable, and the spray head is configured to move in a preset direction vertical to the mounting surface to clean a to-be-cleaned panel on the mounting surface; the first auxiliary worktable is located at one end of the main worktable along the preset direction, and a first surface of the first auxiliary worktable facing the spray head is parallel to the mounting surface, and the first surface is higher than or flush with the mounting surface.

Abstract: Provided herein are methods for forming a layer on a substrate wherein the layer is formed selectively on a first region of the substrate relative to a second region having a composition different than the first region. Methods of the invention include selectively forming a layer using an inhibitor agent capable of reducing the average acidity of a first region of the substrate having a composition characterized by a plurality of hydroxyl groups. Methods of the invention include selectively forming a layer by exposure of the substrate to: (i) an inhibitor agent comprising a substituted or an unsubstituted amine group, a substituted or an unsubstituted pyridyl group, a carbonyl group, or a combination of these, and (ii) a precursor gas comprising one or more ligands selected from the group consisting of a carbonyl group, an allyl group, combination thereof.

Abstract: Discussed is a solar cell including a semiconductor substrate, a conductive region disposed in the semiconductor substrate or over the semiconductor substrate, and an electrode electrically connected to the conductive region. The electrode includes a first electrode part and a second electrode part disposed over the first electrode part. The second electrode part includes a particle connection layer formed by connecting a plurality of particles including a first metal and a cover layer including a second metal different from the first metal and covering at least the outside surface of the particle connection layer.

Abstract: An organic interposer includes: a first organic insulating layer including a groove; a first metal wire located in the groove; a barrier metal material covering the first metal wire; and a second metal wire located above the first metal wire, wherein the barrier metal material includes: a first barrier metal film interposed between the first metal wire and an inner surface of the groove; and a second barrier metal film located on the first metal wire, and wherein the second metal wire is in contact with both of the first barrier metal film and the second barrier metal film.

Abstract: According to one embodiment of the present disclosure, there is provided a substrate processing method including: providing a substrate; forming a seed layer on a surface of the substrate by heating a stage on which the substrate is placed to a first temperature and supplying a first source gas to the substrate; and forming a metal-containing film by heating the stage on which the substrate is placed to a second temperature and supplying a second source gas and a first reducing gas to the substrate on which the seed layer is formed.

Abstract: A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.

Abstract: A semiconductor device and a method of producing the semiconductor device are described. The semiconductor device includes: a semiconductor substrate; a metallization layer over the semiconductor substrate; a plating over the metallization layer, the plating including NiP; a passivation over the metallization layer and laterally adjacent the plating such that a surface of the plating that faces away from the semiconductor substrate is uncovered by the passivation, wherein a seam is present along an interface between the passivation and the plating; and a structure that covers the seam along a periphery of the plating and delimits a bondable area for the plating. The structure extends from the periphery of the plating onto the passivation. The structure includes an imide having a curing temperature below a recrystallization temperature of the NiP or an oxide having a deposition temperature below the recrystallization temperature of the NiP.

Abstract: A method for microstructure modification of conducting lines is provided. An electroplating process is performed to deposit the metal thin film/conducting line(s) with a face-centered cubic (FCC) structure and a preferred crystallographic orientation over a surface of a substrate. The metal thin film/conducting line(s) is subsequently subjected to a thermal annealing process to modify its microstructure with the grain sizes in a range of 5 ?m to 100 ?m. The thermal annealing process is conducted at the temperature of above 25 degrees Celsius and below 240 degrees Celsius.

Abstract: The present invention relates to a method for forming a circuit using a seed layer. The method for forming a circuit using a seed layer according to the present invention, may realize a fine pitch, increase the adhesion of the circuit, and prevent the migration phenomenon.

Abstract: A method of forming a semiconductor structure is provided. The method includes etching a trench in a template layer over a substrate, forming a seed structure over a bottom surface of the trench, forming a dielectric cap over the seed structure, and growing a single crystal semiconductor structure within the trench using a vapor liquid solid epitaxy growth process. The single crystal semiconductor structure is grown from a liquid-solid interface between the seed structure and the bottom surface of the trench.

Abstract: A method of forming an article, including: inserting a conductive material within a via a wafer, wherein the conductive material comprises a first alloy comprising a first metal and a second metal; and contacting the conductive material with a solution comprising ions of a third metal, wherein the ions of the third metal galvanically displace a portion of the second metal from the first alloy to form a second alloy with the first metal.

Abstract: In one embodiment, a conductive connector for a microelectronic component may be formed with a noble metal layer, acting as an adhesion/wetting layer, disposed between a barrier liner and a conductive fill material. In a further embodiment, the conductive connector may have a noble metal conductive fill material disposed directly on the barrier liner. The use of a noble metal as an adhesion/wetting layer or as a conductive fill material may improve gapfill and adhesion, which may result in the conductive connector being substantially free of voids, thereby improving the electrical performance of the conductive connector relative to conductive connectors without a noble metal as the adhesion/wetting layer or the conductive fill material.

Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.

Abstract: There is provided a substrate processing apparatus, including: a film forming part configured to form a metal-containing film on a front surface of a substrate; a film cleaning part configured to clean the metal-containing film formed on a peripheral edge portion of the substrate; and a controller. The controller is configured to control the film forming part so as to form the metal-containing film on the front surface of the substrate, and control the film cleaning part so as to supply a first chemical liquid and a second chemical liquid.

Abstract: A crosslinked self-assembled monolayer (SAM), comprising surface groups containing a nitrogen-heterocycle, was formed on an oxygen plasma-treated silicon oxide or hafnium oxide top surface of a substrate. The SAM is covalently bound to the underlying oxide layer. The SAM was patterned by direct write methods using ultraviolet (UV) light of wavelength 193 nm or an electron beam, forming a line-space pattern comprising non-exposed SAM features. The non-exposed SAM features non-covalently bound DNA-wrapped carbon nanotubes (DNA-CNT) deposited from aqueous solution with a selective placement efficiency of about 90%. Good alignment of carbon nanotubes to the long axis of the SAM features was also observed. The resulting patterned biopolymer features were used to prepare a CNT based field effect transistor.

Abstract: A method of manufacturing a semiconductor structure includes: forming a dielectric layer over a conductive layer; removing a portion of the dielectric layer to form an opening exposing a portion of the conductive layer; filling a ruthenium-containing material in the opening and in contact with the dielectric layer; and polishing the ruthenium-containing material using a slurry including an abrasive and an oxidizer selected from the group consisting of hydrogen peroxide (H2O2), potassium periodate (KIO4), potassium iodate (KIO3), potassium permanganate (KMnO4), iron(III) nitrate (FeNO3) and a combination thereof.

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.

Abstract: Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line.

Abstract: An interconnection structure includes a first dielectric layer, a conductive element, a second dielectric layer, a bottom via, a dielectric spacer, and a top via. The conductive element is embedded in the first dielectric layer. The second dielectric layer is over the first dielectric layer and the conductive element. The second dielectric layer has an opening exposing the conductive element. The bottom via is disposed in the opening and in contact with the conductive element. The dielectric spacer is disposed in the opening and is in contact with the bottom via and the second dielectric layer. The top via is disposed in the opening and covering the bottom via and the dielectric spacer.

Abstract: A metal wiring layer can be formed within a recess of a substrate and an unnecessary plating layer is not left on a surface of the substrate. A metal wiring layer forming method includes forming a first plating layer 7 as a protection layer at least on a tungsten or tungsten alloy 4 formed on a bottom surface 3a of a recess 3 of a substrate 2; removing an unnecessary plating layer 7a formed on a surface 2a of the substrate 2; and forming a second plating layer 8 on the first plating layer 7 within the recess 3.

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon film are provided. First, a substrate having features formed in a first surface thereof is positioned in a processing chamber. A conformal deposition process is then performed to deposit a conformal silicon liner layer on the sidewalls of the features and the exposed first surface of the substrate between the features. A flowable deposition process is then performed to deposit a flowable silicon layer over the conformal silicon liner layer. A curing process is then performed to increase silicon density of the flowable silicon layer. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition two-step process to realize seam-free gapfilling between features with high quality amorphous silicon film.

Abstract: Disclosed herein are methods comprising illuminating a first location of an optothermal substrate with electromagnetic radiation, wherein the optothermal substrate converts at least a portion of the electromagnetic radiation into thermal energy. The optothermal substrate can be in thermal contact with a liquid sample comprising a plurality of capped particles and a plurality of surfactant micelles, the liquid sample having a first temperature. The methods can further comprise generating a confinement region at a location in the liquid sample proximate to the first location of the optothermal substrate, wherein at least a portion of the confinement region has a second temperature that is greater than the first temperature such that the confinement region is bound by a temperature gradient. The methods can further comprise trapping and depositing at least a portion of the plurality of capped particles.

Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.

Abstract: Layer-by-layer thickness control of an electroplated film can be achieved by using a cyclic deposition process. The cyclic process involves forming a layer (or partial layer) of hydrogen on a surface of the substrate, then displacing the layer of hydrogen with a layer of metal. These steps are repeated a number of times to deposit the metal film to a desired thickness. Each step in the cycle is self-limiting, thereby enabling atomic level thickness control.

Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon film are provided. First, a substrate having features formed in a first surface thereof is positioned in a processing chamber. A conformal deposition process is then performed to deposit a conformal silicon liner layer on the sidewalls of the features and the exposed first surface of the substrate between the features. A flowable deposition process is then performed to deposit a flowable silicon layer over the conformal silicon liner layer. A curing process is then performed to increase silicon density of the flowable silicon layer. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition two-step process to realize seam-free gapfilling between features with high quality amorphous silicon film.

Abstract: The present invention relates to a method for manufacturing a nanoparticle array, a surface plasmon resonance-based sensor, and a method for analyzing using the same. According to one embodiment of the present invention, after a mixed solution of an ionized binder and conductive nanoparticles is prepared, a substrate is dipped into the mixed solution. Thereafter, by applying an electric field to the mixed solution into which the substrate is dipped so as to induce coating of the conductive nanoparticles on the substrate, it is possible to manufacture, by a wet method, a nanoparticle array in which the conductive nanoparticles are quickly coated on the substrate with high density.

Abstract: Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an underlying, interconnected metal line, vias are fabricated in the interconnect structure to be self-aligned with an underlying, interconnected metal line. In this regard, underlying metal lines are formed in a dielectric layer. A recess is formed in an underlying metal line below a top surface of an inter-layer dielectric. A stop layer is disposed above the inter-layer dielectric and within the recess of the underlying metal line. The stop layer allows a via tunnel to be formed (e.g., etched) down within the recess of the underlying metal line to self-align the via tunnel with the underlying metal line. A conductive material is then deposited in the via tunnel extending into the recess to form the self-aligned via interconnected to the underlying metal line.

Abstract: A method of producing a layer structure includes forming a first organic layer by applying a first composition including an organic compound on a substrate having a plurality of patterns, applying a solvent on the first organic layer to remove a part of the first organic layer, and applying a second composition including an organic compound on a remaining part of the first organic layer and forming a second organic layer through a curing process.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: A technique relates to manufacturing a nanogap. An oxide layer is disposed on top of a substrate. A release layer is disposed in a pattern on top of the oxide layer. A patterned trench is etched into the oxide layer using the pattern of the release layer. A metal layer is disposed on the release layer and in the patterned trench. A polish removes the release layer, thereby removing both the release layer and a portion of the metal layer having been disposed on top of the release layer, such that the metal layer remaining includes a first metal part and a second metal part connected by a metal nanowire. The metal layer remaining is coplanar with the oxide layer. A nanochannel is formed in the oxide layer in a region of the metal nanowire. The nanogap is formed in the metal nanowire separating the first and second metal parts.

Abstract: An UBM electrode structure body for a radiation detector and a radiation detector arranged with the UBM electrode structure body are provided for suppressing peeling and having high electrode adhesion. In addition, a manufacturing method of an UBM electrode structure body for a radiation detector and a manufacturing method of a radiation detector using the UBM electrode structure body are provided in which peeling does not occur during UBM structure formation, a solder bonding process or bonding of a signal line to a Pt layer. The UBM electrode structure body for a radiation detector of the present invention is arranged with a CdTe substrate or CdZnTe substrate and a Pt electrode layer arranged on the CdTe substrate or CdZnTe substrate, adhesion of the Pt electrode layer with respect to the CdTe substrate or the CdZnTe substrate being 0.5 N/cm or more.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a substrate; forming an MRAM structure over the substrate; forming a first dielectric layer over the MRAM structure; forming a stop layer over the first dielectric layer; forming a second dielectric layer over the stop layer; and removing the second dielectric layer, the stop layer and at least a portion of the first dielectric layer through a planarization operation without exposing a top electrode of the MRAM structure. Associated methods are also disclosed.

Abstract: Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.

Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.

Abstract: A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.