From A Liquid, E.g., Electrolytic Deposition (epo) Patents (Class 257/E21.174)
  • Patent number: 10312074
    Abstract: A method of producing a layer structure includes forming a first organic layer by applying a first composition including an organic compound on a substrate having a plurality of patterns, applying a solvent on the first organic layer to remove a part of the first organic layer, and applying a second composition including an organic compound on a remaining part of the first organic layer and forming a second organic layer through a curing process.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Min-Soo Kim, Hyun-Ji Song, Sun-Hae Kang, Sung-Min Kim, Sung-Hwan Kim, Young-Min Kim, Yun-Jun Kim, Hea-Jung Kim, Youn-Hee Nam, Jae-Yeol Baek, Byeri Yoon, Yong-Woon Yoon, Chung-Heon Lee, Seulgi Jeong, Yeon-Hee Jo, Seung-Hee Hong, Sun-Min Hwang, Won-Jong Hwang, Songse Yi, MyeongKoo Kim, Naery Yu
  • Patent number: 10269627
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-Yi Ruan
  • Patent number: 10247700
    Abstract: A technique relates to manufacturing a nanogap. An oxide layer is disposed on top of a substrate. A release layer is disposed in a pattern on top of the oxide layer. A patterned trench is etched into the oxide layer using the pattern of the release layer. A metal layer is disposed on the release layer and in the patterned trench. A polish removes the release layer, thereby removing both the release layer and a portion of the metal layer having been disposed on top of the release layer, such that the metal layer remaining includes a first metal part and a second metal part connected by a metal nanowire. The metal layer remaining is coplanar with the oxide layer. A nanochannel is formed in the oxide layer in a region of the metal nanowire. The nanogap is formed in the metal nanowire separating the first and second metal parts.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: April 2, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, BIONANO GENOMICS, INC.
    Inventors: Huan Hu, Michael F. Lofaro, Joshua T. Smith, Benjamin H. Wunsch, Daniel J. Solis
  • Patent number: 10199343
    Abstract: An UBM electrode structure body for a radiation detector and a radiation detector arranged with the UBM electrode structure body are provided for suppressing peeling and having high electrode adhesion. In addition, a manufacturing method of an UBM electrode structure body for a radiation detector and a manufacturing method of a radiation detector using the UBM electrode structure body are provided in which peeling does not occur during UBM structure formation, a solder bonding process or bonding of a signal line to a Pt layer. The UBM electrode structure body for a radiation detector of the present invention is arranged with a CdTe substrate or CdZnTe substrate and a Pt electrode layer arranged on the CdTe substrate or CdZnTe substrate, adhesion of the Pt electrode layer with respect to the CdTe substrate or the CdZnTe substrate being 0.5 N/cm or more.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: February 5, 2019
    Assignee: JX NIPPON MINING & METALS CORPORATION
    Inventors: Makoto Mikami, Kouji Murakami, Akira Noda
  • Patent number: 10109790
    Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a substrate; forming an MRAM structure over the substrate; forming a first dielectric layer over the MRAM structure; forming a stop layer over the first dielectric layer; forming a second dielectric layer over the stop layer; and removing the second dielectric layer, the stop layer and at least a portion of the first dielectric layer through a planarization operation without exposing a top electrode of the MRAM structure. Associated methods are also disclosed.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Jiunyu Tsai, Hung Cho Wang, Tsun Chung Tu
  • Patent number: 10056366
    Abstract: Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10049983
    Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cha-Hsin Chao, Chih-Hao Chen, Hsin-Yi Tsai
  • Patent number: 10043707
    Abstract: A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: August 7, 2018
    Assignee: Qorvo US, Inc.
    Inventors: John August Orlowski, David Jandzinski
  • Patent number: 9997518
    Abstract: In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate; wherein forming the nFET transistor comprises first depositing several first layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several first layers; wherein forming the pFET transistor comprises first depositing several second layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several second layers.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Keith Kwong Hon Wong
  • Patent number: 9984922
    Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 29, 2018
    Assignee: Intel Corporation
    Inventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon
  • Patent number: 9960161
    Abstract: In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate; wherein forming the nFET transistor comprises first depositing several first layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several first layers; wherein forming the pFET transistor comprises first depositing several second layers in and along the inner sidewalls of a trench on the substrate, then depositing a conductive metal comprising cobalt on the several second layers.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: May 1, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Keith Kwong Hon Wong
  • Patent number: 9954262
    Abstract: An air secondary battery has a cathode to which an oxygen-containing gas is supplied, an anode containing an active metal material, and an electrolyte interposed between the cathode and the anode. In a discharge process, metal ions are generated from the active metal material, transferred through the electrolyte, and then reacted and bonded with oxygen molecules in the oxygen-containing gas on the cathode. Thus, the oxygen is reduced to generate a metal oxide. The cathode has a trap portion for confining the metal oxide. For example, the cathode has a first cathode layer and a second cathode layer having different average pore diameters. The first cathode layer located adjacent to the electrolyte and having a smaller average pore diameter acts as the trap portion.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: April 24, 2018
    Assignees: HONDA MOTOR CO., LTD., MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Tetsuya Koido, Akihiro Kushima, Yoshiya Fujiwara, Ju Li
  • Patent number: 9888585
    Abstract: Adhesion of an underlying diffusion barrier metal film and an electroless copper plating film with respect to an insulating film can be improved. A method for manufacturing a wiring structure includes a process of forming the underlying diffusion barrier metal film 5, including a base metal with respect to copper, on the insulating film 1; and a process of forming the electroless copper plating film 6 on the underlying diffusion barrier metal film 5 by performing an electroless copper displacement plating process with a copper displacement plating solution. The copper displacement plating solution is an acidic copper displacement plating solution of pH1 to pH4, in which copper ions are contained but a reducing agent for reducing the copper ions is not contained.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: February 6, 2018
    Assignees: TOKYO ELECTRON LIMITED, A SCHOOL CORPORATION KANSAI UNIVERSITY
    Inventors: Shoso Shinguhara, Kohei Ota, Mitsuaki Iwashita, Nobutaka Mizutani
  • Patent number: 9853110
    Abstract: One illustrative method disclosed includes, among other things, forming a gate contact opening in a layer of insulating material, performing at least one etching process through the gate contact opening to remove a gate cap layer and to expose the gate structure, selectively growing a metal material that is conductively coupled to an upper surface of the gate structure such that the grown metal material contacts all of the sidewalls of the gate contact opening and an air space is formed between a bottom of the grown metal material and a conductive source/drain structure, and forming one or more conductive materials in the gate contact opening above the grown metal material.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Ruilong Xie, Sean X. Lin
  • Patent number: 9806018
    Abstract: Semiconductor devices include a patterned dielectric layer overlaying a semiconductor substrate; a metal layer comprising copper disposed in the patterned dielectric layer; and a barrier layer formed at an interface between the dielectric layer and the metal layer, wherein the barrier layer is AlOxNy. The patterned dielectric may define a trench and via interconnect structure or first and second trenches for a capacitor structure. Also disclosed are processes for forming the semiconductor device, which includes subjecting the dielectric surfaces to a nitridization process to form a nitrogen enriched surface. Aluminum metal is then conformally deposited onto the nitrogen enriched surfaces to form AlOxNy at the aluminum metal/dielectric interface. The patterned substrate is then metallized with copper and annealed. Upon annealing, a copper aluminum alloy is formed at the copper metal/aluminum interface.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: October 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Wei Wang, Chih-Chao Yang
  • Patent number: 9804122
    Abstract: A technique relates to manufacturing a nanogap. An oxide layer is disposed on top of a substrate. A release layer is disposed in a pattern on top of the oxide layer. A patterned trench is etched into the oxide layer using the pattern of the release layer. A metal layer is disposed on the release layer and in the patterned trench. A polish removes the release layer, thereby removing both the release layer and a portion of the metal layer having been disposed on top of the release layer, such that the metal layer remaining includes a first metal part and a second metal part connected by a metal nanowire. The metal layer remaining is coplanar with the oxide layer. A nanochannel is formed in the oxide layer in a region of the metal nanowire. The nanogap is formed in the metal nanowire separating the first and second metal parts.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 31, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, BIONANO GENOMICS, INC.
    Inventors: Huan Hu, Michael F. Lofaro, Joshua T. Smith, Daniel J. Solis, Benjamin H. Wunsch
  • Patent number: 9779494
    Abstract: A dispensing system for depositing material on an electronic substrate includes a frame, a dispensing unit gantry movably coupled to the frame, a dispensing unit coupled to the dispensing unit gantry, a vision system gantry coupled to the frame, and a vision system coupled to the vision system gantry. A controller is configured to manipulate the vision system with the vision gantry system to move to the position defined by a feature, to acquire an image of at least a portion of a feature, to search for an edge of interest along a center of the image, and to return a value indicating an offset of zero (0), which is interpreted as the location that is exactly as expected, and an offset that reflects where the edge of interest intersected that axis location.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: October 3, 2017
    Assignee: Illinois Tool Works Inc.
    Inventor: Jonathan Joel Bloom
  • Patent number: 9744595
    Abstract: A method for producing coated copper particles having a surface coated with an aliphatic carboxylic acid, wherein the method comprises obtaining a reaction mixture containing copper formate, an amino alcohol, an aliphatic carboxylic acid having an aliphatic group having 5 or more carbon atoms, and a solvent, and subjecting a complex compound formed in the reaction mixture to thermal decomposition treatment to form metal copper, wherein a ?SP value, which is a difference in SP value between the amino alcohol and the solvent, is 4.2 or more.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 29, 2017
    Assignee: KYORITSU CHEMICAL & CO., LTD.
    Inventors: Kunihiro Fukumoto, Yu Oyama
  • Patent number: 9735216
    Abstract: An organic light emitting display (OLED) device is disclosed. The OLED device includes a substrate configured to include a sub-pixel defined into an emission region and a driving region. A first bank pattern configured to define the emission region of the sub-pixel is formed on the substrate. A second bank pattern configured to include an opening, which exposes the emission region and a part of the driving region, is formed on a part of an upper surface of the first bank pattern. An organic emission layer is formed in the opening. As such, the occupied area of the organic emission layer becomes wider. Therefore, the thickness deviation of the organic emission layer is prevented or minimized.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: August 15, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Geum Young Lee, Ki Soub Yang, Soo Yong Lee, Dae Jung Choi
  • Patent number: 9657404
    Abstract: A method of forming a metallic pattern on a polymer substrate is provided. A mixture layer is formed on a polymer substrate surface. The mixture layer includes an active carrier medium and nanoparticles dispersed in the active carrier medium. A laser process is performed to treat a portion of the mixture layer to form a conductive pattern on the surface of the polymer substrate. A cleaning process is performed to remove an untreated portion of the mixture layer to expose the surface of the polymer substrate, while the conductive pattern is remained on the surface of the polymer substrate. Then, the conductive pattern on the polymer substrate is subjected to an electroplating process to form the metallic pattern over the conductive pattern on the polymer substrate.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 23, 2017
    Assignee: Wistron NeWeb Corp.
    Inventors: Babak Radi, Shih-Hong Chen, Yu-Fu Kuo, Tzu-Wen Chuang
  • Patent number: 9609747
    Abstract: A wiring board includes: an insulating substrate; and a wiring layer including a first metal layer disposed on the insulating substrate and a second metal layer disposed so as to cover a surface of the first metal layer, the surface not being in contact with the insulating substrate, wherein the thickness of the second metal layer is 1/10 of the total thickness of the wiring layer, the wiring layer contains a migration inhibitor, and the mass Y of the migration inhibitor contained in the second metal layer is greater than the mass X of the migration inhibitor contained in the first metal layer.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: March 28, 2017
    Assignee: FUJIFILM CORPORATION
    Inventors: Yasuaki Matsushita, Tokihiko Matsumura
  • Patent number: 9580297
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a dielectric layer; forming an aluminum layer on the dielectric layer; forming a platinum layer on the aluminum layer; performing a first etching process to remove part of the platinum layer and part of the aluminum layer for forming a patterned platinum layer; and performing a second etching process to remove part of the aluminum layer exposed by the patterned platinum layer and part of the dielectric layer.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: February 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yi Lu, Jeng-Ho Wang
  • Patent number: 9581896
    Abstract: There is provided a pellicle 1 for lithography having a frame 12, a film 11 and an agglutinant layer 13 (an adhesive to bond the pellicle on a photomask), in which the agglutinant layer 13 is doped with a luminescence material so as to facilitate the inspection of the quality of the adhesion between the agglutinant layer 13 and the photomask; preferably the luminescence material is a kind that glows in response to UV irradiation, and a preferable dosage of the luminescence material is no less than 0.01 mass % but less than 1.0 mass %.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: February 28, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Jun Horikoshi
  • Patent number: 9523153
    Abstract: A pre-treatment method for plating can form a plating layer having sufficient adhesivity on an inner surface of a recess and on a surface of a substrate at an outside of the recess even when the recess has a high aspect ratio. The pre-treatment method for plating includes a preparation process of preparing the substrate having the recess; a first coupling layer forming process of forming a first coupling layer 21a at least on the inner surface of the recess of the substrate by using a first coupling agent; and a second coupling layer forming process of forming a second coupling layer 21b at least on the surface of the substrate at the outside of the recess by using a second coupling agent after the first coupling layer forming process.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: December 20, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takashi Tanaka, Yuichiro Inatomi, Kazutoshi Iwai, Mitsuaki Iwashita
  • Patent number: 9520422
    Abstract: An oxide thin film transistor and a manufacturing method thereof, an array substrate and a display device are provided. The method comprises: forming a gate electrode (1), a gate insulating layer (4) and an oxide semiconductor thin film (10) sequentially on a substrate; forming a first photoresist (11a) above an active layer region of the oxide semiconductor thin film (10), such that a thickness of the first photoresist above a channel region is greater than a thickness of the first photoresist above a non-channel region; reserving the first photoresist (11a) above the channel region; forming a source-drain metal thin film and a second photoresist (11b) sequentially on a pattern of an active layer, removing a portion of the source-drain metal thin film and a portion of the second photoresist (11b), such that an edge of the first photoresist (11a) above the channel region is covered with the source-drain metal thin film; and obtaining patterns of a source electrode and a drain electrode.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: December 13, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hyun Sic Choi, Yun Sik Im
  • Patent number: 9514986
    Abstract: A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Yen-Hung Chen, Yin-Hua Chen, Ebin Liao, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 9506149
    Abstract: A process for depositing a metal includes disposing a liquid deposition composition on a substrate, the liquid deposition composition including a metal cation; a reducing anion; and a solvent; evaporating the solvent; increasing a concentration of the reducing anion increases in the liquid deposition composition due to evaporating the solvent; performing an oxidation-reduction reaction between the metal cation and the reducing anion in response to increasing the concentration of the reducing anion when the reducing anion is present at a critical concentration; and forming a metal from the metal cation to deposit the metal on the substrate.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: November 29, 2016
    Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventor: Owen J. Hildreth
  • Patent number: 9462699
    Abstract: A method of forming a metallic pattern on a polymer substrate is provided. A mixture layer is formed on a polymer substrate surface. The mixture layer includes an active carrier medium and nanoparticles dispersed in the active carrier medium. A laser process is performed to treat a portion of the mixture layer to form active seed residues on the surface of the polymer substrate. A cleaning process is performed to remove an untreated portion of the mixture layer to expose the surface of the polymer substrate, while the active seed residues are remained on the surface of the polymer substrate. Then, the active seed residues on the polymer substrate are subjected to an electroless plating process to form the metallic pattern over the active seed residues on the polymer substrate.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: October 4, 2016
    Assignee: Wistron NeWeb Corp.
    Inventors: Babak Radi, Yu-Fu Kuo
  • Patent number: 9401284
    Abstract: A semiconductor device includes: a substrate comprised by gallium arsenide; an active layer provided on the substrate; a first nickel-plated layer provided on a lower face of the substrate facing the active layer; a copper-plated layer provided on a lower face of the first nickel-plated layer; and a second nickel-plated layer provided on a lower face of the copper-plated layer.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: July 26, 2016
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Hiroshi Kawakubo
  • Patent number: 9396995
    Abstract: A method of forming a metalized contact in MOL is provided. Embodiments include forming a TT through an ILD down to a S/D region; forming a SiOC, SiCN, or SiON layer on side surfaces of the TT; performing a GCIB vertical etching at a 0° angle; implanting Si into the TT by an angled PAI; removing a portion of the TT by Ar sputtering and a remote plasma assisted dry etch process; forming NiSi on the S/D region at the bottom of the TT; and filling the TT with contact metal over the NiSi.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: July 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj K. Patil, Min-hwa Chi, Garo Derderian, Wen-Pin Peng
  • Patent number: 9385036
    Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: July 5, 2016
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Belgacem Haba, Craig Mitchell
  • Patent number: 9362164
    Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tien-I Bao
  • Patent number: 9287183
    Abstract: A method for detecting contamination on a patterned substrate includes: performing a via etch operation on a substrate, wherein the via etch operation is configured to define a via feature on the substrate and expose an etch-stop layer at a bottom of the via feature; performing an etch-stop removal operation on the substrate, wherein the etch-stop removal operation is configured for removing the etch-stop layer at the bottom of the via feature to expose a metallic feature underlying the etch-stop layer; applying an electroless deposition solution to the substrate, the applied electroless deposition solution configured for selectively depositing a metallic material over the exposed metallic feature and on metallic contaminants on exposed surfaces of the substrate, the metallic contaminants being generated from the metallic feature during the etch-stop removal operation; performing an inspection operation on the substrate to identify the metallic contaminants that have been deposited with the metallic material.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: March 15, 2016
    Assignee: Lam Research Corporation
    Inventors: Larry Zhao, Artur Kolics, Praveen Nalla
  • Patent number: 9263326
    Abstract: After a copper interconnection is formed above a substrate, a surface of the copper interconnection is activated by performing acid cleaning. Thereafter, the substrate is immersed in a BTA (Benzo triazole) aqueous solution to form a protection film covering the surface of the copper interconnection. At this time, Cu—N—R bonds (R is an organic group) are formed in grain boundary portions in the surface of the copper interconnection. Thereafter, the protection film is removed by performing alkaline cleaning. The Cu—N—R bonds remain in the grain boundary portions in the surface of the copper interconnection even after the protection film is removed. Subsequently, the surface of the copper interconnection is subjected to an activation process, and a barrier layer is formed thereafter by electroless-plating the surface of the copper interconnection with NiP or CoWP.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: February 16, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi
  • Patent number: 8980747
    Abstract: Pre-migration of metal ions is achieved in a controlled manner to form a migrated metalover which an inhibitor is applied to prevent further migration. In a semiconductor circuit, pre-migration of metal ions is achieved by exposing a joined metal system to water, oxygen and an electrical field in a controlled manner. Conductors, joined to electrically isolating materials, are exposed to electrical fields in such a manner as to form one or more anodes to corresponding cathodes, thus liberating metal ions. The metal ions are then allowed to migrate in a controlled manner from the anode toward the cathode to form a pre-migrated metal. Finally, an inhibitor is applied on top of the pre-migrated metal to prevent further migration.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: March 17, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Craig J. Rotay, John C. Pritiskutch
  • Patent number: 8956973
    Abstract: According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Troy L. Graves-Abe
  • Patent number: 8906795
    Abstract: A semiconductor device manufacturing method allows stably forming a plating layer at low cost on one main surface side of a substrate, while preventing unintended plating layer deposition on the other main surface side. Emitter and collector electrodes are respectively formed on the front and back surfaces of a semiconductor substrate. A first film is attached to the back surface. A notch portion of the substrate is filled with a resin member. A second film is attached to an outer peripheral portion of the substrate, straddling the substrate from the front surface to the back surface. The first and second films push out air remaining between the first and second films and the substrate. An electroless plating process is carried out while the first and second films are attached to the substrate, thereby sequentially forming a nickel plating layer and a gold plating layer on the front surface side.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: December 9, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shoji Sakaguchi, Idayu Sofya
  • Patent number: 8853677
    Abstract: Metal ink compositions, methods of forming such compositions, and methods of forming conductive layers are disclosed. The ink composition includes a bulk metal, a transition metal source, and an organic solvent. The transition metal source may be a transition metal capable of forming a silicide, in an amount providing from 0.01 to 50 at. % of the transition metal relative to the bulk metal. Conductive structures may be made using such ink compositions by forming a silicon-containing layer on a substrate, printing a metal ink composition on the silicon-containing layer, and curing the composition. The metal inks of the present invention have high conductivity and form low resistivity contacts with silicon, and reduce the number of inks and printing steps needed to fabricate integrated circuits.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 7, 2014
    Assignee: Thin Film Electronics ASA
    Inventors: Joerg Rockenberger, Yu Chen, Fabio Zürcher, Scott Haubrich
  • Patent number: 8790953
    Abstract: The surface of silicon is textured to create black silicon on a nano-micro scale by electrochemical reduction of a silica layer on silicon in molten salts. The silica layer can be a coating, or a layer caused by the oxidation of the silicon.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: July 29, 2014
    Inventors: Derek John Fray, Eimutis Juzeliunas
  • Patent number: 8673762
    Abstract: A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventors: Toshiya Akamatsu, Nobuhiro Imaizumi, Seiki Sakuyama, Keisuke Uenishi, Tetsuhiro Nakanishi
  • Patent number: 8664037
    Abstract: Disclosed are a method for forming a metal oxide pattern and a method of manufacturing a thin film transistor using the patterned metal oxide. The method for forming a metal oxide pattern includes: preparing an ink composition including at least one metal oxide precursor or metal oxide nanoparticle, and a solvent; ejecting the ink composition on a substrate to form a pattern on the substrate; and photosintering the formed pattern. Herein, the metal oxide precursor is ionic.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: March 4, 2014
    Assignee: Korea Institute of Science and Technology
    Inventors: Yong-Won Song, Jae-Min Hong, Jung Ah Lim, Hak-Sung Kim, Seong-Ji Kwon
  • Patent number: 8557703
    Abstract: According to an embodiment of the present disclosure, a method of pre-migrating metal ions is disclosed. A metal in a semiconductor configuration is exposed to water and oxygen to yield metal ions. The metal couples a conductor to another material. The metal and the conductor are exposed to an electrical field in such a manner that one or both of the metal and the conductor becomes an anode to a corresponding cathode. The metal ions are then allowed to migrate from the anode to the cathode to form a migrated metal. Finally, a migration inhibitor is applied on top of the migrated metal to prevent further migration.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: October 15, 2013
    Assignee: STMicroelectronics, Inc.
    Inventors: Craig J. Rotay, John C. Pritiskutch
  • Publication number: 20130260556
    Abstract: According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Troy L. Graves-Abe
  • Publication number: 20130244423
    Abstract: A method for providing copper filled features is provided. Features are provided in a layer on a substrate. A simultaneous electroless copper plating and anneal is provided. The electroless copper plating is chemical-mechanical polished, where there is no annealing before the chemical-mechanical polishing and after the simultaneous electroless copper plating and anneal.
    Type: Application
    Filed: March 19, 2012
    Publication date: September 19, 2013
    Applicant: LAM RESEARCH CORPORATION
    Inventor: Artur KOLICS
  • Patent number: 8518826
    Abstract: One aspect of the present invention is a method of processing a substrate. In one embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electroless deposition solution and electrolessly depositing a metal matrix and co-depositing the metal particles. In another embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electrochemical plating solution and electrochemically plating a metal matrix and co-depositing the metal particles. Another aspect of the present invention is a mixture for the formation of an electrical conductor on or in a substrate. Another aspect of the present invention is an electronic device.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: August 27, 2013
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, Fritz Redeker
  • Patent number: 8435887
    Abstract: Disclosed is a method which includes forming a copper interconnect within a trench or via in a substrate. Forming the copper interconnect includes forming a ruthenium-containing seed layer on a wall of the trench or via; forming a cobalt sacrificial layer on the ruthenium-containing layer before the ruthenium-containing seed layer being exposed to an environment that is oxidizing with respect to the seed layer; and contacting the cobalt sacrificial layer with a copper plating solution, the copper plating solution dissolving the cobalt sacrificial layer and plating out copper on the unoxidized ruthenium-containing seed layer. Alternatively, the ruthenium-containing seed layer may be replaced with platinum, tungsten nitride, titanium nitride or titanium or iridium. Further alternatively, the cobalt sacrificial layer may be replaced by tin, cadmium, copper or manganese.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: May 7, 2013
    Assignees: International Business Machines Corporation, Kabushiki Kaisha Toshiba
    Inventors: James J. Kelly, Takeshi Nogami, Kazumichi Tsumura
  • Patent number: 8431484
    Abstract: A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: April 30, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joseph T. Lindgren
  • Publication number: 20130075906
    Abstract: A semiconductor device includes: a foundation layer that is provided on a substrate and is electrically conductive; a nickel layer provided on the foundation layer; and a solder provided on the nickel layer, the nickel layer having a first region on a side of the foundation layer and a second region on a side of the solder, the second region being harder than the first region.
    Type: Application
    Filed: September 28, 2012
    Publication date: March 28, 2013
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Sumitomo Electric Device Innovations, Inc.
  • Publication number: 20130032900
    Abstract: Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.
    Type: Application
    Filed: August 1, 2011
    Publication date: February 7, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hao HOU, Wei-Yang LEE, Xiong-Fei YU, Kuang-Yuan HSU
  • Publication number: 20120309190
    Abstract: Disclosed is a method which includes forming a copper interconnect within a trench or via in a substrate. Forming the copper interconnect includes forming a ruthenium-containing seed layer on a wall of the trench or via; forming a cobalt sacrificial layer on the ruthenium-containing layer before the ruthenium-containing seed layer being exposed to an environment that is oxidizing with respect to the seed layer; and contacting the cobalt sacrificial layer with a copper plating solution, the copper plating solution dissolving the cobalt sacrificial layer and plating out copper on the unoxidized ruthenium-containing seed layer. Alternatively, the ruthenium-containing seed layer may be replaced with platinum, tungsten nitride, titanium nitride or titanium or iridium. Further alternatively, the cobalt sacrificial layer may be replaced by tin, cadmium, copper or manganese.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 6, 2012
    Applicants: KABUSHIKI KAISHA TOSHIBA, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Kelly, Takeshi Nogami, Kazumichi Tsumura