Top plate for semiconductor manufacturaing equipment
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The broken lines shown are included for the purpose of illustrating portions of the design which form no part of the claimed design. The dot-dash lines indicate the boundary between the claimed portion and forms no part of the claimed design.
Claims
The ornamental design for a top plate for semiconductor manufacturaing equipment, as shown and described.
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Type: Grant
Filed: Jun 10, 2021
Date of Patent: Mar 5, 2024
Assignee: NuFlare Technology, Inc. (Kanagawa)
Inventors: Takuto Umetsu (Kanagawa), Masayoshi Yajima (Kanagawa), Kunihiko Suzuki (Kanagawa)
Primary Examiner: Shawn T Gingrich
Assistant Examiner: Caleb M Baker
Application Number: 29/794,124