Upper chamber for a plasma processing device
Description
The broken line box shown in
Claims
The ornamental design for an upper chamber for a plasma processing device as shown and described.
Referenced Cited
U.S. Patent Documents
| 5820723 | October 13, 1998 | Benjamin |
| 6408786 | June 25, 2002 | Kennedy |
| D491963 | June 22, 2004 | Doba |
| D802790 | November 14, 2017 | Tauchi |
| D804436 | December 5, 2017 | Tauchi |
| D812578 | March 13, 2018 | Uemura |
| 20130105085 | May 2, 2013 | Yousif |
| 20150170885 | June 18, 2015 | Ouye |
Patent History
Patent number: D1094319
Type: Grant
Filed: Jul 22, 2022
Date of Patent: Sep 23, 2025
Assignee: Hitachi High-Tech Corporation (Tokyo)
Inventors: Koji Nagai (Tokyo), Tadayoshi Kawaguchi (Tokyo), Kazuyuki Ikenaga (Tokyo), Kohei Sato (Tokyo)
Primary Examiner: Justin M Jonaitis
Assistant Examiner: Bria′ L Simmons-Holloway
Application Number: 29/847,251
Type: Grant
Filed: Jul 22, 2022
Date of Patent: Sep 23, 2025
Assignee: Hitachi High-Tech Corporation (Tokyo)
Inventors: Koji Nagai (Tokyo), Tadayoshi Kawaguchi (Tokyo), Kazuyuki Ikenaga (Tokyo), Kohei Sato (Tokyo)
Primary Examiner: Justin M Jonaitis
Assistant Examiner: Bria′ L Simmons-Holloway
Application Number: 29/847,251
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)