Temporary package for semiconductor dice

- Micron Technology, Inc.
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Description

FIG. 1 is an enlarged top perspective view of a temporary package for semiconductor dice showing my new design;

FIG. 2 is a left side elevational view thereof;

FIG. 3 is a right side elevational view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a front side elevational view thereof;

FIG. 6 is a bottom plan view thereof; and,

FIG. 7 is a rear side elevation view thereof.

Referenced Cited
U.S. Patent Documents
D317592 June 18, 1991 Yoshizawa
D359028 June 6, 1995 Siegel et al.
5053853 October 1, 1991 Haj-Ali-Ahmadi et al.
5155067 October 13, 1992 Wood et al.
5173451 December 22, 1992 Kinsman et al.
5206536 April 27, 1993 Lim
5302891 April 12, 1994 Wood et al.
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5440240 August 8, 1995 Wood et al.
5442232 August 15, 1995 Goto et al.
5451165 September 19, 1995 Cearley-Cabbiness et al.
5455452 October 3, 1995 Kiyono
5471088 November 28, 1995 Song
5495179 February 27, 1996 Wood et al.
5517125 May 14, 1996 Posedel et al.
5519332 May 21, 1996 Wood et al.
5530376 June 25, 1996 Lim et al.
5541525 July 30, 1996 Wood et al.
5543725 August 6, 1996 Lim et al.
5581195 December 3, 1996 Lee et al.
Other references
  • 1994 Dram Data Book, Micron Semiconductor, Inc., pp. 7-7-7-13, Apr., 1994.
Patent History
Patent number: D394844
Type: Grant
Filed: Apr 25, 1997
Date of Patent: Jun 2, 1998
Assignee: Micron Technology, Inc. (Boise, ID)
Inventors: Warren M. Farnworth (Nampa, ID), Alan G. Wood (Boise, ID), David R. Hembree (Boise, ID), Salman Akram (Boise, ID)
Primary Examiner: M. H. Tung
Attorney: Stephen A. Gratton
Application Number: 0/70,050
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;