Semiconductor memory element

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Description

FIG. 1 is a top perspective view of a semiconductor memory element showing our new design;

FIG. 2 is a side elevation view thereof, the opposite side view being a mirror image of that shown;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof; and,

FIG. 5 is a front elevation view thereof, the rear elevation view being a mirror image of that shown.

Claims

The ornamental design for a semiconductor memory element, as shown and described.

Referenced Cited
U.S. Patent Documents
D260091 August 4, 1981 Mochizuki et al.
4458291 July 3, 1984 Yanagisawa et al.
D319629 September 3, 1991 Hasegawa et al.
5394009 February 28, 1995 Loo
D474472 May 13, 2003 Maekawa et al.
Foreign Patent Documents
D1136820 March 2002 JP
D1137203 March 2002 JP
Patent History
Patent number: D487430
Type: Grant
Filed: Nov 27, 2002
Date of Patent: Mar 9, 2004
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka)
Inventors: Nobuyoshi Asaka (Tokyo), Takashi Noda (Hyogo), Takao Ochi (Shiga-gun), Junichi Shinyashiki (Osaka)
Primary Examiner: Kay H. Chin
Attorney, Agent or Law Firm: Brinks Hofer Gilson & Lione
Application Number: 29/171,752
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182); Cartridge, Chip Or Card (D14/435)
International Classification: 1303;