Semiconductor wafer processing tape

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FIG. 1 is a perspective view showing our new design;

FIG. 2 is a top plan view;

FIG. 3 is a bottom plan view;

FIG. 4 is a left side view;

FIG. 5 is a front side view;

FIG. 6 is a right side view;

FIG. 7 is a cross sectional view at 77 of FIG. 1; and,

FIG. 8 is a cross sectional view at 88 of FIG. 1.


The ornamental design for a “semiconductor wafer processing tape,” as shown and described.

Referenced Cited
U.S. Patent Documents
6864295 March 8, 2005 Mitarai
D589473 March 31, 2009 Takamoto et al.
D598380 August 18, 2009 Kuriki
20070241436 October 18, 2007 Ookubo et al.
20100080989 April 1, 2010 Asai et al.
Foreign Patent Documents
D1267623 April 2006 JP
2007-2173 January 2007 JP
D1315406 November 2007 JP
D1315621 November 2007 JP
Patent History
Patent number: D621803
Type: Grant
Filed: Jul 16, 2008
Date of Patent: Aug 17, 2010
Assignee: The Furukawa Electric Co., Ltd. (Tokyo)
Inventors: Hiromitsu Maruyama (Tokyo), Shuzo Taguchi (Tokyo), Yasumasa Morishima (Tokyo), Shinichi Ishiwata (Tokyo)
Primary Examiner: Selina Sikder
Attorney: Knoble Yoshida & Dunleavy, LLC
Application Number: 29/321,418