Substrate for an electronic circuit
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Description
The broken line portion of the figure drawings is included to show portions of the article that form no part of the claimed design.
Claims
The ornamental design for a substrate for an electronic circuit, as shown and described.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
5303121 | April 12, 1994 | Thornberg |
D432096 | October 17, 2000 | Jeon |
6307754 | October 23, 2001 | Le |
6347394 | February 12, 2002 | Ochoa |
D459706 | July 2, 2002 | Ebihara et al. |
6765278 | July 20, 2004 | Parsons |
D637193 | May 3, 2011 | Andre |
D652041 | January 10, 2012 | Andre |
D655296 | March 6, 2012 | Andre et al. |
D673921 | January 8, 2013 | Ozawa |
D673922 | January 8, 2013 | Moriai |
D686215 | July 16, 2013 | Andre |
D716310 | October 28, 2014 | Andre |
D730304 | May 26, 2015 | Matsumoto |
D753073 | April 5, 2016 | Sponring |
D764424 | August 23, 2016 | Matsumoto |
D778851 | February 14, 2017 | Matsumoto |
D778852 | February 14, 2017 | Matsumoto |
20070274032 | November 29, 2007 | Ni |
20080137278 | June 12, 2008 | Chih |
20090279243 | November 12, 2009 | Amidi |
20100264520 | October 21, 2010 | Ogawa |
20110122481 | May 26, 2011 | Ide |
20130306991 | November 21, 2013 | Terai |
20150355686 | December 10, 2015 | Heyd |
20160172016 | June 16, 2016 | Matsumoto |
20160334992 | November 17, 2016 | Yashiro |
20170010639 | January 12, 2017 | Matsumoto |
1104233 | March 2001 | JP |
1152236 | September 2002 | JP |
1426166 | October 2011 | JP |
1436226 | March 2012 | JP |
1479369 | September 2013 | JP |
1479370 | September 2013 | JP |
Patent History
Patent number: D793973
Type: Grant
Filed: Jul 14, 2015
Date of Patent: Aug 8, 2017
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventors: Manabu Matsumoto (Yokohama), Yasumasa Toyoda (Yokohama)
Primary Examiner: Thomas Johannes
Assistant Examiner: Shawn T Gingrich
Application Number: 29/533,042
Type: Grant
Filed: Jul 14, 2015
Date of Patent: Aug 8, 2017
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventors: Manabu Matsumoto (Yokohama), Yasumasa Toyoda (Yokohama)
Primary Examiner: Thomas Johannes
Assistant Examiner: Shawn T Gingrich
Application Number: 29/533,042
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)