Method and a device for synchronizing a signal
A device synchronizes an internal signal with respect to a reference signal, each signal comprising pulses normally occurring at a rated frequency. The device uses a phase comparator to analyze the phase of the internal signal and the reference signal and produce one logic state if the phase of the internal signal is in advance of the phase of the reference signal and a second logic state otherwise. A programmable frequency divider divides an internal clock signal by a first number if the phase comparator signal produces the first logic state or by a second number if the phase comparator produces the second logic state. A multiplexer provides the programmable divider with either the first number or the second number depending on the logic state produced the phase comparator. The device also includes a storage element for sequentially storing a predetermined number of the latest logic states of the phase comparator. The device also includes circuitry for decrementing the first number when the latest stored logic states of the phase comparator have a single occurrence of the first logic state and for incrementing the second number when the latest stored logic states of the phase comparator have a single occurrence of the second state.
Claims
2. The method of claim 1, further including the step of storing a predetermined number of successive states of said phase comparison signal.
4. The method of claim 3, further including the step of preventing the value of said second.Iadd.variable.Iaddend.divisor from exceeding the value of said first.Iadd.variable.Iaddend.divisor by comparing the value of said first.Iadd.variable.Iaddend.divisor with the value of said second.Iadd.variable.Iaddend.divisor and disabling the decrementing of the value of said first.Iadd.variable.Iaddend.divisor and the incrementing of the value of said second.Iadd.variable.Iaddend.divisor when the value of said first.Iadd.variable.Iaddend.divisor equals the value of said second.Iadd.variable.Iaddend.divisor.
7. A method for synchronizing an internal signal with respect to a reference signal having a reference period, said internal signal having a long period or a short period between which said reference period is normally included, comprising the following steps:
- a) analyzing the duration of the reference period with respect to the durations of the long and short periods;
- b) when the reference period is closer to the long period than the short period, incrementing the short period;
- c) when the reference period is closer to the short period than the long period, decrementing the long period;
- d) when the reference period is higher than the long period, incrementing the long period; and
- e) when the reference period is lower than the short period, decrementing the short period.
9. A method according to claim 8,.Iadd.further.Iaddend.comprising the following steps:
- when the number of successive phases in advance is higher than a predetermined number, incrementing the long period; and
- when the number of successive phase lags is higher than the predetermined number, decrementing the short period.
10. A method according to claim 7,.Iadd.further.Iaddend.comprising the following steps:
- comparing the long and short periods; and
- inhibiting the decrementation of the long period and the incrementation of the short period when the difference between these periods is lower than a predetermined threshold.
11. A method according to claim 7,.Iadd.further.Iaddend.comprising the following steps:
- comparing the long period with a maximum period and inhibiting the incrementation of the long period when said periods are equal; and
- comparing the short period with a minimum period and inhibiting the decrementation of the short period when said periods are equal.
13. The device of claim 12, further including storage means for storing a predetermined number of successive states of said phase comparison signal.
15. The device of claim 14, further including means for preventing the value of said second.Iadd.variable.Iaddend.divisor from exceeding the value of said first.Iadd.variable.Iaddend.divisor by comparing the value of said first.Iadd.variable.Iaddend.divisor with the value of said second.Iadd.variable.Iaddend.divisor and disabling the portion of said control means for decrementing the value of said first.Iadd.variable.Iaddend.divisor and incrementing the value of said second.Iadd.variable.Iaddend.divisor when the value of said first.Iadd.variable.Iaddend.divisor equals the value of said second.Iadd.variable.Iaddend.divisor.
19. A device according to claim 18, further including:
- a third detection means setting said first counting means in up-counting position when said predetermined number of latest stored states of said phase comparison signal are all at said predetermined state; and
- a fourth detection means setting said second counting means to down-counting position when said predetermined number of latest stored states of said phase comparison signal are at said complementary state.
20. A device according to claim 19,.Iadd.further.Iaddend.comprising a first comparator for comparing the high and low binary numbers and setting said first and second counting means in a standby state when the high binary number is lower than or equal to the low.Iadd.binary.Iaddend.number.
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Type: Grant
Filed: Jun 7, 1996
Date of Patent: Feb 9, 1999
Assignee: SGS-Thomson Microelectronics S.A. (Gentilly)
Inventor: Jacques Meyer (Gentilly)
Primary Examiner: Stephen Chin
Assistant Examiner: Jeffrey W. Gluck
Attorneys: David V. Carlson, Bryan A. Seed and Berry LLP Santarelli
Application Number: 8/664,229
International Classification: H03D 324;
