Abstract: A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.

Abstract: According to one embodiment, a semiconductor memory device includes: a stack body having a step structure body with a plurality of wire line layers and a plurality of interlayer insulating layers alternately stacked being set as one step on a substrate; and memory cells arranged three-dimensionally in the stack body, in which the step structure body includes: a plurality of terrace portions configured with the interlayer insulating layers, the plurality of terrace portions having different heights; a plurality of step portions connecting the respective terrace portions in a height direction; insulating layers covering the step portions; and a lead wire line leading out a lowermost wire line layer of a first step onto the terrace portion of a second step being a lower step of the first step.

Abstract: According to one embodiment, a semiconductor device includes: a stack body including an insulator, a first conductor and a second conductor stacked stepwise by interposing the insulator and electrically disconnected from each other; and a first contact plug which reaches the first conductor from a region above the stack body. The first conductor includes a first portion positioned below the insulator, a second portion positioned above the insulator, and a third portion that electrically connects the first portion of the first conductor and the second portion of the first conductor. The third portion of the first conductor is provided in an opening formed on the insulator.

Abstract: A voltage generation circuit is provided to suppress the required layout of the voltage generation circuit and stabilize the output voltage thereof. [Solution] A voltage generation circuit 100A according to the present invention includes a charge pump circuit 20, a resistor voltage-division circuit 120, a comparator 34 having a voltage Vm output from the resistor voltage-division circuit 120 and a reference voltage, and a control circuit 36 controlling the operation of the charge pump circuit 20 based on the comparison result of the comparator 34. The resistor voltage-division circuit 120 includes resistors R1˜R4 connected in series between an output node NOUT and a ground and generates the voltage Vm at a voltage-division node NR in response to an output voltage VOUT. The resistor voltage-division circuit 120 further includes a parasitic capacitor Cp to capacitively couple the resistors R1, R2, R3 and R4 to the output node NOUT.

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

Abstract: Embodiments of the present invention provide methods for forming an interconnection structure in semiconductor devices without breaking vacuum with minimum oxidation/atmosphere exposure. In one embodiment, a method for forming an interconnection structure for semiconductor devices includes supplying a barrier layer etching gas mixture into a first processing chamber having a substrate disposed therein to etch portions of a barrier layer exposed by a patterned metal layer until the underlying substrate is exposed, the first processing chamber disposed in a processing system, and forming a liner layer on the substrate covering the etched barrier layer in a second processing chamber disposed in the processing system.

Abstract: A semiconductor device includes a copper interconnect provided in a trench in an insulation film, a metal film provided on the insulation film along a boundary between the insulation film and the copper interconnect, a barrier metal provided between an inner wall of the trench and the copper interconnect and extending over the metal layer, a first metal cap to cover the copper interconnect and the barrier metal located over the metal film, and a second metal cap to continuously cover the first metal cap, the barrier metal and the metal film.

Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.

Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.

Abstract: To provide a power storage device with improved cycle characteristics and a method for manufacturing the power storage device, a power storage device is provided with a conductive layer in contact with a surface of an active material layer including a silicon layer after an oxide film, such as a natural oxide film, which is formed on the surface of the active material layer is removed. The conductive layer is thus provided in contact with the surface of the active material layer including a silicon layer, whereby the conductivity of the electrode surface of the power storage device is improved; therefore, cycle characteristics of the power storage device can be improved.

Abstract: A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.

Abstract: Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.

Abstract: The present invention relates to a through-wafer via device (10) comprising a wafer (12) made of a wafer material and having a first wafer surface (12a) and a second wafer surface (12b) opposing the first wafer surface (12a). The through-wafer via device (10) further comprises a plurality of side by side first trenches (14) provided with a conductive material and extending from the first wafer surface (12a) into the wafer (12) such that a plurality of spacers (16) of the wafer material are formed between the first trenches (14). The through-wafer via device (10) further comprises a second trench (18) provided with the conductive material and extending from the second wafer surface (12b) into the wafer (12), the second trench (18) being connected to the first trenches (14).

Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

Abstract: The present teachings provides a semiconductor device which has a semiconductor substrate, and a lower electrode including a first layer in contact with a lower surface of the semiconductor substrate, a second layer in contact with a lower surface of the first layer, and a third layer stacked at a position farther from the semiconductor substrate than the second layer, wherein the first layer is an aluminum layer containing silicon, the second layer is a layer including silicon as a primary component, and the third layer is a solder joint layer.

Abstract: A semiconductor device, including: a semiconductor layer having an active region; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric and covering the active region when viewed from a top side; and a forbidden region provided in the semiconductor layer in a specific range positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad. A connection section at which the first conductive layer and the second conductive layer are connected is not provided in the forbidden region.

Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Abstract: A storage device includes a memory and a wireless transmitter, both contained in a disaster-proof enclosure. The memory is configured to receive and store data, and the wireless transmitter is coupled to read and transmit the data from the memory. The disaster-proof enclosure is surrounded by a thermally-insulating layer, and is configured to protect the memory and the transmitter from environmental conditions caused by a disaster event, such that the memory and the wireless transmitter remain functional during and after the disaster event and the transmitter is able to transmit at least a portion of the data to a receiver from within the disaster-proof enclosure after the disaster event.

Abstract: Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. Here, the lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel. Thus, the use of the multi-layered transparent conductive layer can ensure transparency and conductivity, overcome a problem of contact resistance between the source and drain electrodes and a semiconductor, and improve processibility by patterning the multi-layered transparent conductive layer all at once, while deposition is performed layer by layer.

Abstract: An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.

Abstract: A semiconductor device, including: a semiconductor layer having an active region; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric and covering the active region when viewed from a top side; and a forbidden region provided in the semiconductor layer in a specific range positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad. A connection section at which the first conductive layer and the second conductive layer are connected is not provided in the forbidden region.

Abstract: A flexible film is provided. The flexible film includes a dielectric film; and a metal layer disposed on the dielectric film, wherein the ratio of the thickness of the metal layer to the thickness of the dielectric film is about 1:3 to 1:10. Therefore, it is possible to improve the peel strength, dimension stability, and tensile strength of a flexible film by limiting the ratio of the thicknesses of a dielectric film and a metal layer of the flexible film.

Abstract: An inclined surface having an inclination angle ? is formed in an edge portion which forms an opening portion of an inter-layer insulating film, thereby reducing a stress by the inclined surface.

Abstract: The present invention provides a solder resist material, which can suppress the warpage of a semiconductor package upon exposure to heat or impact even when used in a thin wiring board and meets a demand for size reduction in electronic devices and a higher level of integration, and a wiring board comprising the solder resist material and a semiconductor package. The solder resist material of the present invention can effectively suppress the warpage of a semiconductor package through a fiber base material-containing layer interposed between resin layers. The fiber base material-containing layer is preferably unevenly distributed in the thickness direction of the solder resist material.

Abstract: In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.

Abstract: A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, forming a first liner nitride layer on an exposed surface of the trench, forming a first high density plasma (HDP) oxide layer such that the first HDP oxide layer partially fills the trench to cover a bottom surface and a side surface of the trench and an upper surface of the first liner nitride layer, etching overhangs generated during the forming of the first HDP oxide layer by introducing a hydrofluoric acid (HF) solution into the semiconductor substrate, forming a second liner nitride layer over the first HDP oxide layer, removing the second liner nitride layer formed on the first HDP oxide layer while forming a second HDP oxide layer to fill the trench, and subjecting the second HDP oxide layer to planarization, so as to form a trench isolation layer.

Abstract: A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer, forming an etch stop layer over the second insulation layer and the second contact layers, forming a third insulation layer over the etch stop layer, etching the third insulation layer and the etch stop layer to form first contact holes exposing the second contact layers, etching the exposed second contact layers to form second contact holes exposing the first contact holes, and forming bottom electrodes over the inner surface of the second contact holes.

Abstract: A layout structure is provided with a conducting line extending in a conducting line direction, the conducting line being arranged within a substrate area, a fill element being arranged within the substrate area at a predetermined distance from the conducting line, the fill element having a fill element axis extending perpendicularly to a side of the fill element in a fill element direction, an angle between the conducting line direction and the fill element direction being greater than 0° and smaller than 90°.

Abstract: Defect density of a polysilicon metal silicide wiring is reduced by employing a block of undoped polysilicon metal silicide in locations in which dopants are not needed in the underlying polysilicon. Furthermore, detection of presence of defects in the polysilicon metal wiring that adversely impacts device performance at high frequency is facilitated by employing a block of undoped polysilicon metal silicide since defects in undoped polysilicon metal silicide is more readily detectable than defects in doped polysilicon metal silicide. Locations wherein undoped polysilicon metal silicide wiring is employed include areas over shallow trench isolation.

Abstract: Apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.

Abstract: The semiconductor device, in which a flaking of a layer or an element is prevented, is provided. A bonding pad section 13 of a semiconductor device 1 includes a polysilicon film 131, a barrier metal film 133 provided on the polysilicon film 131 and a metallic electrode 134 provided on the barrier metal film 133. The surface roughness of the surface of the polysilicon film 131 in the side of the barrier metal film 133 is equal to or larger than 3 nm. Further, the polysilicon film 131 contains substantially no phosphorus.

Abstract: A polycrystalline silicon plate has grain boundary lines on a surface thereof, and at least one of the grain boundary lines is a quasi-linear grain boundary line (1). The silicon plate is used to produce a solar cell. The silicon plate is formed using a base substrate having an irregular surface provided with dotted or linear protrusions, which makes it possible to control the grain boundary lines. As such, an inexpensive and high-quality silicon plate can be provided. Further, by employing this silicon plate to produce a solar cell, an inexpensive and high-quality solar cell can be provided as well.

Abstract: A method for protecting an electronic component including a semiconductor chip with a first elastic modulus includes steps as follows. At least one application of a first protective substance is applied on an outer surface of the semiconductor chip. The first protective substance has a second elastic modulus. A second substance is applied to an outer surface of the first protective substance. The second substance has a third elastic modulus. The second elastic modulus is substantially lower than the first elastic modulus and the third elastic modulus, and the first protective substance protects the semiconductor chip from damage during the application of the second substance and/or during the life of the semiconductor chip.

Abstract: A thermocouple and power supply structure. The structure is interleaved through a substrate. The structure includes a first through via extending through the substrate and connected to a first contact on a top surface and a second contact on a bottom surface of the substrate, through via extending through the substrate and connected to the second contact and a third contact on the top surface of the substrate. The first contact, first through via and third contact formed from a first material and the second contact and second through via formed from a second material that is different from the first material.

Abstract: The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

Abstract: The present invention describes a test structure with a first set of features which is a subset of product features; and a second set of features adjacent to the first set of features, the second set occupying a smaller area than the first set and the second set being similar to the first set yet being distinguishable from surrounding structures.

Abstract: A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a second layer of dielectric material adjacent the layer of silicon nitride.

Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

Abstract: Defect density of a polysilicon metal silicide wiring is reduced by employing a block of undoped polysilicon metal silicide in locations in which dopants are not needed in the underlying polysilicon. Furthermore, detection of presence of defects in the polysilicon metal wiring that adversely impacts device performance at high frequency is facilitated by employing a block of undoped polysilicon metal silicide since defects in undoped polysilicon metal silicide is more readily detectable than defects in doped polysilicon metal silicide. Locations wherein undoped polysilicon metal silicide wiring is employed include areas over shallow trench isolation.

Abstract: A process of metal interconnects and a structure of metal interconnect produced therefrom are provided. An opening is formed in a dielectric layer. A metal layer is formed over the dielectric layer filling the opening. A film layer is formed on the metal layer and the dielectric layer. The film layer is reacted with the metal layer during a thermal process, and a protective layer is formed on the surface of the metal layer. The portion of the film layer not reacted with the metal layer is removed to avoid short between the metal layers. The protective layer can protect the surface of the metal layer from being oxidized and thus the stability and the reliability of the semiconductor device can be effectively promoted.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first semiconductor substrate has a semiconductive material projection extending therefrom, and the second semiconductor substrate has an electrically conductive interconnect extending therethrough. The interconnect electrically connects with the semiconductive material projection, and comprises a different dopant type than the semiconductor material projection. The invention also includes a method of bonding a first monocrystalline semiconductor substrate construction to a second monocrystalline semiconductor substrate construction, wherein the first construction is doped to a first dopant type, and the second construction is doped to a second dopant type different from the first dopant type.

Abstract: In a display apparatus, a display panel receives a driving signal from a driving chip through a pad and displays an image in response to the driving signal. The driving chip includes a terminal outputting the driving signal. The driving chip is mounted on the display panel using the anisotropic conductive film and electrically connected to the display panel. A lubricant layer is formed on a surface of the anisotropic conductive film to prevent an electrical defect in the connection between the driving chip and the display panel. Thus, the display apparatus may have improved yield.

Abstract: There is provided a method of manufacturing a semiconductor device in which interconnect capacitance is restrained. The semiconductor device 200 comprises a semiconductor substrate; a second interconnect insulating film 216 constituted of a ladder-type hydrogen siloxane formed on the semiconductor substrate; a second protection film 217 provided on the second interconnect insulating film 216; and an upper interconnect 270 formed in the second interconnect insulating film 216 and the second protection film 217. The second interconnect insulating film 216 is constituted of for example an L-Ox™ (trademark) film, and the second protection film 217 is constituted of for example a silicon oxide film.

Abstract: A semiconductor device includes a first insulating layer; a first poly-silicon plug formed in the first insulating layer; a second insulating layer, formed on the first insulating layer; and a second poly-silicon plug that is formed in the second insulating layer. At least one of the first and second insulating layers is made from non-doped silicate glass. The first and second poly-silicon plugs are electrically coupled to each other in a thickness direction. Preferably, both the first and second insulating layers are made from non-doped silicate glass.

Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.