Stacked Capacitor Patents (Class 257/306)
  • Patent number: 10784263
    Abstract: There is provided an apparatus includes a substrate having a main surface, a wordline buried in the substrate and a bitline buried in a shallower area than the wordline in the substrate.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Nan Wu
  • Patent number: 10777465
    Abstract: Structures including a vertical-transport field-effect transistor and a planar field-effect transistor, and methods of forming such structures. First and second sacrificial fins are respectively formed over first and second areas of the first device region. One or more semiconductor fins of the vertical-transport field-effect transistor are formed over the second device region. A first gate electrode of the planar field-effect transistor, which is arranged on the first device region between the first sacrificial fin and the second sacrificial fin, and a second gate electrode of the vertical-transport field-effect transistor, which is wrapped about the one or more semiconductor fins, are currently formed.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chun-chen Yeh, Kangguo Cheng, Tenko Yamashita
  • Patent number: 10763398
    Abstract: A light emitting device package according to an embodiment includes: a body including an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface, and first and second openings passing through the upper surface and the lower surface; and a light emitting device including first and second bonding portions disposed on the first and second openings, respectively, wherein the body may include a recess provided on the lower surface, the recess may be vertically overlapped with the first opening and the second opening, and the recess may be exposed at the side surface of the body.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: September 1, 2020
    Assignee: LG Innotek Co., Ltd.
    Inventors: Wong Jung Kim, June O Song, Ki Seok Kim, Chang Man Lim
  • Patent number: 10755855
    Abstract: Provided is a capacitor including a substrate including first and second trenches spaced apart from each other, a first electrode disposed in the first trench and one surface of the substrate, a second electrode disposed in the second trench and on the one surface of the substrate and spaced apart from the first electrode, first and second pad electrodes arranged on the first and second electrodes, respectively, and a passivation layer disposed on the first and second pad electrodes and having openings partially exposing the first and second pad electrodes, respectively.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chang Soo Jang, Yun Hee Kim, Woong Do Jung, Jeong Hoon Ryou
  • Patent number: 10755964
    Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 10707858
    Abstract: A power module includes a first terminal, a second terminal, and a number of semiconductor die coupled between the first terminal and the second terminal. The semiconductor die are configured to provide a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation and a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking configuration. Due to improvements made to the power module, it is able to pass a temperature, humidity, and bias test at 80% of its rated voltage for at least 1000 hours.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 7, 2020
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Adam Barkley, Brian Fetzer, Jonathan Young, Van Mieczkowski, Scott Allen
  • Patent number: 10700010
    Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen, Hsueh Wen Tsau
  • Patent number: 10692872
    Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 23, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson
  • Patent number: 10685983
    Abstract: To provide a semiconductor device capable of retaining data for a long time. The semiconductor device includes a first transistor, an insulator covering the first transistor, and a second transistor over the insulator. The first transistor includes a first gate electrode, a second gate electrode overlapping with the first gate electrode, and a semiconductor between the first gate electrode and the second gate electrode. The first gate electrode is electrically connected to one of a source and a drain of the second transistor.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Yutaka Okazaki, Takahisa Ishiyama
  • Patent number: 10686031
    Abstract: A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 16, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Peijie Feng, Junjing Bao, Ye Lu, Giridhar Nallapati
  • Patent number: 10686279
    Abstract: Methods and devices for wired charging and communication with a wearable device are described. In one embodiment, a symmetrical contact interface comprises a first contact pad and a second contact pad, and particular wired circuitry is coupled to the first and second contact pad to enable charging as well as receive and transmit communications via the contact pads as part of various device states.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 16, 2020
    Assignee: Snap Inc.
    Inventors: Russell Douglas Patton, Jonathan M. Rodriguez, II, Stephen Andrew Steger
  • Patent number: 10665394
    Abstract: A solid electrolyte condenser includes two condenser components disposed along a first direction Z and connected in parallel. Each condenser component includes: a porous sintered body forming an anode; an anode wire having a portion being inserted into the porous sintered body; a dielectric layer covering the porous sintered body; and a cathode portion forming a cathode. The solid electrolyte condenser includes: a spacer, which is conductive and of which two ends in the first direction Z are respectively connected with the anode wires; an anode terminal, fixed to a side of the spacer that is opposite to the two condenser components; a cathode terminal, connected with each cathode portion at the two sides in the first direction Z; a sealing resin, covering the two condenser components; and an anode connection portion, fixed at the anode terminal of the spacer and formed along the first direction Z.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: May 26, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Masahiro Noda, Takeshi Miura
  • Patent number: 10658455
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Yin Hsu, Chun Li Wu, Ching-Hung Kao
  • Patent number: 10607988
    Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Srinivas Pulugurtha, Rajesh N. Gupta
  • Patent number: 10566339
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 18, 2020
    Assignee: Toshiba Memory Coporation
    Inventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
  • Patent number: 10560094
    Abstract: An integrated circuit (IC) can include multiple power domains that are served by a common power source. In an example, a first IC power rail can be coupled to the source and a first consumer circuit. A second IC power rail can be coupled to a second consumer circuit. The second IC power rail can receive a filtered power signal from an isolation module that is coupled between the first and second power rails. In an example, an isolation module includes an integrated inductor and a capacitor (e.g., a land-side capacitor). The integrated inductor can optionally include multiple spaced apart conductive layers that are electrically coupled. The integrated inductor can optionally include a series of conductive traces and plated through holes or vias that together provide a current path with multiple turns.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Fern Nee Tan, Sanjiv Soman, Alexander Levin, Srinivasan Rajagopalan
  • Patent number: 10559687
    Abstract: A semiconductor device including a substrate; a first and second active region on the substrate; a first recess intersecting with the first active region; a second recess intersecting with the second active region; a gate spacer extending along sidewalls of the first and second recess; a first lower high-k dielectric film in the first recess and including a first high-k dielectric material in a first concentration and a second high-k dielectric material; a second lower high-k dielectric film in the second recess and including the first high-k dielectric material in a second concentration that is greater than the first concentration, and the second high-k dielectric material; a first metal-containing film on the first lower high-k dielectric film and including silicon in a third concentration; and a second metal-containing film on the second lower high-k dielectric film and including silicon in a fourth concentration that is smaller than the third concentration.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Yeol Song, Su Young Bae, Dong Soo Lee, Hyung Suk Jung, Sang Jin Hyun
  • Patent number: 10553822
    Abstract: A display device, which includes a lower face film, a TFT layer, and a light emitting element layer, includes a resin layer provided above the lower face film and below the TFT layer. A first region and a second region are included in a lower face of the resin layer, and the second region is a carbide pattern in which an amount of carbide per unit area is greater than an amount of carbide per unit area in the first region.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 4, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Mayuko Sakamoto
  • Patent number: 10546918
    Abstract: Metal-on-metal insulator structures and methods for making the same. The method includes: providing an insulator layer overlying a semiconductor substrate, forming a plurality of alternating first conductive layers and second conductive layers on the insulator layer, forming at least one dielectric layer between each of the alternating first conductive layers and second conductive layers, forming a first trench at a first location through a first portion of the plurality of the alternating first conductive layers and second conductive layers and the at least one dielectric layer, and first etching the first trench selective to the plurality of alternating first conductive layers and second conductive layers, wherein the first conductive layers are etched faster than the second conductive layers to form a first modified trench, wherein the first conductive layers are recessed relative to the center of the first modified trench greater than the second conductive layers.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Joshua M. Rubin, Oscar Van Der Straten, Praneet Adusumilli
  • Patent number: 10535661
    Abstract: Some embodiments include an integrated assembly having a capacitor. The capacitor has a storage node configured as an upwardly-opening container shape. The container shape has a first side surface and a second side surface. The first and second side surfaces are along outer edges of the container shape and are in opposing relation to one another. The second side surface has a lower portion vertically overlapped by the first side surface, and has an upper portion which is not vertically overlapped by the first side surface. A middle-level lattice is adjacent to the first side surface and supports the first side surface. A higher-level lattice is adjacent to the second side surface and supports the second side surface. Some embodiments include integrated memory (e.g., DRAM).
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yuichi Yokoyama
  • Patent number: 10529579
    Abstract: Disclosed herein is a manufacturing method of a semiconductor device that includes forming first and second layers over an underlying martial such that the first layer is between the underlying material and the second layer, forming a third layer over the second layer, forming first and second core portions apart from each other over the third layer, forming a gap portion between the first and the second core portions; and removing the second and the third layers by using the first and the second core portions and the gap portion as a mask to expose a part of the first layer.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Lionel Lupo
  • Patent number: 10522619
    Abstract: The disclosed subject matter provides a method for fabricating a three-dimensional transistor. The method includes forming an active region and two isolation structures on a semiconductor substrate. The active region is formed between the two isolation structures. The method further includes forming a photoresist layer on the active region and the isolation structures, forming an opening in the photoresist layer to expose a top surface of the active region and a portion of a top surface of each isolation structure, and then forming a trench on each side of the active region by removing a portion of the corresponding isolation structure exposed in the opening through an etching process using the photoresist layer as an etch mask. After the etching process, the portion of the active region between the two trenches becomes a three-dimensional fin structure. The disclosed method simplifies fabrication process for three-dimensional transistors and reduces product cost.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 31, 2019
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xinyuan Lin, Ying Jin
  • Patent number: 10504575
    Abstract: The invention relates to a capacitive matrix arrangement that comprises an active medium, which is arranged in a layer between word lines and bit lines whose crossing points have capacitor cells, selectable by actuation of the word lines and bit lines, arranged at them with the interposed active medium, and to an actuation method, wherein the invention is based on the object of combining active actuation of capacitive elements in a matrix with the advantages of passive actuation. This is achieved by virtue of the word lines having a specific variable Debye length, i.e. consisting of a material with a variable mobile charge carrier concentration, and being arranged between the active medium and a non-active dielectric. The actuation is effected by controlling the action of an electrical field.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: December 10, 2019
    Inventors: Kai-Uwe Demasius, Aron Kirschen
  • Patent number: 10497761
    Abstract: An organic EL display device provided with a display portion includes a flexible base material (substrate) in which the display portion is provided, an inorganic film provided on the base material, a display element portion that is provided on the inorganic film and is provided to form the display portion, and a suppression portion that is provided outside the display portion and suppresses progression of cracking that has occurred in a peripheral portion of the base material.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: December 3, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Shoji Okazaki
  • Patent number: 10497794
    Abstract: A FinFet capacitor structure includes a first, second, third, and fourth FinFet fin, a contiguous gate layer over the fins, first and second source/drain contacts in direct physical contact with the first FinFet fin on either side of the gate layer, a first gate contact in direct physical contact with a portion of the contiguous gate layer directly over the second FinFet fin, third and fourth source/drain contacts in direct physical contact with the third FinFet fin on either side of the gate layer, and a second gate contact in direct physical contact with a portion of the contiguous gate layer directly over the fourth FinFet fin. The first, second, third, and fourth source/drain contacts are all connected to a first power supply rail, and the first and second gate contacts are all connected to a second power supply rail.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: December 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Anis Mahmoud Jarrar, David Russell Tipple, Colin MacDonald
  • Patent number: 10491189
    Abstract: A topographical structure includes a carrier layer (TS); at least one metal layer (M) applied on the carrier layer; a marginal topology edge at the metal layer; and a structured cover (AB) at the topology edge.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Stephan Marksteiner
  • Patent number: 10483381
    Abstract: A semiconductor device and a method for fabricating a semiconductor device are disclosed. The semiconductor device includes a tunnel field-effect transistor and a planar device. The tunnel field-effect transistor includes a first substrate and a first electrical element, and the first electrical element is formed on one side of the first substrate; the planar device includes a second substrate and a second electrical element, the second substrate and the first substrate are an integrated structure and form a main substrate, the second electrical element is formed on one side of the second substrate, and the second electrical element and the first electrical element are disposed on a same side of the main substrate; and the planar device includes any one of a metal oxide semiconductor transistor, a capacitor, and a resistor.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 19, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jing Zhao, Chen-Xiong Zhang
  • Patent number: 10475735
    Abstract: Methods of processing a substrate include: providing a substrate with a first polymer dielectric layer; forming a first RDL on the first polymer dielectric layer; constructing a 3D MIM capacitive stack on the first RDL in at least one opening in a top surface of a second polymer dielectric layer, the 3D MIM capacitive stack having a top electrode, a bottom electrode, and a capacitive dielectric layer interposed between the top electrode and the bottom electrode; depositing a dielectric layer on the 3D MIM capacitive stack and on the second polymer dielectric layer; and removing a portion of the dielectric layer to expose at least a portion of the top electrode at a bottom of at least one opening of the 3D MIM capacitive stack and to expose at least a portion of the metal layer at a bottom of at least one opening of the second polymer dielectric layer.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: November 12, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Peng Suo, Guan Huei See, Arvind Sundarrajan
  • Patent number: 10475918
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tohru Kawai, Yasutaka Nakashiba, Yutaka Akiyama
  • Patent number: 10475841
    Abstract: A method of manufacturing a solid-state image sensor comprising a pixel part including a photoelectric conversion element and a MOS transistor, comprising steps of forming a first insulating film made of a nitrogen-containing silicon compound on the photoelectric conversion element and the MOS transistor, forming an opening in at least a portion of the first insulating film, which is positioned above a channel of the MOS transistor, forming a second insulating film on the first insulating film, forming a contact hole extending through the second insulating film and the first insulating film, and forming, in the contact hole, a contact plug to be connected to the MOS transistor.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: November 12, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Toshihiro Shoyama
  • Patent number: 10468085
    Abstract: Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Vimercati, Xinwei Guo
  • Patent number: 10468416
    Abstract: The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Tieh-Chiang Wu
  • Patent number: 10461176
    Abstract: A finFET device having a substrate and a fin disposed on the substrate. The fin includes a passive region, a stem region overlying the passive region, and an active region overlying the stem region. The stem region has a first width and the active region has a second width. The first width is less than the second width. The stem region and the active region also have different compositions. A gate structure is disposed on the active region.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
  • Patent number: 10453959
    Abstract: In a method for fabricating a field-effect transistor (FET) structure, forming a fin on a semiconductor substrate. The method further includes forming a gate on a portion of the fin and the semiconductor substrate. The method further includes epitaxially growing a semiconductor material on the fin. The method further includes depositing oxide covering the fin and the epitaxially grown semiconductor material. The method further includes recessing the deposited oxide and the epitaxially grown semiconductor material to expose a top portion of the fin. The method further includes removing the fin. In another embodiment, the method further includes epitaxially growing another fin in a respective trench formed by removing the first set of fins.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 10447228
    Abstract: A multilayer fringe capacitor includes first and second interdigitated capacitor electrodes, both parallel to and intersecting a first planar surface; third and fourth interdigitated capacitor electrodes, the first and second electrodes parallel to and separated by a non-zero distance from the third and fourth electrodes; a first set of coupling vias that electrically couples the first electrode to the third electrode; and a second set of coupling vias that electrically couples the second electrode to the fourth electrode.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: October 15, 2019
    Assignee: Kumu Networks, Inc.
    Inventors: Wilhelm Steffen Hahn, Alfred Riddle, Ernie Landi
  • Patent number: 10446551
    Abstract: To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: October 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takeshi Aoki
  • Patent number: 10438832
    Abstract: A semiconductor device manufacturing method is disclosed. The semiconductor device manufacturing method includes: a preparation step of preparing a semiconductor wafer; a removal step of removing a thickness part of the semiconductor wafer; and a cutting step of cutting the semiconductor wafer. In the removal step, a rib-shaped portion partially raised on a second main surface of the semiconductor wafer is used as an alignment mark, so that a cutter can align with the semiconductor wafer.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: October 8, 2019
    Assignee: uPI SEMICONDUCTOR CORP.
    Inventors: Masamichi Yanagida, Nobuyoshi Matsuura
  • Patent number: 10439096
    Abstract: Disclosed is an optoelectronic semiconductor chip (10) comprising: —a succession of semiconductor layers (1) that has a main plane of extension, an active layer (12) and a bottom surface (1c); —a substrate (41) that is arranged on the bottom surface (1c) of the succession of semiconductor layers (1) and has a base surface (41c) facing away from the bottom surface (1c); and —a succession of joining layers (3) which is arranged in at least some locations between the succession of semiconductor layers (1) and the substrate (41) in a vertical direction; wherein —the substrate (41) laterally protrudes from the succession of semiconductor layers (1) by a maximum of 10 ?m.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: October 8, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Johannes Baur, Lutz Hoeppel
  • Patent number: 10424586
    Abstract: A memory device includes a semiconductor substrate having at least one active area that is defined by a device isolation structure. The memory device further includes two neighboring buried word lines disposed in the semiconductor substrate of the active area. The memory device further includes a trench isolation structure disposed in the semiconductor substrate between the buried word lines.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 24, 2019
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Ying-Chu Yen, Wei-Che Chang, Yoshinori Tanaka
  • Patent number: 10411107
    Abstract: A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laura J. Schutz, Anthony K. Stamper, Siva P. Adusumilli, Joshua F. Dillon
  • Patent number: 10381353
    Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 13, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jenn-Gwo Hwu, Samuel C. Pan, Chien-Shun Liao, Kuan-Hao Tseng
  • Patent number: 10381357
    Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Srinivas Pulugurtha, Rajesh N. Gupta
  • Patent number: 10366832
    Abstract: A capacitor that includes a substrate, a first inner electrode and a second inner electrode provided above the first main surface of the substrate, the second inner electrode arranged so as to face the first inner electrode; a dielectric layer between the first inner electrode and the second inner electrode; a first intermediate electrode connected to the first inner electrode at a plurality of first locations; first surface electrodes electrically connected to the first intermediate electrode; and a second surface electrode connected to the second inner electrode at a plurality of second locations.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 30, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Toshiyuki Nakaiso
  • Patent number: 10361119
    Abstract: A method is presented for forming an enlarged contact area. The method includes forming a trench for receiving a first conductive material, forming a noble metal cap over a portion of the first conductive material, forming a dielectric capping layer over the noble metal cap, etching a portion of the first conductive material to create a via anchoring structure and an undercut region exposing a bottom surface of the noble metal cap, and depositing a plurality of liners such that one liner of the plurality of liners directly contacts an entirety of the exposed bottom surface of the noble metal cap.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Koichi Motoyama, Chih-Chao Yang, James J. Kelly, Cornelius Brown Peethala
  • Patent number: 10347641
    Abstract: A semiconductor device includes a substrate including a cell region and peripheral region and bottom electrodes on the substrate. The bottom electrodes are arranged in a first row and a second row each extending in a first direction. The first row and the second row are adjacent to each other in a second direction perpendicular to the first direction. The bottom electrodes in the first row include an outermost bottom electrode and a next outermost bottom electrode that are separated by a first distance in the first direction. The bottom electrodes in the second row include an outermost bottom electrode and a next outermost bottom electrode that are separated by a second distance in the first direction. The outermost bottom electrode in the first row is on the peripheral region of the substrate. The outermost bottom electrode in the second row is on the cell region of the substrate.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jihoon Kim, Wonchul Lee
  • Patent number: 10311938
    Abstract: One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 4, 2019
    Assignee: Apple Inc.
    Inventor: Sanjay Dabral
  • Patent number: 10297290
    Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Scott E. Sills
  • Patent number: 10297555
    Abstract: An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Chun Kuan, Chih-Teng Liao, Yi-Wei Chiu, Tzu-Chan Weng
  • Patent number: 10283585
    Abstract: A process of forming a metal-insulator-metal (MIM) capacitor is disclosed. The process includes steps of (i) forming an insulating film as a dielectric film of the MIM capacitor; (ii) forming a first portion of an upper electrode by a metal evaporation and a lift-off technique subsequent to the metal evaporation; and (iii) forming a second portion of the upper electrode by the metal evaporation and the lift-off technique subsequent to the metal evaporation for the second portion.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: May 7, 2019
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Yasuyo Kurachi, Takeshi Igarashi
  • Patent number: 10283509
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 7, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Ung Pak, Won Chul Lee