Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, which at least includes discrete conducting layers in the semiconductor substrate; forming discretely arranged supporting structures on the semiconductor substrate, capacitor openings being included between the supporting structures; forming lower electrodes on sidewalls of the supporting structures, the lower electrodes being electrically connected with the conducting layers; forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and forming an upper electrode covering the capacitor dielectric layer, to form capacitor structures.

Abstract: An integrated circuit device includes a capacitor structure, wherein the capacitor structure includes: a bottom electrode over a substrate; a supporter on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the supporter; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode comprises: a base electrode layer over the substrate and extending in a first direction that is perpendicular to a top surface of the substrate, and a conductive capping layer including niobium nitride that is between a sidewall of the base electrode layer and the dielectric layer, and also between a top surface of the base electrode layer and the dielectric layer.

Abstract: A method for forming a capacitor array structure includes the following steps: providing a substrate, a capacitor contact being exposed on a surface of the substrate, and the substrate including an array region and a peripheral region; forming a bottom supporting layer covering the substrate and the capacitor contact, the bottom supporting layer having a gap therein; forming a filling layer filling the gap and covering the capacitor contact and the surface of the bottom supporting layer, a thickness of the filling layer located at the peripheral region being larger than that of the filling layer located at the array region; forming supporting layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate; forming a capacitor hole; sequentially forming a lower electrode layer on an inner wall of the capacitor hole.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple active pillars arranged in an array on the substrate, where an outer surface layer of each of the active pillars has a concave-convex surface; forming a gate oxide layer on the substrate, where a filling region is formed between two adjacent active pillars in the same row; forming a word line and a first dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the top surface of each of the active pillars; and forming a capacitor structure on the contact layer.

Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a transistor formed on a silicon substrate and a capacitor electrically connected to the transistor by a conductive via. The capacitor comprises upper and lower conductive oxide electrodes on opposing sides of a polar layer, wherein the lower conductive oxide electrode is electrically connected to a drain of the transistor.

Abstract: An apparatus includes at least one vertical transistor having a channel region. The channel region includes an upper region having a first width and a lower region below the upper region and having a second width smaller than the first width. The upper region defines at least one overhang portion extending laterally beyond the lower region. The at least one vertical transistor further includes gate electrodes at least partially vertically beneath the at least one overhang portion of the upper region of the channel region. Additional apparatuses and related systems and methods are also disclosed.

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

Abstract: A semiconductor structure includes a substrate comprising a peripheral region and a memory region defined thereon, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer, an opening on the peripheral region of the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an interconnecting structure disposed on the second dielectric layer and two sides of the opening, a contact structure disposed in the lower portion of the opening, and a spacer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnecting structure.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one memory circuit, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: A method for preparing a semiconductor device is provided. The method includes forming a first dielectric layer over a semiconductor substrate, and forming a conductive contact penetrating through the first dielectric layer. The method also includes forming a lower landing pad over the conductive contact, and forming a second dielectric layer covering the lower landing pad. The method further includes etching the second dielectric layer to form a first opening exposing the lower landing pad, and forming an upper landing pad in the first opening. The lower landing pad and the upper landing pad form a T-shaped landing pad structure.

Abstract: A semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a conductive contact penetrating through the first dielectric layer. The semiconductor device also includes a T-shaped landing pad structure disposed over and in direct contact with the conductive contact. The T-shaped landing pad structure includes a lower landing pad and an upper landing pad disposed over the lower landing pad, and a width of the upper landing pad is greater than a width of the lower landing pad. The semiconductor device further includes a capacitor disposed over and in direct contact with the T-shaped landing pad structure, and a second dielectric layer disposed over the first dielectric layer and surrounding the T-shaped landing pad structure and the capacitor.

Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 100 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where a typical thickness of the fourth metal layer is at least 50% greater than a typical thickness of the third metal.

Abstract: An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.

Abstract: A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.

Abstract: The present disclosure provides a capacitor structure and a method for manufacturing same. The capacitor structure includes: a substrate, a first capacitor contact layer, a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer, where the first capacitor contact layer is arranged on the substrate in an array manner, the bottom electrode layer surrounds a side wall of the first capacitor contact layer and extends in a direction of the first capacitor contact layer away from the substrate, the capacitor dielectric layer covers an upper surface of the substrate, a surface of the bottom electrode layer and an upper surface of the first capacitor contact layer, and the top electrode layer covers a surface of the capacitor dielectric layer.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: A semiconductor device includes a first semiconductor fin, a first epitaxial layer, a first alloy layer and a contact plug. The first semiconductor fin is on a substrate. The first epitaxial layer is on the first semiconductor fin. The first alloy layer is on the first epitaxial layer. The first alloy layer is made of one or more Group IV elements and one or more metal elements, and the first alloy layer comprises a first sidewall and a second sidewall extending downwardly from a bottom of the first sidewall along a direction non-parallel to the first sidewall. The contact plug is in contact with the first and second sidewalls of the first alloy layer.

Abstract: A semiconductor device includes: a substrate; a test transistor over the substrate; and multi-level metal interconnections formed over the substrate spaced apart from the test transistor, wherein at least one metal interconnection among the multi-level metal interconnections is a spiral metal interconnection.

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures.

Abstract: A microelectronic device comprises: a first electrode; a second electrode located vertically below said first electrode and separated by a dielectric material; and a connection wire electrically connected to said second electrode; wherein said first electrode comprises a notch located vertically above said connection wire.

Abstract: A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via includes contact with at least one of the plurality of transistors.

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.

Abstract: A metal-clad laminate includes: an insulating layer; and a metal layer stacked on the insulating layer. The insulating layer includes: a first layer; and a second layer interposed between the first layer and the metal layer. The first layer contains a cured product of a first resin composition containing composite particles. The second layer contains a cured product of a second resin composition. The first resin composition contains composite particles, each having a core containing a fluororesin and a shell containing a silicon oxide that coats the core at least partially. The second resin composition may or may not contain composite particles. When the second resin composition contains the composite particles, a ratio of the composite particles in the second resin composition to solid content of the second resin composition is lower than a ratio of the composite particles in the first resin composition to solid content of the first resin composition.

Abstract: An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.

Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.

Abstract: A memory device includes a common source line, a memory cell array, bit lines, and a conductive layer. The common source line is formed on a substrate. The memory cell array is formed on the common source line. The bit lines are connected to the memory cell array. The conductive layer is formed over the bit lines. In an erase operation, the memory device increases a voltage of the bit lines to an erase voltage through capacitive coupling by increasing a voltage applied to the conductive layer.

Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

Abstract: A semiconductor device includes a substrate comprising a first material, a first major surface, and a second major surface opposite to the first major surface, the first material having a first coefficient of thermal expansion (CTE). A filled recessed structure having recesses extends into the substrate and has a pattern in a plan view. The recesses are spaced apart so that part of the substrate is interposed between each of the recesses, and a second material different than the first material is in the recesses. The second material has a second CTE. A structure is proximate to the first major surface over the filled recessed structure and has a third CTE. The third CTE and the second CTE are different than the first CTE. The filled recessed structure reduces stresses between the substrate and structure. In some examples, the structure comprises a MIM capacitor. In other examples, the structure comprises a heterojunction semiconductor material.

Abstract: The present invention provides a semiconductor memory device and a fabricating method thereof. The semiconductor memory device includes a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.

Abstract: Provided is an interposer structure. The interposer structure comprises an interposer substrate, an interlayer insulating film which covers a top surface of the interposer substrate, a capacitor structure in the interlayer insulating film and a wiring structure including a first wiring pattern and a second wiring pattern spaced apart from the first wiring pattern, on the interlayer insulating film, wherein the capacitor structure includes an upper electrode connected to the first wiring pattern, a lower electrode connected to the second wiring pattern, and a capacitor dielectric film between the upper electrode and the lower electrode.

Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

Abstract: An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a substrate. A gate dielectric is disposed over the substrate and between the source/drain regions. A gate electrode is disposed on the gate dielectric. A polarization switching structure is disposed on the gate electrode. A pair of sidewall spacers is disposed over the substrate and along opposite sidewalls of the gate electrode and the polarization switching structure.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.

Abstract: Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.

Abstract: Some embodiments include an integrated assembly having an access transistor. The access transistor has a first source/drain region gatedly coupled with a second source/drain region. A digit line is coupled with the first source/drain region. A charge-storage device is coupled with the second source/drain region through an interconnect. The interconnect includes a length of a semiconductor material. A protective transistor gates a portion of the length of the semiconductor material.

Abstract: In one embodiment, a semiconductor device includes a substrate including two element regions that extend in a first direction parallel to a surface of the substrate and are adjacent to each other in a second direction crossing the first direction. The device further includes an interconnection layer provided above the substrate. The device further includes an insulator provided between the substrate and the interconnection layer. The device further includes a plug extending in the second direction and in a third direction crossing the first and second directions in the insulator, provided on each of the element regions, and electrically connected to the element regions and the interconnection layer.

Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.

Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes disposed with the dielectric layer interposed therebetween; first and second through electrodes penetrating the body, connected to the first and second internal electrodes, respectively, and including nickel; first and second external electrodes, and connected to the first through electrode; and third and fourth external electrodes spaced apart from the first and second external electrodes, and connected to the second through electrode. Each of the first to fourth external electrodes includes a sintered electrode including nickel, and a first plating layer and a second plating layer stacked on the sintered electrode in order.

Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.

Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes disposed with the dielectric layer interposed therebetween; first and second through electrodes penetrating the body, connected to the first and second internal electrodes, respectively, and including nickel; first and second external electrodes, and connected to the first through electrode; and third and fourth external electrodes spaced apart from the first and second external electrodes, and connected to the second through electrode. Each of the first to fourth external electrodes includes a sintered electrode including nickel, and a first plating layer and a second plating layer stacked on the sintered electrode in order.

Abstract: A flat field transistor (FFT) based dynamic random-access memory (DRAM) (FFT-DRAM) is disclosed. The FFT-DRAM comprises an epitaxially grown source region comprising a source extension and an epitaxial source over and in contact with the source extension. The epitaxially grown source region is over a surface of a semiconductor substrate. The FFT-DRAM further comprises a trench capacitor structurally integrated into the epitaxially grown source region. The trench capacitor has a first terminal formed by the epitaxially grown source region and a second terminal being a conductive material filling one or more trenches of the trench capacitor. The second terminal is connected to a ground terminal or a fixed voltage terminal.

Abstract: Various communication systems may benefit from appropriate sharing of resources amongst multiple nodes. For example, certain wireless communication systems may benefit from using a single measurement gap for master node and secondary node measurements in a multi-radio-access-technology dual connectivity scenario, or similar scenarios. A method can include determining, by a first network node, that a gap pattern is existing in a second network node. The method can also include enquiring, by the first network node to the second network node, whether the gap pattern can be used for a new measurement. The method can further include configuring, by the first network node, a user equipment to perform the new measurement in the gap pattern, based on a response from the second network node to the enquiring.

Abstract: Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.