Abstract: A capacitor with a nano-composite dielectric layer and a method for fabricating the same are provided. A dielectric layer of a capacitor includes a nano-composite layer formed by mixing X number of different sub-layers, X being a positive integer greater than approximately 1. A method for forming a dielectric layer of a capacitor includes: forming a nano-composite layer by mixing X number of different sub-layers in the form of a nano-composition, X being a positive integer greater than approximately 1; and densifying the nano-composite layer.

Abstract: A structure having a dielectric layer sandwiched between two conductors for providing enhanced cracking resistance to the dielectric layer is disclosed, which comprises a bottom electrode layer, a dielectric layer and a top electrode layer. The structure of the invention is designed with a specific layout that prevents the dielectric layer from cracking while it is formed on a flexible substrate and is subjected to a stress developed by the bending of the substrate. The structure of invention not only can enhance the reliability of an electronic component implementing the structure, but also increase the flexibility of the dielectric layer.

Abstract: A vertical or three-dimensional non-planar configuration for a decoupling capacitor is provided, which significantly reduces the required die area for capacitors of high charge carrier storage capacity. The non-planar configuration of the decoupling capacitors also provides enhanced pattern uniformity during the highly critical gate patterning process.

Abstract: A capacitor and a method for fabricating the same are provided. The capacitor includes: a substrate; an inter-layer insulation layer formed over the substrate and including a contact hole; a storage node formed over the inter-layer insulation layer and filled into the contact hole; a tantalum oxide layer of single crystal formed over the storage node; and a plate formed over the tantalum oxide layer.

Abstract: In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable of preventing a current from flowing to a display element in signal writing operation without varying potentials of power source lines for supplying a current to the display element per row. In setting a gate-source voltage of a transistor by applying a predetermined current to the transistor, a potential of a gate terminal of the transistor is adjusted so as to prevent a current from flowing to a load connected to a source terminal of the transistor. Therefore, a potential of a wire connected to the gate terminal of the transistor is differentiated from a potential of a wire connected to a drain terminal of the transistor.

Abstract: The invention comprises capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen. In one embodiment, a capacitor includes first and second conductive electrodes having a high k capacitor dielectric region positioned therebetween. The high k capacitor dielectric region includes a layer of metal oxide having multiple different metals bonded with oxygen. The layer has varying stoichiometry across its thickness. The layer includes an inner region, a middle region, and an outer region. The middle region has a different stoichiometry than both the inner and outer regions.

Abstract: A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a first cell dielectric on the first top plate layer. Next, first and second bottom plate layers are formed on the first cell dielectric layer, and a second cell dielectric layer is formed on the second bottom plate layers. Finally, a second top plate layer is formed on the second cell dielectric layer, and the first and second top plate layers are electrically connected using a conductive plug or conductive spacer. An inventive structure formed using the inventive method is also described.

Abstract: A DRAM stack capacitor and a fabrication method thereof is disclosed. The DRAM stack capacitor is formed with a first capacitor electrode comprising a conductive carbon layer, a capacitor dielectric layer and a second capacitor electrode.

Abstract: In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.

Abstract: A non-volatile memory having a gate structure, a pair of storage units and two assist gates is provided. The gate structure is disposed on the substrate. The storage units are disposed on the sidewalls of the gate structure. The assist gates are disposed on the respective sides of the gate structure and adjacent to the storage units. Each assist gate is shared between two adjacent memory cells. The gate structure, the storage units and the assist gates are electrically isolated from one another.

Abstract: A floating gate of a flash memory device is formed in a moat formed in an isolation film. Therefore, an electric field applied between a control gate and a channel region upon cycling can be precluded or mitigated. A distance between the control gate and the channel region is set greater than a predetermined value. Therefore, an electric field applied between the control gate and the channel region upon cycling can be mitigated. As a result, a data retention characteristic and an endurance characteristic can be improved.

Abstract: A NAND-type memory device may include first and second selection transistors on a semiconductor substrate and a plurality of memory cell transistors coupled in series between the first and second selection transistors. A first source/drain region may be shared between the first selection transistor and a first of the memory cell transistors, and a second source/drain region may be shared between the second selection transistor and a last of the memory cell transistors. Moreover, a portion of at least one of the first and/or second source/drain regions may be recessed relative to a surface of the semiconductor substrate. Related methods are also discussed.

Abstract: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.

Abstract: A method of manufacturing flash memory devices, wherein in a peripheral region, a polysilicon layer is formed to extend on an isolation film at the interface of an active region and the isolation film. The isolation film that has been partially wet-etched is over etched when removing a dielectric layer. It is thus possible to prevent a thinning phenomenon in which a gate oxide film is made thin. As a result, a breakdown voltage of an oxide film, which occurs in the gate oxide film, can be prevented. Furthermore, characteristics of transistors can be prevented. In addition, resistance of about several hundreds ohm/square, of the polysilicon layer can be formed.

Abstract: A nonvolatile memory device includes a device isolating layer disposed at a substrate to define an active region and a floating gate disposed on the active region. The floating gate includes a flat portion and a pair of wall portions. The pair of wall portions extend upward from both edges of the flat portion adjacent to the device isolating layer and face each other. The nonvolatile memory device further includes a tunnel insulating layer interposed between the floating gate and the active region. Moreover, the wall portions and the flat portion are formed of a single layer, and the thickness of the flat portion is larger than a width of the wall portions.

Abstract: A non-volatile memory device includes first and second cell gates formed in a cell region; first and second peripheral gates are formed in a peri-region; and an inter-gate plug is provided between the first and second cell gates. The inter-gate plug includes a first insulating layer, a second conductive layer formed over the first insulating layer, and a third insulating layer formed over the second conductive layer.

Abstract: An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers the gate structure and surrounding substrate to induce increase tensile stresses in the N-MOS device and increased compressive stresses in the P-MOS device.

Abstract: A storage device has a two bit cell in which the select electrode is nearest the channel between two storage layers. Individual control electrodes are over individual storage layers. Adjacent cells are separated by a doped region that is shared between the adjacent cells. The doped region is formed by an implant in which the select gates of adjacent cells are used as a mask. This structure provides for reduced area while retaining the ability to perform programming by source side injection.

Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Abstract: Single-walled carbon nanotube transistor and rectifying devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed into the porous structure. A transistor of the invention may be especially suited for power transistor or power amplifier applications.

Abstract: In a transistor model generating apparatus, a transistor region extracting section extracts a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion layer region, from a mask layout data of a semiconductor integrated circuit. A dividing section sets a division line extending in a direction of a gate length of a transistor to divide the non-rectangular transistor region into a plurality of rectangular transistor regions. A relating section relates the non-rectangular transistor region and the plurality of rectangular transistor regions with the mask layout data. A size calculating section calculates a size data of each of the plurality of rectangular transistor regions. A correction value calculating section calculates a correction value of a diffusion layer length dependency parameter to the plurality of rectangular transistor regions based on the size data.

Abstract: A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.

Abstract: An ultra thin SOI MOSFET device structure and method of fabrication is presented. The device has a terminal composed of silicide, which terminal is forming a Schottky contact with the channel. A plurality of impurities are segregated on the silicide/channel interface, and these segregated impurities determine the resistance of the Schottky contact. Such impurity segregation is achieved by a so called silicidation induced impurity segregation process. Silicon substitutional impurities are appropriate for accomplishing such a segregation.

Abstract: A micromachine is generally formed using a semiconductor substrate such as a silicon wafer. One of the objects of the present invention is to realize further reduction in cost by integrating a minute structure and a semiconductor element controlling the minute structure over one insulating surface in one step. A minute structure has a structure in which a first layer formed into a frame-shape are provided over an insulating surface, a space is formed inside the frame, and a second layer is formed to cross over the first layer. Such a minute structure and a thin film transistor can be integrated over one insulating surface in one step.

Abstract: To provide a manufacturing method in which LDD regions with different widths are formed in a self-aligned manner, and the respective widths are precisely controlled in accordance with each circuit. By using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function formed of a diffraction grating pattern or a semi-transparent film, the width of a region with a small thickness of a gate electrode can be freely set, and the widths of two LDD regions capable of being formed in a self-aligned manner with the gate electrode as a mask can be different in accordance with each circuit. In one TFT, both of two LDD regions with different widths overlap a gate electrode.

Abstract: The present invention provides a semiconductor device in which a first conductive layer included in a stack having a transistor and a second conductive layer over a substrate are electrically connected. The semiconductor device provides a s conductive layer for electrically connecting the first conductive layer included in the stack having the transistor (for example, a conductive layer provided on the same layer as a gate electrode included in the transistor, a conductive layer provided on the same layer as a source wiring or a drain wiring connected to a source or drain of the transistor, a conductive layer provided in the same layer as the wire connected to the source wiring or the drain wiring, or the like) and the second conductive layer (for example, a conductive layer functioning as an antenna or a connection wire) provided over the substrate.

Abstract: Transistor type semiconducting device comprising: a substrate, an insulating layer comprising sidewalls formed on each part of the source zone and the drain zone, drain, channel and source zones, the channel zone being formed on the insulating layer and being strained by the drain and the source zones, between the side parts, a grid, separated from the channel by a grid insulator.

Abstract: In a conventional method of crystallization using a laser beam, variance (or dispersion) in a TFT characteristic becomes large, which causes various functions of a semiconductor device comprising TFTs as components of its electronic circuit to be restrained. A first shape of semiconductor region having on its one side a plurality of sharp convex top-end portions is formed first and a continuous wave laser beam is used for radiation from the above region so as to crystallize the first shape of semiconductor region. A continuous wave laser beam condensed in one or plural lines is used for the laser beam. The first shape of semiconductor region is etched to form a second shape of semiconductor region in which a channel forming region and a source and drain region are formed. The second shape of semiconductor region is disposed so that a channel forming range would be formed on respective crystal regions extending from the plurality of convex end portions.

Abstract: An electrostatic discharge (ESD) device has a parasitic SCR structure and a controllable trigger voltage. The controllable trigger voltage of the ESD device is achieved by modulating a distance between an edge of a lightly doped well and an edge of a heavily doped region located at two ends of the lightly doped well. Since the distance and the trigger voltage are linearly proportional, the trigger voltage can be set to a specific value from a minimum value to a maximum value.

Abstract: A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners surrounding the active region. The active region includes an active n region and active p pillars having vertical stripe shapes disposed at regular intervals in the active n region. The top and bottom ends of the active p pillars are separated from the edge p pillar. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar. Surplus p charges that are not used to balance the quantity of p charges and the quantity of n charges among p charges included in the upper and lower parts of the edge p pillar are eliminated or n charges are supplemented to balance the quantity of p charges and the quantity of n charges.

Abstract: A structure having a dielectric layer that includes a dielectric material comprising a first metal nitride, and an electrode layer disposed over the dielectric layer, the electrode layer comprising a second metal nitride, with the first metal nitride and the second metal nitride having at least one metal in common. Alternatively, structure has a dielectric layer including a dielectric material comprising a metal oxide, and an electrode layer disposed over the dielectric layer, the electrode layer comprising a metal nitride. The metal oxide and the metal nitride each comprise at least one of a rare earth metal, a group IIIA metal, an alkali metal, an alkaline earth metal, and a transition metal, and the metal oxide and the metal nitride comprise the same metal. An interfacial layer may be disposed under the dielectric layer.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

Abstract: A technique is provided that enables the formation of metal silicide individually for N-channel transistors and P-channel transistors, while at the same time a strain-inducing mechanism is also provided individually for each transistor type. In this way, a cobalt silicide having a reduced distance to the channel region of an NMOS transistor may be provided, while a P-channel transistor may receive a highly conductive nickel silicide, without unduly affecting or compromising the characteristics of the N-channel transistor.

Abstract: The diffusion structures in CMOS devices can be changed to minimize the effects of IR drop on those devices. A simulation can be run before tape-off to determine which transistors are at risk. The area of the source region and/or the width of the drain region of the at-risk transistor(s) can be adjusted to change the capacitive and/or resistive capability of the transistor(s). These altered diffusion structures can reduce the peak IR drop value, such as by an amount in the range of 8%-30% of the original peak noise, to prevent the chip from malfunctioning due to the resultant noise. The reduction in IR drop can be balanced with the timing delays introduced by the increased capacitance of the source area. An optimal combination of source area and drain width can be obtained and instituted during the simulation and testing processes.

Abstract: A pixel cell having a photo-conversion device at a surface of a substrate and at least one contact area from which charge or a signal is output or received. A first insulating layer is located over the photo-conversion device and the at least one contact area. The pixel cell further includes at least one conductor in contact with the at least one contact area. The conductor includes a polysilicon material extending through the first insulating layer and in contact with the at least one contact area. Further, a conductive material, which includes at least one of a silicide and a refractory metal, can be over and in contact with the polysilicon material.

Abstract: The active layer of an n-channel TFT is formed with a channel forming region, a first impurity region, a second impurity region and a third impurity region. In this case, the concentration of the impurities in each of the impurity regions is made higher as the region is remote from the channel forming region. Further, the first impurity region is disposed so as to overlap a side wall, and the side wall is caused to function as an electrode to thereby attain a substantial gate overlap structure. By adopting the structure, a semiconductor device of high reliability can be manufactured.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

Abstract: It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substrate, and in a region of a gate electrode of the p-channel MIS transistor at least 1 nm or less apart from the interface with a gate insulating film, the oxygen concentration is 1020 cm?3 or more and 1022 cm?3 or less.

Abstract: An MIS transistor having a T shaped gate is characterised by the presence of a shaping material (14) coating a T shaped solid form. The gate structure is lodged in the envelope formed by the shaping material (14). The coating of the T shape of the gate by the shaping material (14) is carried out at the very start of forming the gate structure and is chosen in such a way that it withstands all subsequent manufacturing treatments of the transistor and subsists, thus defining the definitive shape of the gate structure. One thus obtains a perfectly controlled gate shape.

Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.

Abstract: A semiconductor device may include a semiconductor substrate having a first region and a second region. The nitrogen-incorporated active region may be formed within the first region. A first gate electrode may be formed on the nitrogen-incorporated active region. A first gate dielectric layer may be interposed between the nitrogen-incorporated active region and the first gate electrode. The first gate dielectric layer may include a first dielectric layer and a second dielectric layer. The second dielectric layer may be a nitrogen contained dielectric layer. A second gate electrode may be formed on the second region. A second gate dielectric layer may be interposed between the second region and the second gate electrode. The first gate dielectric layer may have the same or substantially the same thickness as the second gate dielectric layer, and the nitrogen contained dielectric layer may contact with the nitrogen-incorporated active region.

Abstract: A thin film transistor device for a liquid crystal display, as embodied, includes a gate electrode on a transparent insulating substrate; a gate insulating film formed of a first glass composition covering the gate electrode; a semiconductor layer on the gate insulating film; and a source electrode and a drain electrode on the semiconductor layer.

Abstract: A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated.

Abstract: In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Abstract: An impurity having a conductivity type same as that contained in a source-and-drain region is implanted to an exposed surface of a gate electrode along a direction inclined to the surface of said semiconductor substrate, while using over-etched sidewalls as a mask, where the gate electrode is implanted both at the top surface and the upper portion of one side face thereof, whereas one of the source-and-drain regions is implanted with the impurity in an amount possibly attained by a single implantation, but the other portion is not implanted or only slightly implanted to a less affective degree.

Abstract: A gate electrode with a double diffusion barrier and a fabrication method of a semiconductor device including the same are provided. The gate electrode of a semiconductor device includes: a silicon electrode; a double diffusion barrier formed on the silicon electrode and including at least a crystalline tungsten nitride-based layer; and a metal electrode formed on the double diffusion barrier.

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Abstract: A MEMS device including a plurality of actuator layers formed over a substrate and a bimorph actuator having a substantially serpentine pattern. The serpentine pattern is a staggered pattern having a plurality of static segments interlaced with a plurality of deformable segments. Each of the plurality of static segments has a static segment length and each of the plurality of deformable segments has a deformable segment length, wherein the deformable segment length is substantially different than the static segment length. At least a portion of each of the plurality of deformable segments and each of the plurality of static segments is defined from a common one of the plurality of actuator layers.

Abstract: A structure of sweep-type fingerprint sensing chip capable of resisting electrostatic discharge (ESD) includes a semiconductor substrate, and a sweep-type fingerprint sensing chip formed on the semiconductor substrate, a polymer layer and a conducting metal layer. The sweep-type fingerprint sensing chip includes a sensing array region and a peripheral circuit region. The sensing array region has an exposed area for sensing a plurality of fingerprint fragment images as a finger sweeps thereacross. The peripheral circuit region, which is formed on the substrate and located around the sensing array region, controls an operation of the sensing array region. The polymer layer is disposed on the peripheral circuit region and has a flat and smooth outer surface. The conducting metal layer is disposed on the flat and smooth outer surface of the polymer layer. The conducting metal layer discharges the approaching electrostatic charges to the ground to avoid damaging of the sensing chip.

Abstract: A micromachine successfully reduced in parasitic capacity between input and output electrodes, and having an oscillator configured as ensuring a high S/N ratio under operation at higher frequencies is disclosed. The micromachine comprises an insulating layer formed on a substrate; a first electrode for signal input formed on the insulating layer; a second electrode for signal output formed on the insulating layer; and an oscillator electrode formed as being opposed with the first electrode and the second electrode and as being spaced therefrom by an air gap, wherein the insulating layer has a groove formed therein at least between the first electrode and the second electrode.