Abstract: A spin injection magnetization reversal element includes a ferromagnetic fixed layer, an isolation layer and a ferromagnetic free layer. The area of contact between the ferromagnetic fixed layer and the isolation layer is larger than an area of contact between the ferromagnetic free layer and the isolation layer. The ferromagnetic fixed layer may be divided into ferromagnetic first fixed layer and ferromagnetic second fixed layer, and the isolation layer may be divided into first isolation layer and second isolation layer. The ferromagnetic first fixed layer may be arranged on one of opposed principal surfaces of the ferromagnetic free layer with the first isolation layer in between, and the ferromagnetic second fixed layer may be arranged on the other of the opposed principal surfaces of the ferromagnetic free layer with the second isolation layer in between. The element holds recorded magnetization and can reverse magnetization with a small current density.

Abstract: A solid-state image sensing device having an effective pixel area and an optical black area disposed on one principal surface of a substrate, includes photoelectric converter elements, a wiring part containing a plurality of wiring layers disposed on the one principal surface of the substrate, in which in the optical black area more wiring layers are disposed than in the effective pixel area, an interlayer dielectric disposed between, among the plurality of wiring layers, a topmost first wiring layer and a second wiring layer disposed beneath the first wiring layer, a passivation film disposed on the interlayer dielectric in the effective pixel area and disposed on the first wiring layer in the optical black area, and inner lenses disposed at least at positions on the passivation film that corresponds to the effective pixel area, a thickness of the passivation film being equal to or less than a thickness of the first wiring layer.

Abstract: In this invention, an extended gate FET with a tin dioxide membrane is applied to fabricate a berberine sensor. There are two methods for fabricating the berberine sensor. First, it is mixed by the macromolecule polymer and electrocatalytic activities. The membrane is adsorbed on the SnO2/ITO glass and the berberine sensor is completed. Second, a polymer is used to immobilize enzyme on the substrate and detect the berberine. In this invention, the extended gate field effect transistor of the SnO2/ITO glass is applied to fabricate a durable berberine detection electrode. One of the berberine sensors that is macromolecule polymer, the optimal measurement environment is in distilled water and the best response curve can be realized, the detection rang is from 1×10?3M to 5×10?7M and the linear range is about 121.47 mV/pC. The berberine sensor based on the enzyme that optimal measurement environment is in 0.1M phosphate buffer solution at pH7.4 and better response curves can be obtained.

Abstract: A forward light monitoring photodiode having a high reflection film with low dark current for detecting forward light emitted from a laser diode and power of the laser diode in spite of the change of temperatures or yearly degradation. The high reflection film is made by depositing an SiON layer upon an InP window layer or an InP substrate by a plasma CVD method. Al2O3/Si reciprocal layers or Al2O3/TiO2 reciprocal layers are produced upon the SiON layer. The high reflection film reflects 80%-90% of a 45 degree inclination incidence beam and allows 20%-10% of the incidence beam to pass the film and arrive at the InP window or substrate.

Abstract: MOSFETs are provided to connect the sensor input terminals of a ratiometric output sensor to a pair of power terminals, and the gate of each MOSFET is coupled to the opposite power terminal so that both MOSFETs are rendered conducting to power the sensor when a supply voltage of a predetermined polarity is connected across the power terminals but one of the MOSFETs is rendered non-conducting when a voltage of the opposite polarity is so applied. The MOSFET that is rendered non-conducting is oriented so that any internal source-drain diode does not bypass current around the MOSFET when voltage of the opposite polarity is applied. Optionally, over-voltage protection is provided by an input voltage sensor controlling the other MOSFET through a third MOSFET.

Abstract: A rectifying diode. The diode comprises a first conductor region and a second conductor region. The diode further comprises a diode conductive path between the first conductor region and the second conductor region. The path comprises a first semiconductor volume having a non-uniform distribution of ions and a second semiconductor volume having a uniform distribution of ions relative to the first semiconductor volume.

Abstract: An anti-punch-through semiconductor device is provided. The anti-punch-through semiconductor device includes a substrate, at least an isolation region and a plurality of trench devices. The trench device is disposed in the substrate. The trench device includes a source/drain region. The source/drain region of the trench device is disposed at the bottom of the trench device. The isolation region is disposed in the substrate and between the source/drain regions of each trench device.

Abstract: A capacitor includes a first electrode and a second electrode arranged so that a main surface of the first electrode opposes a main surface of the second electrode, a first pseudo electrode layer disposed on the main surface of the first electrode, and a dielectric layer disposed between the first pseudo electrode layer and the main surface of the second electrode. The first pseudo electrode layer includes conductive particles electrically coupled to the first electrode.

Abstract: An apparatus including a first electrode; a second electrode; a first and second ceramic material disposed between the first electrode and the second electrode, the second ceramic material having a greater electrical conductivity than the first ceramic material. A method including forming a first ceramic material film and a different second ceramic material film on a first electrode; and forming a second electrode on the second ceramic material film to form a capacitor structure having the first ceramic material film and the second ceramic material film disposed between the first electrode and the second electrode, wherein the first ceramic material has a conductivity selected to dampen undesired oscillations in electrical device operation to which the capacitor structure may be exposed. An apparatus including a first electrode; a second electrode; and a composite dielectric including a plurality of dielectric films including a different Curie temperature.

Abstract: A method to reduce parasitic mutual capacitances in embedded passives. A first capacitor is formed by first and second electrodes embedding a dielectric layer. A second capacitor is formed by third and fourth electrodes embedding the dielectric layer. The third and first electrodes are etched from a first metal layer. The fourth and second electrodes are etched from a second metal layer. The first and the fourth electrodes are connected by a connection through the dielectric layer to shield a mutual capacitance between the first and second capacitors.

Abstract: A substrate is disclosed that includes a base material, a first capacitor arranged on the base material, and a second capacitor arranged on the base material near the first capacitor. The first capacitor is realized by a lower electrode, a first dielectric layer, and a first upper electrode; and the second capacitor is realized by the lower electrode that is held in common with the first capacitor, a second dielectric layer, and a second upper electrode having a smaller area than the first upper electrode. The first capacitor and the second capacitor are connected in parallel in a case where the capacity of the first capacitor is less than a desired capacity.

Abstract: A bipolar transistor includes a collector located over a substrate; and a heat conductive path connecting the substrate to the collector. The heat conductive path is filled with a heat conductive material such as metal or polysilicon. In one embodiment the heat conductive path runs through the collector to extract heat from the collector and drain it to the substrate. In alternate embodiments, the transistor can be a vertical or a lateral device. According to another embodiment, an integrated circuit using BiCMOS technology comprises pnp and npn bipolar transistors with heat conduction from collector to substrate and possibly p-channel and n-channel MOSFETS. According to yet another embodiment, a method for making a transistor in an integrated network comprises steps of etching the heat conducting path through the collector and to the substrate and fill with heat conductive material to provide a heat drain for the transistor comprising the collector.

Abstract: A semiconductor device comprises a first semiconductor layer of the first conduction type; and a second semiconductor layer of the second conduction type formed on one surface of the first semiconductor layer. The semiconductor device also comprises a gate electrode formed in a trench with an insulator interposed therebetween, the trench passing through the second semiconductor layer and reaching the first semiconductor layer; and a third semiconductor layer of the first conduction type formed on a surface of the second semiconductor layer between adjacent gate electrodes. The semiconductor device further comprises a first main electrode connected to the second and third semiconductor layers: a fourth semiconductor layer of the second conduction type formed on the other surface of the first semiconductor layer; and a second main electrode connected to the fourth semiconductor layer. The semiconductor layer between adjacent gates has a width d, which satisfies a relation of 2??d?0.

Abstract: A complementary bipolar transistor is fabricated using an available a portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.

Abstract: A semiconductor device has a structure capable of connecting a lead terminal directly to an electrode on a front surface thereof. The semiconductor device includes a first main electrode provided on the front surface, a second main electrode provided on a back surface, and a metal film provided so as to cover at least a portion of a surface of the first main electrode and for soldering the lead terminal thereto. Here, the metal film includes a plurality of opening portions through which the surface of the first main electrode is exposed.

Abstract: A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material property than the matrix, forming a dispersed phase, the resulting composite material having a different material property than the matrix.

Abstract: Processing techniques are disclosed for batch fabrication of microstructures comprising an oxide mask on a substrate with submicron openings formed therein, and microstructures having deep-submicron, high aspect-ratio etched trenches, using conventional optical photolithography. Exemplary high aspect-ratio etched-trench microstructures that may be produced include single crystal resonators and sensors.

Abstract: A high-hardness and corrosion-tolerant integrated circuit packing mold comprises a package mold including at least one filling channel, at least one mold cavity, and at least one channel between the mold cavities; a protecting layer deposited upon surfaces of the package mold and the protecting layer being an amorphous coating layer. In one case, the protecting layer is a graded layer including an amorphous coating layer and a middle layer. In a second case, the protecting layer is a multiplayer structure formed by at least one amorphous coating layer and at least one polycrystal coating layer. In the third case, the protecting layer is a compound structure formed by distributing polycrystal material into an amorphous coating layer.

Abstract: A nitride semiconductor device includes a nitride semiconductor layer having a main surface, and an ohmic electrode formed on the main surface of the nitride semiconductor layer The ohmic electrode includes a silicon layer formed to contact with the main surface of the nitride semiconductor layer, and a first metal layer formed on the silicon layer.

Abstract: A communication board mounted on an electronic device includes a plurality of antennas configured to transmit and/or receive a signal by electromagnetic induction, where each of the plurality of antennas is provided on a substrate, as a coil-shaped pattern, a semiconductor chip mounted on the substrate, the semiconductor chip including at least one of a transmission circuit which transmits a signal to the antenna and a reception circuit which receives a signal transmitted from the antenna, and an input-and-output end that is connected to the semiconductor chip via a wiring layer provided on the substrate and an electronic circuit of the electronic device. The communication board communicates with a communication board mounted on another electronic device via the antenna by electromagnetic induction.

Abstract: A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased.

Abstract: A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. The semiconductor die may be supported on the leads extending across the leadframe. The package may further include a spacer layer affixed to the electrical leads to fortify the semiconductor package and to prevent exposure of the electrical leads during the molding of the package.

Abstract: A semiconductor device having a plurality of chips is reduced in size. In HSOP(semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the PMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.

Abstract: A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame, including leads, is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame semiconductor device assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi-part lead frame may be dissimilar.

Abstract: A semiconductor package encapsulating a semiconductor chip provides inner leads and outer leads for establishing electrical connections with the substrate. Herein, a lead frame is set into the metal mold, into which a resin is injected and which is clamped in proximity to the outer leads. Thus, the semiconductor package is sealed so as to avoid unwanted formation of resin burrs around lower surfaces of the inner leads. In addition, a semiconductor device is produced using a package in which a semiconductor chip mounted on a stage and terminals are embedded within a resin. Each terminal provides an electrode surface, an interconnecting portion, and an exposed terminal surface. Herein, an isolation portion is formed as an integral part of the package made by the resin and is arranged in the prescribed area between the electrode surface and the exposed terminal surface.

Abstract: A method of fabricating a lead frame for a semiconductor device. The lead frame has a lead electrically connected to a semiconductor chip within sealing resin and sealed into the sealing resin such that at least a part of its lower surface is exposed from a lower surface of the sealing resin. The method includes a punching step for forming the lead by punching processing in a direction from the lower surface to its upper surface and a coining step for subjecting the lead to coining processing from the side of the upper surface after the punching processing.

Abstract: In one embodiment, a stack is assembled comprising a first integrated circuit package, and a substrate connector which connects the integrated circuit package to a circuit board. In one embodiment, the substrate connector includes an interposer substrate and a patch substrate bonded to the interposer substrate. Each substrate includes columnar conductors extending through the substrate to connect to another layer. Other embodiments are described and claimed.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A semiconductor device includes external interface terminals and processing circuits, and it is fed with an operating power source when detachably set in a host equipment. Power source feeding terminals (VCC, VSS) among the external interface terminals are long enough to keep touching the corresponding terminals of the host equipment for, at least, a predetermined time period since the separation of an extraction detecting terminal among the external interface terminals, from the corresponding terminal of the host equipment, and they are formed to be longer in the extraction direction of the semiconductor device than the extraction detecting terminal. Thus, a time period till the cutoff of the power source is easily made comparatively long. The power source feeding terminals should preferably be extended onto the insertion side of the semiconductor device, but an extendible distance is sometimes liable to be limited.

Abstract: A nano-sized metal particle composite includes a first metal that has a particle size of about 50 nanometer or smaller. A wire interconnect is in contact with a reflowed nanosolder and has the same metal or alloy composition as the reflowed nanosolder. A microelectronic package is also disclosed that uses the reflowed nanosolder composition. A method of assembling a microelectronic package includes preparing a wire interconnect template. A computing system includes a nanosolder composition coupled to a wire interconnect.

Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

Abstract: The present invention relates to a three-dimensional semiconductor module having at least one unit semiconductor device connected to the outer-facing side surfaces of a multi-side ground block. The unit semiconductor device has a structure in which a semiconductor package (or semiconductor chip) is mounted on a unit wiring substrate. Ground pads to be connected to the outer-facing side surfaces of the ground block are formed on the first surface of the unit wiring substrate, the semiconductor chip is mounted on the second surface opposite to the first surface, and contact terminals electrically connected to the semiconductor chip are formed on the second surface.

Abstract: An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability.

Abstract: A semiconductor package may include a printed circuit board having a conductive bump pad. At least one semiconductor chip may be electrically connected to the printed circuit board. A lead free conductive bump may be mounted on the conductive bump pad. The lead free conductive bump may include no more than about 0.3% by weight of copper. The lead free conductive bump may include about 3.0% to about 4.0% by weight of silver, about 0.1% to about 0.3% by weight of copper and about 95.7% to about 96.9% by weight of tin.

Abstract: A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern including straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of lines, or contiguous or spaced polygons, such as hexagons. Portions of the dummy circuit pattern may also be formed with an orientation, size and position that are randomly selected.

Abstract: A system and method is disclosed for venting pressure from an integrated circuit package that is sealed with a lid. During a surface mount process for mounting a ball grid array integrated circuit package to a circuit board the application of heat (1) weakens the solder that seals a soldered lid, and (2) increases vapor pressure within the integrated circuit package. This may cause the soldered lid to move out of its soldered position. The present invention solves this problem by providing an integrated circuit with a solder mask that has a plurality of solder mask vents that form a plurality of vapor pressure vents through the solder. The vapor pressure vents prevent the occurrence of any increase in vapor pressure that would shift the soldered lid out of its soldered position. An alternate embodiment vents pressure through an epoxy layer that is used to attach a lid by epoxy.

Abstract: A packaging structure (10) is provided having a hermetic sealed cavity for microelectronic applications. The packaging structure (10) comprises first and second packaging layers (12, 28) forming a cavity. Two liquid crystal polymer (LCP) layers (16, 22) are formed between and hermetically seal the first and second packaging layers (12, 28). First and second conductive strips (18, 20) are formed between the LCP layers (16, 22) and extend into the cavity. An electronic device (24) is positioned within the cavity and is coupled to the first and second conductive strips (18, 20).

Abstract: A package for an electronic device equipped with an external terminal other than a terminal for mounting, includes a first internal terminal electrically connected to an external terminal other than the terminal for mounting and a second internal terminal connected to an external terminal for mounting for ground connection which is selectively connected to the internal terminal.

Abstract: A semiconductor device 1 includes a SOI substrate 10, an interconnect layer 20, and an isolation region 30. The SOI substrate 10 includes a supporting substrate 12, an insulating film 14 (substrate insulating film) provided on the supporting substrate 12, and a silicon active layer 16 (silicon layer) provided on the insulating film 14. Preferably, the supporting substrate 12 has a thickness of 10 ?m to 150 ?m. A thermal conductivity of the insulating film 14 is lower than that of the silicon active layer 16 but higher than that of SiO2, at a normal temperature.

Abstract: A semiconductor packaging structure includes a baseboard, a semiconductor chip set, a thermal conductor, a package and a heat sink. The thermal conductor is located on the baseboard. The semiconductor chip set is directly mounted onto the thermal conductor. The heat sink is coupled on the thermal conductor. Hence heat energy generated by the semiconductor chip set, when electrically energized, is transferred through the thermal conductor to the heat sink, to perform heat exchange.

Abstract: An anti-warp heat spreader for semiconductor devices is disclosed, wherein the heat spreader is made of a metal sheet of substantially constant thickness, the metal sheet being perforated by at least one opening to allow for the percolation of an adhesive or a resin. The heat spreader is designed to strengthen the package by providing a strong bond between its components, i.e., the circuit board, die, heat spreader and reinforcing frame. At the same time the heat generated by the die during operation is efficiently dissipated. The heat spreader can easily be attached to the die by positioning it in the mold used to produce the reinforcing frame and then fill the mold with a mold compound. The mold compound will easily flow through the opening or openings, thereby filling the gap between the heat spreader and the die. The mold compound replaces the air that escapes from the gap through the opening or openings. Thus, a strong and intense connection between the die and the heat spreader is constituted.

Abstract: A heat radiation member including a thermal diffusion sheet; and a thermally conductive polymer layer provided on at least a part of the thermal diffusion sheet. Thermal conductivity of the thermally conductive polymer layer in a thickness direction of the layer is higher than thermal conductivity of the thermally conductive polymer layer in a direction parallel to the surface of the layer. The heat radiation member is formed by joining an independently formed thermally conductive layer including a thermally conductive filler onto the thermal diffusion sheet. The thermally conductive filler are oriented in a specific direction. Alternatively, the heat radiation member is formed by placing a thermally conductive polymer composition containing a thermal conductive filler containing a thermally conductive filler onto the thermal diffusion sheet, orienting the thermally conductive filler in a specific direction, and curing the thermally conductive polymer composition while the orientation is maintained.

Abstract: Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and packages, and the assemblies and packages created by the methods, are disclosed. A sacrificial layer is deposited on a support substrate. An etch stop layer having a lower etch is deposited on the sacrificial layer. Redistribution lines in a dielectric material are formed on the support substrate on the etch stop layer. Semiconductor dice, either singulated or at the wafer level, are connected to the redistribution lines. The assembly may be scribed to allow the sacrificial layer to be etched to enable removal of the semiconductor dice and associated redistribution layer from the support substrate. The etch stop layer is removed to allow access to the redistribution lines for conductive bumping.

Abstract: A stacked semiconductor chip package comprising a first semiconductor chip having an upper surface, a lower surface opposed to said upper surface, and a plurality of conductive metal lines formed on said upper surface of said first semiconductor chip; a plurality of metal elements each having a first arm portion located on said upper surface of said first semiconductor chip and connected electrically to a corresponding one of said metal lines, a second arm portion located on said lower surface of said first semiconductor chip; and a second semiconductor chip having a lower surface and a plurality of conductive bumps provided on said lower surface, and mounted on said upper surface of said first semiconductor chip in such a manner that said solder bumps of said second semiconductor chip is electrically connected to said corresponding conductive metal lines on said upper surface of said first semiconductor chip.

Abstract: A semiconductor device and a method of fabricating the same may be provided. The semiconductor device may include an insulation material as a base frame of a PCB, including an opening penetrating the insulation material with sidewalls plated with a gold (Au) layer. The semiconductor device may further include a printed circuit board for use in a module, having a pad whose surface may be coated with an organic solderability preservative (OSP) and an opening whose sidewalls may be plated with a nickel (Ni) layer and a gold (Au) layer, and a semiconductor device mounted on the PCB via the pad. During a temperature cycling reliability test on the semiconductor device, no defects, for example, cracks may form inside the opening.

Abstract: A semiconductor package system is provided including forming a support platform, mounting a first device over the support platform, forming a bump on the support platform, and mounting a second device on the first device and the bump.

Abstract: A circuit substrate on which bubbles generated between a pad electrode and a land can be eliminated is disclosed. Resists are provided at any one of ends of a land on a circuit substrate. Solder paste is printed on the land, and an electronic component (MOSFET or the like) is placed and heated on the same. When the solder paste is melted, an electrode of the electronic component comes into contact with the resists on the circuit substrate. A gap is created by the resists between the land and the electrode of the electronic component. Since the melted solder paste does not wet the resists, bubbles generated in the solder escape to the end of the land through the gap.

Abstract: A semiconductor device of the invention includes a substrate in which a power-supply electrode and a ground electrode are provided. A first semiconductor chip is disposed over the substrate and has a first conductor layer formed on a surface facing a second semiconductor chip. A second conductor layer is disposed over the first semiconductor chip and has a second conductor layer formed on a surface facing the first semiconductor chip. And an adhesive layer is disposed between the first conductor layer and the second conductor layer and bonds together the first semiconductor chip and the second semiconductor chip. In the semiconductor device, the adhesive layer and the first and second conductor layers function as a capacitor.

Abstract: A stacked semiconductor package comprises two semiconductor chips (11, 12) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate (13) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.