Abstract: This invention is used to determine the condition of power transformers using real-time on-line high speed measurements. Specifically, a failure prediction method is described. This provides alerts prior to a catastrophic event that could cause major damage to the transformer and resulting business losses. Real time absolute phase angle and frequency as well as real and reactive power measurements from both sides of the transformer are used to estimate frequency domain transfer functions. The transfer functions are in fact the complex admittance functions relating the input and the outputs from the transformer. Three methods of computing the transfer function are outlined in this application. First, the Fast Fourier Transform (FFT) of both the input and the output wave forms are used to compute the transfer functions continuously in real time.

Abstract: There is provided a test apparatus for testing a device-under-test, having a reference clock source for generating reference clock for controlling operations of the device-under-test, a clock regenerating circuit for generating, based on a phase adjusting signal to be inputted, regenerated clock whose frequency is almost equal with the reference clock and having a phase difference from the reference clock corresponding to the phase adjusting signal, a timing comparator for obtaining a value of an output signal outputted from the device-under-test based on the regenerated clock, a first phase comparing section for outputting the phase adjusting signal that converges the phase difference into a reference phase difference set in advance to the clock regenerating circuit based on the comparison result of the phases of the output signal and the regenerated clock and a storage section for sequentially storing the phase adjusting signals outputted from the first phase comparing section.

Abstract: An electric field object sensing system (1) and method. The system (1) comprises a transmitter electrode (2), a receiver electrode (4), a switching circuit (32) coupled to the receiver electrode, an alternating voltage source (3) coupled to the transmitter electrode (2) and the switching circuit (32), and an output connection (34) coupled to the receiver electrode (4). Charge pumping performed according to the alternating voltage cycle provides a voltage over a capacitor (43) of the switching circuit (32) that increases dependent upon the capacitive coupling between the transmitter electrode (2) and the receiver electrode (4). The voltage over the capacitor (43) of the switching circuit (32) is allowed to saturate, and the saturated voltage is used as an output (20) that varies when an object (8) is in the vicinity of the transmitter and receiver electrodes. The output (20) may be fed to a high impedance read-out means e.g. an (24).

Abstract: A sensor system includes a thin-film sensor provided with at least one contact area on the surface thereof, and a printed circuit board provided with at least one contact pad on the surface thereof. The thin-film sensor is arranged in relation to the surface of the printed circuit board such that the surface of the thin-film sensor opposes the surface of the printed circuit board. In order to transmit sensor currents from the thin-film sensor to the printed circuit board, a conductive glue adheres to both the contact area of the thin-film sensor and to the contact pad on the surface of the printed circuit board.

Abstract: A sensor circuit is provided that comprises at least one pair of interconnected T-networks. Each pair comprises a first T-network including a first impedance serially connected to a second impedance at a first junction and a first variable resistance sensor element connected to the first junction. Each pair also comprises a second T-network including a third impedance serially connected to a fourth impedance at a second junction and a second variable resistance sensor element connected to the second junction. The sensor circuit further comprises an operational amplifier connected to the first T-network of a selected one of the at least one pair of T-networks and a constant voltage source connected to the second T-network of the selected T-network pair.

Abstract: A device measures an impedance of an electronic component with using an impedance measuring apparatus. The impedance measuring device includes first and second probes to be connected to measuring terminals of the impedance measuring apparatus, an anisotropic conductive sheet, and a pressing member for pressing the electronic component toward the first and second probes. The first probe has a first contact surface. The second probe has a second contact surface flush with the first contact surface. The anisotropic conductive sheet has a first surface contacting the first and second contact surface, and a second surface opposite to the first surface. The pressing member causes first and second external terminals of the electronic component to contact the anisotropic conductive sheet. The conductive sheet includes an insulating elastic sheet and plural conductive wires penetrating the elastic sheet to expose from the first surface and the second surface.

Abstract: The invention aims to provide a vertical type probe card in which a probe can scrape an oxide film on a surface of an electrode of the measurement object, thereby ensuring stable contact with the electrode of the measurement object.

Abstract: A coaxial probe for near-field measurements including a connection wire of which a first end is connected to a connector, the connection wire covered with a dielectric substrate and a shield to form a waveguide. The probe has a diameter D equal to at least 300 micrometers.

Abstract: A cooling apparatus includes a cooling device, a baseplate and at least one shock absorber. The cooling device is used for absorbing and dissipating heat. The shock absorber resiliently supports the cooling device on the baseplate. A testing machine, using the cooling apparatus, for testing an electronic product is also disclosed.

Abstract: A testbed is provided for testing broadband wireless test units. The testbed includes an enclosure and a plurality of I/O connectors accessible externally of the enclosure. Each of the I/O connectors is for being electrically coupled to a respective test unit. A series of connections within the enclosure serve to interconnect the plurality of I/O connectors as respective nodes in a bus-mesh network topology.

Abstract: The invention includes a design for device design-for-test and a burn-in-board that reduce the number of external components per device on the board. Inputs to the I/Os of a device from input means are inverted between pairs of output pins. A single resister is coupled between an output that is true (e.g., not inverted) and an output that is inverted. Thus, instead of using one or more resistors per I/O from the DUT, a single resister can be coupled between inverted and non-inverted outputs.

Abstract: An EMI suppressive device. In one embodiment, the EMI suppressive device is electrically connected to an electric motor having a substantially non-conductive shroud and a conductive drive shaft. The EMI suppressive device includes a packaged circuit that suppresses electromagnetic interference and contains one or more signal terminals that connect to the electric motor and one or more ground terminals that connect to ground. The EMI suppressive device also includes a bracket that supports the packaged circuit and has one or more interfaces that interface with one or more of the one or more ground terminals of the packaged circuit, and a conductive element that contacts the shroud and electrically connects to the drive shaft to provide a path to ground.

Abstract: Methods and apparatus are provided for testing to determine the existence of defects and faults in circuits, devices, and systems such as digital integrated circuits, SRAM memory, mixed signal circuits, and the like. In particular, methods and apparatus are provided for detecting faults in circuits, devices, and systems using input control signals to generate controlled-duration, controlled pulse-width, transient power supply currents in a device under test, where said transient power supply currents are of controllable bandwidth and can be used as observables to determine faulty or defective operation. Additionally, methods and apparatus are provided to permit high bandwidth sensing of transient supply currents as need to preserve the narrow widths of these current pulses. These methods may include autozero techniques to remove supply current leakage current and DC offsets associated with practical current sensing currents.

Abstract: A checking unit includes a power net extracting means for extracting a power net with power attribution, which is segmented by a power-decoupling element, with reference to circuit design data of the printed wiring board; a parts number extracting means for extracting a parts number of an integrated circuit which is connected to the extracted power net; a parts headcount calculating means for calculating a headcount of the extracted parts; a judging means for comparing the extracted parts headcount with a predetermined reference value; and a representing means for representing a name of the power net and the parts number of the integrated circuit as an unprocessed location of power decoupling when the headcount is larger than the reference value, whereby inspecting quickly whether or not a power supply in use, which is shared by each of the integrated circuits, is decoupled at higher frequencies by the power-decoupling element.

Abstract: Power measurement and control in transmission systems are affected by changes in load conditions. A method and system are provided for detecting and controlling power levels independent of such load conditions.

Abstract: A superconducting circuit includes a first transformer to produce a first alternating-current output at a secondary-side inductor, a second transformer to produce a second alternating-current output at a secondary-side inductor, a first pulse generating circuit to produce a single flux quantum pulse responsive to the first alternating-current output, a second pulse generating circuit to produce a single flux quantum pulse responsive to the second alternating-current output, and a confluence buffer circuit to merge the single flux quantum pulses from the pulse generating circuits, wherein each of the pulse generating circuits includes a superconducting loop including the secondary-side inductor, a first Josephson junction situated in the superconducting loop to generate the single flux quantum pulse, and a second Josephson junction situated in the superconducting loop, a threshold value of the second Josephson junction for an electric current flowing through the secondary-side inductor being different from tha

Abstract: A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block receives a first data input and second data input from redundant logic blocks or from logic blocks designed to provide complementary outputs. The decision block provides an output that is at a same logic level as the first data input if the two data inputs are at expected logic levels during normal operating conditions (i.e., no disturbances). The decision block provides an output that is at a same logic level as a previous output of the decision block if the two data inputs are not at expected logic levels during normal operating conditions.

Abstract: A buffer circuit (31), for example a repeater or receiver circuit for a signal wire of an on-chip bus, receives an input signal, and produces an output signal. The buffer circuit (31) comprises a first inverting stage (7) and a second inverter stage (9). The second inverting stage (9) provides the drive for the output (5). The first inverting stage (7) has additional circuitry (15, 17, 19, 21, 23, 25, 27, 29) for controlling the strengths of the pull up path and the pull down path. The pull up/down paths are dynamically controlled according to the status of one or more aggressor signals. In one embodiment the switching threshold is lowered only in the worst case delay scenario, i.e. when the signal wire (3) is at a different logic level to the aggressor signals. In another embodiment, the switching threshold is raised when the signal wire and aggressor signals are all at the same logic level, thereby reducing crosstalk.

Abstract: A programmable interconnect structure to couple a first wire segment to a second wire segment of an integrated circuit comprising: a pass-gate to electrically couple the first wire segment to the second wire segment fabricated on a substrate layer, and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer, wherein changing data stored in the memory element provides a programmable method to achieve one of: isolate said first wire segment from said second wire segment; and couple said first wire segment to said second wire segment.

Abstract: A pre-buffer level shifter and an I/O buffer apparatus are provided. The pre-buffer level shifter includes a switchable current source, a current mirror, a buffer unit, a first clamping circuit and a second clamping circuit. Because of a clamping circuit inside a thin oxide MOS transistor device of the pre-buffer level shifter, the present invention can control the voltage swing of the signal for driving an output buffer within a suitable voltage range. Thus, the pre-buffer level shifter can correctly drive the output buffer made of thin oxide MOS transistor devices, increase the operating speed and ensure the reliability thereof.

Abstract: A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.

Abstract: CMOS buffer circuits with reduced short circuit current. In the CMOS buffer circuit, an output stage drives an output terminal and comprises a first output transistor of a first conductive type and a second output transistor of a second conductive type. An output driving unit produces a first signal to turn off the first output transistor according to a delay signal. A bidirectional delay unit is controlled by the input signal to turn on the second output transistor after the first output transistor be turned off. In the bidirectional delay unit, a bidirectional logic unit generates two logic signals according to an inversion signal of the input signal, first and second bidirectional buffers are coupled to the output driving unit, generating a second signal to turn on the second output transistor according to the input signal and the two logic signals.

Abstract: A chain of processing element (10a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic circuit (14) of a next processing element (10a, 10, 10b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (10b) includes loading time points of loading all processing elements (10a, 10) other than the final processing element (10).

Abstract: A deglitch circuit capable of removing noise with low power consumption. Voltage is input to a first inverter, connected to a power supply line via a first current source and grounded via a second current source. The first inverter is grounded via a capacitor and connected to first and second transistors. The gate terminals of these transistors receive a second control voltage, which is lower than the power supply voltage, and a first control voltage, which is higher than the ground level. The second transistor is connected to the ground line via a fourth current source. First voltage is supplied to a first input terminal of the latch circuit via a second inverter. The first transistor is connected to the power supply line via a third current source. Second voltage is supplied to a second input terminal of the latch circuit via the second inverter.

Abstract: Current feedback amplifiers circuits that generate common mode (CM) and/or differential mode (DM) currents are provided herein. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: An improved differential inverter comprising a differential inverter having a differential input for receiving a first input signal and a second input signal, said inverter further comprising a differential control input for receiving a first control signal and a second control signal. The improved differential inverter further comprises a differential output for transmitting a first output signal and a second output signal. The improved differential inverter further comprises a controlled bias generator that generates the second vector of input signals in response to a bias control signal. The control bias signal is generated at an output of a voltage divider coupled to the differential output of the differential inverter said bias control signal being indicative for a DC voltage of the of the differential output.

Abstract: A sample/hold circuit module. The sample/hold circuit module comprises a sample/hold circuit, an S/H controller, a pass transistor, and a high voltage generator. The sample/hold circuit comprises a capacitor and a sampling switch. The capacitor has a first electrode coupled to a first fixed voltage and a second electrode coupled to an output node of the sample/hold circuit module. The sampling switch comprises an output terminal coupled to the second electrode of the capacitor, an input terminal, and a control terminal. The S/H controller is coupled between the control terminal of the sampling switch and a second fixed voltage. The pass transistor has a sampling input terminal, an output terminal coupled to the input terminal of the sampling switch, and a control terminal. The high voltage generator is coupled between the control terminal of the pass transistor and the second fixed voltage.

Abstract: Logic included in an IC monitors values of parameters that may affect operation of the IC, such as, for example, supply voltage (VDD), junction temperature (TJUNC) and the frequency of a ring oscillator on the IC. In response to the monitored values, the logic in the IC changes, if necessary, one or more parameters such as VDD, processor frequency (FCLK), and/or cooling level to control the performance of the IC. Thus, the IC monitors its own environment and operating conditions and takes appropriate steps to control its environment and operating conditions to achieve certain goals.

Abstract: An integrated driver with improved load current sense capability includes a first transistor, a first amplifier, a second transistor, a third transistor, a second amplifier and a fourth transistor. The integrated driver allows for significantly better fault handling capability, provides accurate thermal and current sensing capability and reduces I/O pin count over prior designs.

Abstract: A low-power multi-level pulse amplitude modulation (PAM) driver, and a semiconductor device having the same, in which the multi (M)-level PAM driver includes a load unit, first and second current sources, a pair of first input transistors, a pair of second input transistors, and a current source controller, where M is an integer greater than 3. The load unit is electrically connected to an output terminal, and the first and second current sources respectively supply a first amount of current and a second amount of current to the load unit. The pair of first input transistors electrically connects the first current source and the load unit in response to a first bit signal, and the pair of the second input transistors electrically connects the second current source and the load unit in response to a second bit signal. The current source controller activates or deactivates one of the first and second current sources in response to the first and second bit signals.

Abstract: A drive circuit apparatus for use in generating a drive signal for energizing an actuator about a natural resonant frequency is disclosed. The circuit has a counter that generates a count sequence derived from a drive sense signal. Additionally, a demodulator is further coupled to the counter and generates a voltage level signal from the drive sense signal based on the count sequence. A digital to analog (D/A) converter is coupled to both the counter and demodulator. The D/A converter generates the drive signal in a substantially constant phase relationship with respect to the drive sense signal as derived from the voltage level signal and based on the count sequence. In addition, a method of generating a drive signal for energizing an actuator about a natural resonant frequency is provided.

Abstract: A frequency-divider circuit arrangement having a power supply, a first clock signal, a second clock signal, a first switch unit, a first capacitance which is connected downstream from the first switch unit is disclosed. A second switch unit is connected downstream from the first capacitance and is controlled by the second clock signal, a second capacitance is connected downstream from the second switch unit and is connected in parallel to the first capacitance, a clock-signal control unit, a capacitance discharge device and a capacitance discharge device control unit.

Abstract: A frequency divider circuit is disclosed with at least one push-pull divider with adjustable division ratio and a connected converter device. The circuit converts a clock signal delivered by a push-pull divider into a single-ended signal. A first and a second single-ended divider are connected to the output of the converter device, and a feedback path is provided, which is connected to the output of the push-pull divider and to the outputs of the first and of the at least one second single-ended divider, and which includes an evaluation circuit. This circuit has first and second inputs which are connected to the first and second single-ended dividers in such a way that a future state of the clock signal delivered by the single-ended divider in question can be supplied to the inputs of the evaluation circuit. The evaluation circuit evaluates states of the clock signals delivered by the first and second single-ended dividers, i.e.

Abstract: To oscillate and output multiphased triangular waves with a designed waveform shape, wave crest value, and phase relationship. This multiphased triangular wave oscillating circuit has two triangular wave generating circuits 10A and 10B for generating two phased triangular waves A and B with phases opposite each other, a middle point potential fixing element 20 that always fixes the middle point potential of the output voltage A and B of the two triangular wave generating circuits 10A and 10B at a fixed value, and a mode switching element 30 that instantly switches the output voltage generation mode (up-slope waveform mode/down-slope waveform mode) in the two triangular wave generating circuits 10A and 10B at a preset reference wave crest value level.

Abstract: The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

Abstract: Methods and apparatus are disclosed for protecting circuits from damages caused by elevated temperatures. Presented embodiments illustrate IC thermal protection circuits that shut down power delivery circuits when the circuit temperature reaches a predefined upper threshold and restart the circuit when the circuit cools down to a predefined lower threshold. Other embodiments provide soft shutdown and soft restart, where not only the temperature range between the shutdown and the restart is predetermined, but also the time between the start of a shutdown process and the complete shutdown is controllable.

Abstract: A control signal generating circuit used in a battery management system may stably generate a control signal. The control signal generating circuit includes a first signal line transmitting a first control signal having an on-level or an off-level, a second signal line transmitting a second control signal having an on-level or an off-level, and a third signal line transmitting a third control signal having an on-level or an off-level. In addition, the control signal generating circuit includes a transistor including a first electrode coupled to the first signal line and a second electrode applied with the off-level. The transistor electrically connects the first and second electrodes and converts the first control signal into a fourth control signal by being turned on based on the second and third control signals.

Abstract: Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.

Abstract: The invention relates to a method of estimating an intersection between at least two continuous signal representations (SR1, SR2) in a pulse width modulator, at least one of said continuous signal representations (SR1, SR2) being non-linear, said method comprising the step of providing an intersection estimate (CPE) between said at least two continuous signal representations on the basis of at least one iteration comprising at least one iterative call of a function describing said continuous signal representations (SR1, SR2) being non-linear and whereby said estimating of intersections are performed in a pulse width modulation modulator. According to an embodiment of the invention, a simple iterative call of the established continuous signal representation, e.g. an interpolation polynomial, will provide the desired intersection. It should be noted that the established estimate might be provided without any complicated root solving and avoiding division and even square root.

Abstract: An Schmitt trigger with electrostatic discharge protection includes a first PMOS, a second PMOS, a first NMOS, and a second NMOS, which are connected in series and each of which has a gate coupled to an input terminal. The drain of the second PMOS is coupled to an output terminal. The source of the first PMOS is coupled to a first voltage. The source of the second NMOS is coupled to a second voltage. The Schmitt trigger further includes a third PMOS, which has a gate coupled to the output terminal, a source coupled to the drain of the first PMOS, and a drain coupled to the second voltage through a poly-silicon resistor; and a third NMOS which has a gate coupled to the output terminal, a source coupled to the source of the first NMOS, and a drain coupled to the first voltage through a poly-silicon resistor.

Abstract: A flip-flop with an improved operating speed is disclosed. The flip-flop includes a switch unit, a latch unit and a reset controller. The switch unit transfers data to a first node in response to a clock signal. The latch unit latches the data apparent at the first node at a second node and outputs the data through an output node in response to the clock signal. The reset controller resets the output node in response to a reset control signal. The reset controller is connected between the second node and a first voltage and includes a transistor having a gate receiving the inverted form of the reset control signal.

Abstract: Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in broadband applications. These two stages, (1) buffer stage (or data amplifier stage) and (2) cross-coupled differential pair stage, are both very fast operating stages. This design does not incur any increased loading to previous or subsequent stages in a device. In addition, there is no increase in the total amount of current that is required.

Abstract: A shift down-level shifter used with a memory negative word line architecture prevents current flow between a positive bias voltage and a negative bias voltage when the input signal is at circuit ground. The output circuit of the shift down-level shifter comprises two transistors connecting a positive voltage and a negative voltage to the output terminal. A feed back circuit establishes a node voltage from which the output transistor coupling the negative voltage to the output terminal is controlled to be off when the input signal is at circuit ground and the output is a positive voltage, thus preventing current flow between the positive and negative bias voltages, which reduces power consumption.

Abstract: Mixer-systems comprising gain-blocks (1-4) and switches (5-8) have a flexibility depending upon their configuration (insight) and are made more flexible (basic idea) by supplying data input signals to the gain-blocks (1-4) and oscillation signals to the switches (5-6) for switching couplings between the gain-blocks (1-4). A switch (5-6) comprises a switch-transistor and a gain-block (1-4) either comprises a gain-block-transistor or comprises five gain-block-transistors for increasing the linearity of the mixer-system. The switches (5-6) have main electrodes which in the balanced situation are all coupled via four impedances (13-16) to the gain-blocks (1-4). In the single ended situation two main electrodes are coupled via two impedances (13,15,18,20) to the gain-blocks (1-4) and two others are coupled directly to the gain-blocks (1-4). By introducing further switches (7-8) parallel to the switches (5-6), harmonics can be suppressed.

Abstract: A method of switching on a voltage supply of a voltage domain of a semiconductor circuit includes switching, initially, a first switchable element, via which elements of the voltage domain are connected to a supply voltage of the semiconductor circuit, to a conductive state. The method includes switching, after a predetermined period of time, a second switchable element, via which elements of the voltage domain are connected to the supply voltage of the semiconductor circuit, to a conductive state. The driving capacity of the first switchable element is less than the driving capacity of the second switchable element.

Abstract: The invention relate to a power supply apparatus operating on the charge pump principle, comprising multiple regulators and three boosting capacitors switched in a switch matrix consisting of nine switches. A control circuit is provided capable of controlling the switches so that the charge pump is changed over between charging phases and discharge phases and which is capable of operating the charge pump in different voltage gains (1; 4/3; 3/2; 5/3; 2). The invention comprises furthermore a mode transitioning system. The selection of a mode is based on comparators capable of comparing signals from current regulation elements to predetermined voltages and then when the former attains the latter, changing over the charge pump into the corresponding other mode, wherein the predetermined voltages are selected so that the efficiency of the converter is optimized.

Abstract: Systems and methods for generating reference voltages are provided. A representative system comprises a resistor circuit; a first switch coupled between a first end of the resistor circuit and a first power source; a second switch coupled between the first end of the resistor circuit and a second power source; a third switch coupled to a second end of the resistor circuit; a fourth switch coupled to the second end of the resistor circuit; a first resistor coupled between the first end of the resistor circuit and the first switch; a second resistor coupled between the first end of the resistor circuit and the second switch; a third resistor coupled between the second end of the resistor circuit and the third switch; a fourth resistor coupled between the second end of the resistor circuit and the fourth switch; and a control circuit for controlling the switches.

Abstract: In one embodiment, a bandgap voltage reference generating circuit is configured to generate a reference voltage, and may comprise a first PN-junction whose base-emitter voltage (VBE) exhibits a curvature with respect to temperature, where a current conducted by the first PN-junction is proportional to absolute temperature (PTAT). The voltage reference generating circuit may also include a second PN-junction coupled to the first PN-junction. A control circuit coupled to the second PN-junction may be configured to inject a control current into the second PN-junction, where the control current has a negative to absolute temperature (NTAT) characteristic, the control circuit thereby operating to effectively eliminate a curvature with respect to temperature exhibited by the bandgap voltage.

Abstract: An amplifier is provided with an amplifier circuit including a plurality of first transistors having gates thereof coupled in common, a bias circuit including a plurality of second transistors that are coupled and outputs a bias voltage to the gates of the plurality of first transistors, and a selection circuit simultaneously controlling a number of first transistors to be coupled to the amplifier circuit and a number of second transistors to be coupled to the bias circuit based on the bias voltage.

Abstract: Methods and apparatus are provided for efficiently combining and filtering a plurality of input signals into a single combined output signal. M number of input signals are received, combined and filtered by a filter/combiner. The filter/combiner has a plurality of input stages for each input signal, and an output stage that combines the outputs of the input stages into the combined signal. The filter/combiner has a desired overall filter transfer function designed to filter signals having frequencies outside a passband and which passes the desired M input signals.