Abstract: A backlight module includes a frame, a light guide plate, a FPCB and a plurality of point light sources. The light guide plate has a light incident surface. The point light sources are electrically connected with one surface of the FPCB, each point light source having an emitting surface. The frame includes a plurality of connecting sidewalls encircling the light guide plate. An inner surface of the sidewall facing the light incident surface defines a plurality of elastic members thereon according to the point light sources. Each elastic member pushes the corresponding point light source towards the light guide plate, so as to have the final position of the emitting surface of each point light source come in contact with the light incident surface. The present backlight module has a highly light energy utilization rate.

Abstract: It is a light emitting apparatus having a light source, and also having a light guide element into which light from the light source is guided. The light source is accommodated in an accommodating portion formed a top-surface side of the light emitting element. In the bottom surface of the light guide element, a light emitting portion is formed at a portion which is located away from places directly below the light source and directly below an optical axis of the light source and which extends from a region placed obliquely frontwardly from the light source to a region placed laterally from the light source.

Abstract: A technique for extending the operating range of a flyforward converter to low input voltages. In one aspect, power converter includes a positive input supply rail and a negative input supply rail. A power converter input voltage is to be applied between the positive and negative input supply rails. A flyback energy transfer element having a flyback input winding and a forward energy transfer element having a forward input winding are also included. The flyback and forward input windings are coupled between the positive and negative input supply rails. Voltage control circuitry coupled to the forward energy transfer element is also included to reduce a voltage across the forward input winding, substantially to zero, when the power converter input voltage falls below a first threshold value.

Abstract: A flyback power converter includes a transformer having a first primary winding and a second primary winding. The first primary winding is coupled to the positive supply rail. The second primary winding is coupled to the negative supply rail. A transistor is connected in between the first primary winding and the second primary winding for switching the transformer. A control circuit is coupled to the transistor and the second primary winding to generate a switching signal for switching the transistor and regulating the output of the flyback power converter. A supplied capacitor is connected to the control circuit to supply the power to the control circuit. The second primary winding has a leakage inductor to store a stored energy when the transistor is on. A diode is coupled from the negative supply rail to the supplied capacitor. The stored energy of the leakage inductor is discharged to the supplied capacitor through the diode once the transistor is off.

Abstract: A direct current (DC) to DC converter is provided. The DC to DC converter includes: a transformer which comprises a primary winding which is connected in series with an input voltage and a secondary winding which generates induced current when the input voltage is applied to the primary winding; a switching part which is connected to the primary winding and performs a switching operation according to a predetermined control signal; a first delay part which delays an increasing rate of voltage between open nodes according to a turned-off state of the switching part and supplies a discharge current when the switching part is turned-on; and a second delay part which delays current flow in the switching part when the first delay part discharges the current when the switching part is turned-on.

Abstract: An alternating current (AC) to direct current (DC) high efficiency conversion architecture comprises an AC-to-DC conversion input stage operative to receive an instantaneous AC input, a DC output stage connected to the input stage through an AC link and operative to output a DC power to at least one customer, and an energy storage device used as an energy balancer between the changing power availability at the instantaneous AC input and the constant power requirements of the at least one customer, the energy storage device coupled to both input and output stages stage through the AC link.

Abstract: A voltage translator circuit and a method for operating the same. The voltage translator circuit includes (a) an input node, an output node, and a ground node; (b) a voltage divider circuit including a first and second resistors coupled in series between the input node and the ground node; (c) a start voltage circuit coupled to a first voltage and to the input node; (d) a transfer circuit coupled to the output node; and (e) a capacitive circuit having a first and second capacitive nodes. The first capacitive node is coupled to the voltage divider circuit. The second capacitive node is coupled (i) to the first voltage via the start voltage circuit, and (ii) to the output node via the transfer circuit. In response to the input node changing towards the first voltage, the start voltage circuit is capable of disconnecting the second capacitive node from the first voltage.

Abstract: EMC filter, for connection between a mains supply network and a mains-operated appliance to reduce conduction noise between said supply network and said appliance, comprising a voltage divider connected to said mains network, for generating a voltage lower than a voltage of said mains network; rectifying means, connected to an output of said voltage divider, for generating a DC voltage; and an electronic active circuit, supplied by said DC voltage, for absorbing a noise current transmitted between said supply network and said appliance.

Abstract: An engine control device, especially an engine control device having an internal by-pass, is disclosed. The universally applicable engine control device includes an integrated by-pass function. For this purpose, a housing includes chambers that are electrically insulated from one another and that are configured both to receive a respective power subunit, and, alternatively, to receive a continuous current-bearing element.

Abstract: A method and apparatus for adaptively configuring an array of voltage transformation modules is disclosed. The aggregate voltage transformation ratio of the adaptive array is adjusted to digitally regulate the output voltage for a wide range of input voltages. An integrated adaptive array having a plurality of input cells, a plurality of output cells, or a plurality of both is also disclosed. The input and output cells may be adaptively configured to provide an adjustable transformer turns ratio for the adaptive array or in the case of an integrated VTM, an adjustable voltage transformation ratio for the integrated VTM. A controller is used to configure the cells and provide digital regulation of the output. A converter having input cells configured as a complementary pair, which are switched out of phase, reduces common mode current and noise. Series connected input cells are used for reducing primary switch voltage ratings in a converter and enabling increased operating frequency or efficiency.

Abstract: The Lus, Semiconductor in this invention is characterized by replacing the static shielding diode (SSD) of traditional Enhancement Mode Field Effect Transistors (EMFETs) or Depletion Mode Field Effect Transistor (DMFETs) with polarity reversed (comparing with traditional SSD) SSD, Schottky Diode, or Zener Diode, or face-to-face or back-to-back coupled Schottky Diodes, Zener Diodes, Fast Diodes, or Four Layer Devices such as DIAC and TRIAC. With the proposed Power EMFETs or DMFETs of which the drain to source resistors (Rds) are quite low, high efficiency synchronous rectification may be achieved.

Abstract: One method of achieving the above subjects is by connecting a block member 14, which is connected to the side opposite to that of a semiconductor chip 11 having insulating substrates 12 and 13 connected to the top and bottom of the semiconductor chip 11, to a block member 15 across an laminated structure constituted by the semiconductor chip 11 and the insulating substrates 12 and 13.

Abstract: A DC-DC converter is provided which includes a switching element, a choke coil, a flywheel diode, an output capacitor, a diode, and an auxiliary transformer having primary and secondary windings. The primary winding and the switching element constitute a first series circuit such that one terminal of the primary winding is connected to the drain terminal of the switching element, and the secondary winding and the diode constitute a second series circuit such that one terminal of the secondary winding is connected to the cathode terminal of the diode, where the other terminal of the second winding is connected to the positive terminal of a DC power source, and the anode terminal of the diode is connected to the negative terminal of the DC power source.

Abstract: An inverter for use in connecting a DC power source to the utility grid includes a single DC-AC conversion stage, maximum (source) power tracking, and current control based on feed-forward compensation as a function of input power voltage error, rectified utility line voltage, and a scaled inverse of RMS utility line voltage. Various topologies of the inverter power stage are developed for bi-directional power-flow operation after those developed for unidirectional power-flow operation. Various embodiments also include over-voltage protection, over-current protection, under-voltage protection, over-temperature protection, and stand-by battery with battery management control, while still others are adapted for a multiple-channel front-end distributed power system with distributed maximum power tracking for serving as a single DC power source input to the inverter system downstream with controllers, emergency or auxiliary loads, and alternative current feedback control systems.

Abstract: A first variable resistor (5) is connected between a first terminal (7) and a third terminal (9) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the first terminal (7) and the third terminal (9). A second variable resistor (6) is connected between the third terminal (9) and a second terminal (8) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the third terminal (9) and the second terminal (8). Given pulse voltages are applied between the first terminal (7) and the third terminal (9) and between the third terminal (9) and the second terminal (8) to reversibly change the resistance values of the first and second variable resistors (5, 6), thereby recording one bit or multiple bits of information.

Abstract: A nonvolatile memory device comprises memory cells, each including a variable resistor element for storing data in accordance with a change in electrical resistance due to application of electrical stress, and a thermal diffusion barrier on a thermal diffusion path, wherein the thermal diffusion barrier is capable of suppressing a change in resistance of the variable resistor element due to heat diffusion from one of two adjacent memory cells separated by an electrical insulator from each other where heat is generated by applying the electrical stress for changing the electrical resistance of the variable resistor element to the other memory cell via the thermal diffusion path including an electrically conductive wiring material higher in thermal conductivity than that of the electrical insulator.

Abstract: A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying a corresponding current to the memory element.

Abstract: Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.

Abstract: A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

Abstract: An SRAM device including first and second access transistor composed of an N channel MOS transistor, first and second drive transistors composed of the N channel MOS transistor, and first and second P channel thin film transistor functioning as a pull-up device, comprises: a well formed by implanting a dopant of a conductivity an opposite to that of a semiconductor substrate in the semiconductor substrate; a first active region in which a drain of the first access transistor and a drain of the first drive transistor are formed; a second active region in which a drain of the second access transistor and a drain of the second drive transistor are formed; and a groove line for isolating the first active region and the second active region from each other, wherein the first access transistor, the first drive transistor, the first thin film transistor are formed in point-symmetrical relation with the second access transistor, the second drive transistor, and the second thin film transistor based on a center of the

Abstract: A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter has an enable node to which a read signal is applied and is configured to generate an output signal that is the complement of an input signal in response to an active read signal. The SRAM cell further includes an access transistor having a first node coupled to the output of the tri-state inverter and having a second node coupled to the digit line. The access transistor is configured to couple the first and second nodes in response to an active access signal applied to its gate.

Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

Abstract: It is made possible to prevent the recording layer in the TMR element from assuming the intermediate state as perfectly as possible even if writing into the MRAM is conducted, as heretofore described. A write control method for a magnetoresistive random access memory including: applying a pulsative first magnetic field substantially parallel to the axis of easy magnetization of the recording layer and a pulsative second magnetic field substantially parallel to the axis of hard magnetization to the recording layer so as to cause a period of the pulsative first magnetic field and a period of the pulsative second magnetic field to overlap each other; and applying a pulsative third magnetic field having substantially the same direction as the pulsative first magnetic field to the recording layer at least once after applying the pulsative first magnetic field to the recording layer.

Abstract: A semiconductor memory device is provided with a memory array including memory cells arranged in rows and columns; and a sense amplifier circuit. Each of the memory cells includes at least one magnetoresistive element storing data, and an amplifying member used to amplify a signal generated by a current through the at least one magnetoresistive element. The sense amplifier circuit identifies data stored in the at least one magnetoresistive element in response to an output signal of the amplifying member.

Abstract: In an MRAM of the invention, a curved region (206) is formed in a bit line (202), and this curved region (206) is in bent shape, with a TMR element (203) serving as a center, in this case, in rough U shape (in the illustrated example, in roughly inverted U shape). The bit line (202) in which the curved region (206) is formed includes the TMR element (203) in a space formed by the curved region (206). Thanks to such relatively simple construction, this construction realizes a highly reliable MRAM which ensures that power is substantially saved during data writing into a memory cell while meeting requirements for further miniaturization of the device.

Abstract: A phase change memory device includes a semiconductor substrate which includes a plurality of phase change memory cells, a plurality of local bit lines extending over the semiconductor substrate, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells, and a plurality of global bit lines extending over the plurality of local bit lines, each of the plurality of global bit lines being selectively coupled to the plurality of local bit lines. The plurality of global bit lines are located at two or more different wiring line levels over the semiconductor substrate.

Abstract: A method and system for probing FCode in problem state memory. A PCI device is detected from a PCI-PCI bridge node included in a device tree. A child node for the detected PCI device is created in problem state memory. The active package is switched to the child node, and the processor switches from running in privileged mode to running in problem mode. FCode of an FCode driver in the PCI device is probed. Data, properties and methods generated in response to the probe are created in problem state memory. After the probe is complete, the active package is switched to the parent node of the child node, and the processor switches back to running in privileged mode.

Abstract: Secondary electron injection (SEI) is used for programming NVM cells having separate charge storage areas in an ONO layer, such as NROM cells. Various combinations of low wordline voltage (Vwl), negative substrate voltabe (Vb), and shallow and deep implants facilitate the process. Second bit problems may be controlled, and retention and punchthrough may be improved. Lower SEI programming current may result in relaxed constraints on bitine resistance, number of contacts required, and power supply requirements.

Abstract: A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.

Abstract: A method for protecting an integrated circuit, including at least one non-volatile memory, including the steps of detecting a possible disturbance in the flow of a program executed by the integrated circuit, modifying the value of a digital variable in a volatile storage element in case of a disturbance detection and, in a way independent in time from the detection, intervening upon the non-volatile memory according to the value of said variable.

Abstract: A method capable of improving endurance of memory includes detecting whether a record cell is the last non-programmed record cell of a set of record cells that includes the record cell. The method includes erasing the corresponding set of multi-time programmable memory blocks and erasing the set of record cells, if the record cell is the last non-programmed record cell of the set of record cells that includes the record cell. The method further includes programming the record cell corresponding to a first non-programmed record cell in the set of record cells if the non-programmed record cell is not the last non-programmed record cell of the set of record cells.

Abstract: On a write-once-type recording medium 10, there are provided: a definite defect management area 13 to definitely record therein defect management information; and a plurality of temporary defect management areas 14A, 14B, and 14C to temporarily record therein the defect management information. If the recording medium 10 is not yet finalized, every time the defect management information is updated, the updated defect management information is recorded into any one of the plurality of temporary defect management areas. Moreover, a status information recording area 15 is provided on the recording medium 10, and status information for indicating the temporary defect management area in which there is the defect management information recorded at last is recorded into the status information recording area 15. By referring to the status information, it is possible to quickly specify the defect management information recorded at last.

Abstract: The invention describes the method for regrouping data read from multi-sector pages inside a memory chip. As a result, garbage collection operation time greatly reduces and overall system performance increases. Architectural features include the ability to selectively transfer individual data sectors of a page between on-chip registers and the ability to realign data sectors within a register.

Abstract: A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells.

Abstract: Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.

Abstract: A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

Abstract: A program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of states. The program method includes programming memory cells selected to have one of the states by using multi-bit data; detecting programmed memory cells within a predetermined region of a threshold voltage distribution where the programmed memory cells having the respective states are distributed, wherein the predetermined region of the respective states is selected by one of a first verify voltage and a read voltage and a second voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and programming the detected memory cells to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

Abstract: A reference fail bit verification circuit includes a fail bit counter which counts a number of fail bits to generate a first counting signal and a second counting signal, the first counting signal and the second counting signal being activated in response to the number of fail bits counted. The circuit also includes a bit verification block which generates a reference bit verification signal that is activated in response to a transition of the first counting signal and the second counting signal, wherein the reference bit verification signal is activated in response to at least one of the activation of the first counting signal in a first mode, and the activation of the second counting signal in a second mode.

Abstract: A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

Abstract: A programming method of a flash memory device having a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The programming method includes programming selected memory cells using multi-bit data to have one of the states; detecting programmed memory cells arranged within a predetermined region of threshold voltage distribution each corresponding to at least two of the states, wherein predetermined regions of the respective at least two states are selected by one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and simultaneously programming detected memory cells of the at least two states to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

Abstract: A memory cell includes transistors and two read ports. Each read port is configured to be connected to a read line. The memory cell is configured such that in a read operation of the memory cell an information stored in the memory cell is readable by a differential reading including an evaluation of an electric current between the two read ports.

Abstract: A semiconductor memory device arranged for minimizing the duration of time required for conducting a batch verify action and thus speeding up a buffer write action is provided. The device which conducts a write action to memory cells in an address area, a batch verify action for collectively conducting verify action for a plurality of addresses, and repeats the batch verify action and the write action, comprises a detecting means for detecting whether or not each address contains an unwritten memory cell, and conducts a verify action at least at a part of the batch verify action excluding at least a part of addresses judged not to contain unwritten memory cells by the verify action at one or more cycles before.

Abstract: Each of first and second differential amplifiers has a function of increasing a bias current in response to the activation of a drivability control signal. A first driving circuit connects an output node to a high power supply line in response to the activation of an output signal of the first differential amplifier, and connects the output node to a low power supply line in response to the activation of an output signal of the second differential amplifier. Only during the activation period of the drivability control signal, a second driving circuit connects the output node to the high power supply line in response to the activation of the output signal of the first differential amplifier, and connects the output node to the low power supply line in response to the activation of the output signal of the second differential amplifier.

Abstract: Methods and systems for preventing permanent data loss due to a single failure in an array of storage devices are described. In particular, a defective memory block is detected and data that was on the now defective memory block is reconstructed using backup data in the array. The reconstructed data is stored in a replacement memory block, without requiring the rewriting of data in non-defective memory blocks. The information mapping the defective memory block to the replacement memory block may be stored as metadata on a storage device.

Abstract: Apparatus for repairing one or more shorted memory cells in a memory circuit includes control circuitry. The control circuitry is operative in one of at least a first mode and a second mode. In the first mode, the control circuitry is operative to apply a first signal to a selected memory cell in the memory circuit for reading a logic state of the selected memory cell and to determine whether or not the selected memory cell is shorted. In the second mode, the control circuitry is operative to apply a second signal to a selected memory cell which has been determined to be shorted for initiating a repair of the selected memory cell, the second signal being greater in magnitude than the first signal.

Abstract: Structures and methods are disclosed for operating Balanced Sense Amplifier Circuits. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first and second transistors comprise (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively. The structure also comprises a control circuit, which is electrically coupled to the first and second transistor bodies. The structure further comprises a testing circuit, which is electrically coupled to the control circuit and the first and second transistors of the reading circuit. The testing circuit is capable of determining whether strengths of the first and second transistors are different. In response to the testing circuit determining that the strengths of the first and second transistors are different, the control circuit is capable of adjusting the voltage of the first transistor body.

Abstract: Disclosed is a semiconductor memory device includes two equalizing elements, each connected between a pair of bit lines and being separately subjected to on/off control by respective control signals. When performing a test, one of the control signals is kept HIGH and the other of the control signal is kept LOW during a precharge period, and activation/deactivation of the two equalizing elements is separately controlled. A failure such as a defect in one of the two equalizing elements subjected to the on/off control by the control signal can be thereby detected.

Abstract: A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.

Abstract: A sense amplifier circuit for sensing a logic state of a selected memory cell in a memory circuit includes a precharge circuit and a latch circuit. The precharge circuit is adapted for connection to a pair of complementary bit lines corresponding to the selected memory cell and is operative to selectively drive the pair of complementary bit lines to a first voltage in response to a first control signal. The latch circuit is adapted for connection to the pair of complementary bit lines. The sense amplifier circuit further includes a replication circuit adapted for connection to the pair of complementary bit lines. The replication circuit is operative to selectively transfer a voltage representative of a logic state on a first bit line of the pair of complementary bit lines to a second bit line of the pair of complementary bit lines in response to at least a second control signal.