Abstract: An improved way to apply tensile or compressive stress to one or more transistors on a semiconductor device is described. A portion of the tensile or compressive stress liner may be removed or modified such that a reduced amount of stress, or even no stress, is applied above the transistor gate. This may cause edges of the stress liner to be adjacent to and on either side of the channel, thus, increasing the stress effect. To produce this stress liner structure, the stress liner may be applied and then a portion of the stress liner is modified to reduce the stress in that portion, such as through ion implantation. The stress liner portion may be modified to have a reduced stress by, for example, implanting certain ions such as germanium or xenon ions therein.

Abstract: The invention relates to a method of manufacturing a semiconductor strained layer and to a method of manufacturing a semiconductor device (10) in which a semiconductor body (11) of silicon is provided, at a surface thereof, with a first semiconductor layer (1) having a lattice of a mixed crystal of silicon and germanium and a thickness such that the lattice is substantially relaxed, and on top of the first semiconductor layer (1) a second semiconductor layer (2) is provided comprising strained silicon, in which layer (2) a part of the semiconductor device (10) is formed, and wherein measures are taken to avoid reduction of the effective thickness of the strained silicon layer (2) during subsequent processing needed to form the semiconductor device (10), said measures comprising the use of a third layer (3) having a lattice of a mixed crystal of silicon and germanium.

Abstract: A method of forming a phase change material layer includes preparing a substrate having an insulator and a conductor, loading the substrate into a process housing, injecting a deposition gas into the process housing to selectively form a phase change material layer on an exposed surface of the conductor, and unloading the substrate from the process housing, wherein a lifetime of the deposition gas in the process housing is shorter than a time the deposition gas takes to react by thermal energy.

Abstract: A method of manufacturing a coreless package substrate together with a conductive structure of the substrate is disclosed. The method can produce a coreless package substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless package substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A complementary metal oxide semiconductor image sensor and a method for fabricating the same are disclosed, wherein a width of a depletion area of a photodiode is varied by variably applying a back bias voltage to a semiconductor substrate without using any color filter, thereby preventing a back bias voltage from influencing a transistor formed on the outside of a photodiode in a CMOS image sensor sensing optical color sensitivity of light rays irradiated to the photodiode.

Abstract: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.

Abstract: An image display apparatus includes a front substrate, and a rear substrate opposed to the front substrate. The front substrate has phosphor layers, resistor layers provided between the phosphor layers, a metal-back layer divided into metal-back segments covering the phosphor layers and resistor layers at least in part, and spaced apart by gaps Gx in a first direction intersecting at right angles with a scanning direction and by gaps Gy in a second direction identical to the scanning direction, and a voltage-applying portion which applies a voltage on the metal-back segments. Rx(100)/Rx(1)<Ry(100)/Ry(1) is satisfied, where Rx(V) is a resistance between any two metal-back segments on the sides of a gap Gx, respectively, which is the function of voltage V[V], and Rx(V) is a resistance between any two metal-back segments on the sides of a gap Gy, respectively, which is the function of the voltage V[V].

Abstract: A memory cell comprises a dielectric layer and a phase change material. The dielectric layer defines a trench having both a wide portion and a narrow portion. The narrow portion is substantially narrower than the wide portion. The phase change material, in turn, at least partially fills the wide and narrow portions of the trench. What is more, the phase change material within the narrow portion of the trench defines a void. Data can be stored in the memory cell by heating the phase change material by applying a pulse of switching current to the memory cell. Advantageously, embodiments of the invention provide high switching current density and heating efficiency so that the magnitude of the switching current pulse can be reduced.

Abstract: For improving efficiency of a power device having an exposed surface capable of radiating energy, a shielding layer is disposed in between the exposed surface and a conductive layer. The shielding layer causes at least a portion of the energy to be directed back into the power device, thereby substantially preventing the energy from inducing eddy currents in the conductive layer. The conductive layer is fabricated from a metal foil for compliance with electromagnetic energy leakage regulations.

Abstract: A partially-depleted silicon-on-insulator (SOI) field-effect transistor (FET) with a reduced off-current is described, as well as methods for manufacturing. This may be accomplished by providing an SOI FET having a lower body potential than in previous SOI FETs. To lower the body potential, carrier traps may be formed mainly in the neutral source and drain regions of the SOI FET by extra over-etching of the gate spacers and the underlying silicon layer.

Abstract: A spacer structure contains a carbon-containing oxynitride film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxynitride film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxynitride film.

Abstract: Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material.

Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

Abstract: A semiconductor device is formed with a lower field plate (32) and optional lateral field plates (34) around semiconductor (20) in which devices are formed, for example power FETs or other transistor or diode types. The semiconductor device is manufactured by forming trenches with insulated sidewalls, etching cavities (26) at the base of the trenches which join up and then filling the trenches with conductor (30).

Abstract: A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

Abstract: An imager pixel utilizing a silicon-on-insulator substrate, a photodiode in said substrate below the buried oxide, and a dual contact to said photodiode and methods of forming said imager pixel. The photodiode has an increased fill factor due to its increased size relative to the pixel.

Abstract: A CMOS image sensor and a method for fabricating the same is disclosed, to improve reliability of a driving part transistor and to improve an output voltage of a photodiode, which includes a semiconductor substrate defined as a photodiode transistor region and a driving part transistor region; a first gate insulating layer on the photodiode transistor region of the semiconductor substrate; a second gate insulating layer on the driving part transistor region of the semiconductor substrate, wherein the second gate insulating layer is thicker than the first gate insulating layer; and gate electrodes on the respective first and second gate insulating layers.

Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.

Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.

Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.

Abstract: Tunneling magnetoresistive (TMR) electrical lapping guides (ELG) are disclosed for use in wafer fabrication of magnetic sensing devices, such as magnetic recording heads using TMR read elements. A TMR ELG includes a TMR stack comprising a first conductive layer, a barrier layer, and a second conductive layer of TMR material. The TMR ELG also includes a first lead and a second lead that connect to conductive pads used for applying a sense current to the TMR ELG in a current in plane (CIP) fashion. The first lead contacts one side of the TMR stack so that the first lead contacts both the first conductive layer and the second conductive layer of the TMR stack. The second lead contacts the other side of the TMR stack so that the second lead contacts both the first conductive layer and the second conductive layer of the TMR stack.

Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.

Abstract: A trench step channel cell transistor and a manufacture method thereof are disclosed. The transistor could be applied to increase the channel length thereof. The transistor comprises a step silicon layer formed by a selective growth, while the step silicon layer is located above the active area of the transistor.

Abstract: The present invention provides for a low-temperature method to crystallize a silicon-germanium film. Metal-induced crystallization of a deposited silicon film can serve to reduce the temperature required to crystallize the film. Increasing germanium content in a silicon-germanium alloy further decreases crystallization temperature. By using metal-induced crystallization to crystallize a deposited silicon-germanium film, temperature can be reduced substantially. In preferred embodiments, for example in a monolithic three dimensional array of stacked memory levels, reduced temperature allows the use of aluminum metallization. In some embodiments, use of metal-induced crystallization in a vertically oriented silicon-germanium diode having conductive contacts at the top and bottom end is be particularly advantageous, as increased solubility of the metal catalyst in the contact material will reduce the risk of metal contamination of the diode.

Abstract: Parallel fins or ridges are arranged on a main surface of a semiconductor substrate. Source/drain regions are provided at top and bottom portions of said fins, and wordlines comprising gate electrodes are arranged in interspaces between neighboring fins. The channels of individual memory cells are directed vertically with respect to the substrate surface.

Abstract: A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material element is positioned over the first electrode, and a phase change material layer is formed over the first electrode and surrounding the insulating material element such that the phase change material layer has a lower surface that is in electrical communication with the first electrode. The memory element also has a second electrode in electrical communication with an upper surface of the phase change material layer.

Abstract: Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.

Abstract: A nonvolatile memory device and a method of fabricating the same are disclosed. The method includes forming a tunnel oxide film and a conductive film for a floating gate on a semiconductor substrate; nitriding the top surface of the conductive film for a floating gate; oxidizing the nitrided top surface of the conductive film for a floating gate that is nitrided, forming an ONO film comprising a lower oxide film, a nitride film and an upper oxide film sequentially laminated on the surface-modified conductive film for a floating gate to complete formation of the dielectric film; and forming the conductive film for a control gate on the dielectric film.

Abstract: A semiconductor device includes an interconnection layer including adjacent two interconnection lines extending adjacent to each other. A plurality of contact plugs pass through the space between the adjacent two interconnection lines. The adjacent two interconnection lines have different distances therebetween due to a concave-and-convex surface of the sidewall of the adjacent two interconnection lines.

Abstract: A semiconductor device, including a semiconductor region of the first conduction type which is formed on a semiconductor substrate; a gate electrode at least part of which is present within a trench which is selectively formed in part of the semiconductor region, and an extended top end portion of which is formed to have a wide width via a stepped portion; a gate insulating film which is formed between the trench and the gate electrode along a wall surface of the trench; a base layer of the second conduction type which is provided on the semiconductor region via the gate insulating film so as to enclose a side wall except a bottom portion of the trench; a source region of the first conduction type which is formed adjacent to the gate insulating film outside the trench in the vicinity of a top surface of the base layer; and an insulating film which is formed at least partially between a bottom surface of the top end portion and a top surface of the source region and which is formed so as to have a film thickne

Abstract: A lateral double-diffused metal oxide semiconductor (LDMOS) device is disclosed. The LDMOS device comprises a gate region and a body region under the gate region. The LDMOS device includes an enhanced drift region under the gate region. The enhanced drift region touches the body region. By designing the device such that the enhanced drift region overlaps and compensates the lateral tail of the body region of the LDMOS transistor, the Ron*area product is reduced. Accordingly, the on-resistance is significantly reduced while minimally affecting the breakdown voltage of the device.

Abstract: A power MOSFET package is disclosed. The power MOSFET package includes a leadframe having first and second die pads insulated one from the other, the first die pad being coupled to a first drain lead and the second die pad being coupled to a second drain lead. A first MOSFET device has a drain contact coupled-to the first die pad, a gate contact coupled to a first gate lead, and a source contact coupled to the second die pad. A second MOSFET device has a drain contact coupled to the second die pad, a gate contact coupled to a second gate lead, and a source contact coupled to a source lead. An encapsulant substantially encapsulates the leadframe, the first and second MOSFET devices and portions of the first and second gate leads, the first and second drain leads, and the source lead.

Abstract: A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.

Abstract: The semiconductor device includes an active region, a stepped recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The stepped recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the stepped recess channel region. The gate structure is disposed over the stepped recess channel region of the gate region.

Abstract: Provided are an SOI substrate, memory devices using the SOI substrate, and a method of manufacturing the same. The SOI substrate includes a thermal oxide layer pattern which minimizes leakage current but allows back biasing and heat dissipation through the substrate. The SOI substrate also includes a metal-gettering site to further minimize leakage current.

Abstract: Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel diffusion region and terminates as far as practical beyond the edge without making undesirable electrical contact with any other features of the integrated circuit design, and without overlying any other diffusion regions. A compressively strained cap layer overlies the P-channel diffusion. In yet another aspect, roughly described, a gate conductor crosses an N-channel diffusion and extends by as short a distance as practical before terminating or turning. A tensile strained cap material overlies the N-channel diffusion.

Abstract: A high reliability semiconductor display device is provided. A semiconductor layer in the semiconductor display device has a channel forming region, an LDD region, a source region, and a drain region, and the LDD region overlaps a first gate electrode, sandwiching a gate insulating film.

Abstract: An electrostatic discharge protection structure disposed in a peripheral area of a display panel is electrical connected to a wire of a display area of the display panel and a short ring of the peripheral area. The electrostatic discharge protection structure comprises a first path having a first resistance, and a second path having a second resistance. The first path and the second path are parallel connected between the wire and the short ring, wherein the first resistance is lower than the second resistance.

Abstract: In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of manufacturing the dual gate insulation layer includes, forming the device isolation layer so that an uppermost part thereof is positioned lower than an upper surface of the first and second active regions, before forming a gate insulation layer corresponding to each of the first and second active regions. Whereby, it is be effective till a portion of trench sidewall utilized as the active region, to increase a cell current of the active region and to prevent a stringer caused by a stepped coverage between the active region and a field region and a dent caused on a boundary face between the active region and the field region.

Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.

Abstract: A MOS semiconductor device includes a substrate having a first region with a Si(110) surface and a second region with a Si(100) surface, a p-channel MOSFET formed in the first region, and an n-channel MOSFET formed in the second region. The p-channel MOSFET including a first silicide layer formed on source/drain regions, and containing N atoms at an areal density of 8.5×1013 to 8.5×1014 cm?2, and F atoms at an areal density of less than 5.0×1012 cm?2. The n-channel MOSFET including a second silicide layer formed on a source/drain regions, and containing F atoms at an areal density of not less than 5.0×1013 cm?2.

Abstract: A memory cell includes a first electrode, a second electrode, a layer of phase change material extending from a first contact with the first electrode to a second contact with the second electrode, and a sidewall spacer contacting the second electrode and a sidewall of the layer of phase change material adjacent to the second contact.

Abstract: A method of manufacturing a semiconductor device includes forming a pillar-shaped active region by etching a portion of a semiconductor substrate, forming a blocking film selectively exposing a sidewall of a lower portion of the pillar-shaped active region, and forming a bit-line selectively on the exposed sidewall of the lower portion of the pillar-shaped active region.

Abstract: An ambipolar nanotube field effect transistor is converted to a unipolar nanotube field effect transistor by providing a carrier-trapping material such as oxygen molecules for the nanotube such as by adsorption or by providing a layer of material containing the carrier-trapping material adjacent to the nanotube.

Abstract: A locking device to lock a six degree of freedom positioned body is disclosed. The device has a clamping bushing to clamp against a surface of a bore extending through the body, a clamping ring to expand when subject to a compression force, and a lock actuator configured to cause the force to be applied so that the clamping ring expands against the clamping bushing so as to cause the clamping bushing to be pushed into contact against the surface. An adjustment mechanism to adjust a position of a body is also disclosed. The mechanism has an intermediate body on which the body is mounted and first and second adjustment elements to adjust a position of the intermediate body with respect to a fixed location in first and second directions, respectively, so that adjustment of the intermediate body is effected substantially in a plane defined by the directions.

Abstract: Doped silicon carbide structures, as well as methods associated with the same, are provided. The structures, for example, are components (e.g., layer, patterned structure) in MEMS structures. The doped silicon carbide structures may be highly conductive, thus, providing low resistance to electrical current. An in-situ doping process may be used to form the structures. The process parameters can be selected so that the structures have a low residual stress and/or low strain gradient. Thus, the structures may be formed having desired dimensions with little (or no) distortion arising from residual stress and/or strain gradient. The high conductivity and mechanical integrity of the structures are significant advantages in MEMS devices such as sensors and actuators.

Abstract: Techniques and device designs associated with devices having magnetic or magnetoresistive tunnel junctions (MTJs) configured to operate based on spin torque transfer switching. On-plug MTJ designs and fabrication techniques are described.

Abstract: The barrier region for isolating one or more dark regions of the pixel array of an image sensor from the active array or from the peripheral circuitry includes N-well pixel isolation region. The N-well pixel isolation region includes at least one N-well implant or at least one N-well stripe. The N-well pixel isolation region is adjacent the pixel cells which comprise the dark region. The addition of the N-well in the barrier region improves the isolation properties of the barrier region by reducing or eliminating the neutral P? EPI region in the barrier pixel area below the N-well isolation region.

Abstract: A thermionic flat electron emitter has an emitter arrangement with an emitter plate having slits therein that produce serpentine current paths. The emitter arrangement has a structure that, in operation, causes the electron density of the emitted electrons to be lower in the central region of the emitter plate than in a region adjoining the central region.

Abstract: In a method to form a DMOS or bipolar transistor, two epitaxial silicon layers are grown over a silicon substrate instead of the typical one low-resistivity epitaxial layer. The bottom epitaxial layer has a relatively high resistivity of, for example 10 ohms-cm, while the upper epitaxial layer, acting as a drift region, may have a conventional low resistivity such as 3 ohms-cm. The bottom epi layer, being less doped than the upper epi layer, causes a wider and deeper depletion region to occur for a given drain or collector voltage, as compared to a depletion region where the entire epitaxial layer is formed of the upper epitaxial layer composition. Therefore, the parasitic capacitor's depletion region will be wider and deeper when employing the bottom epitaxial layer. The wider and deeper depletion region in the lower epitaxial layer lowers the overall parasitic capacitance value. This improves the switching speed of the transistor.