Abstract: A The semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge termination zone has a junction termination extension (JTE) region of the second conductivity type, the region having portions extending away from the well region and a number of field limiting rings of the second conductivity type disposed at the upper surface in the junction termination extension region.

Abstract: A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place.

Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening. The sidewall can extend from the surface towards the bottom of the opening. The process can also include forming a layer over the semiconductor layer and within the opening, and removing a part of the first layer from within the opening. After removing the part of the layer, a remaining portion of the layer may lie within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the layer may be spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the first layer.

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract: Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth A between an array trench depth and a periphery trench depth. One etching method creates a trench delta depth utilizing a single dry etch step, while two other etching methods create a trench A depth by utilizing three dry etch steps.

Abstract: One aspect of the invention provides an integrated circuit (IC). The IC comprises transistors and contact fuses. The contact fuses each comprise a conducting layer, a frustum-shaped contact has a narrower end that contacts the conducting layer and a first metal layer that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink that is located over and contacts the first metal layer.

Abstract: A fuse corner pad is part of an integrated circuit that includes a built-in fuse contact and a plurality of auxiliary pads. The fuse contact is a conductive metallic or metalloid structure that is connected to a fuse element. The fuse contact and fuse element are used inside of the fuse corner pad for programmability (e.g., for security) and/or adjustment (e.g., trimming) of analog and/or digital signals. The fuse contact and fuse element are not required to be bonded to an external electrical connection (such as, a pin or ball). The auxiliary pads provide a variety of functional or non-functional applications, such as testing, probing, programming, and/or circuit adjustment.

Abstract: An inductive device including an inductor coil located over a substrate, at least one electrically insulating layer interposing the inductor coil and the substrate, and a plurality of current interrupters each extending into the substrate, wherein a first aggregate outer boundary of the plurality of current interrupters substantially encompasses a second aggregate outer boundary of the inductor coil.

Abstract: A first opening portion for via hole opening is formed above an electrode groove and a second opening portion for via hole opening for connecting with wiring layer is formed on interlayer insulation film at a position corresponding to the top portion of wiring layer provided out of a capacitor formation area. At this time, the diameter of the opening of the first opening portion is set larger than the second opening portion. If the diameter of the second opening portion is 0.36 ?m, the diameter of the opening of the first opening portion is set to 0.38 ?m.

Abstract: A transistor apparatus includes a silicon substrate and a barrier structure extending substantially from generally adjacent the silicon substrate to a locus displaced from the silicon substrate. The barrier structure generally surrounds a volume containing connection loci for the transistor apparatus and a buried layer in a silicon medium. The connection loci and the buried layer occupy a space generally presenting a first lateral expanse generally parallel with the silicon substrate. The volume presents a second lateral expanse generally parallel with the silicon substrate. The second lateral expanse is greater than the first lateral expanse within a predetermined distance of the substrate.

Abstract: A varactor on a substrate is provided. The varactor comprises a bottom electrode, an upper electrode, a first dielectric layer and a conductive layer. The bottom electrode has several doped regions arranged in the substrate as an array with several rows and several columns, wherein the doped regions in adjacent columns are arranged alternatively. The upper electrode is located over the substrate and the upper electrode is composed of several electrode locations and has several openings, wherein each opening exposes the corresponding doped region. Furthermore, each electrode location is surrounded by three doped regions. The first dielectric layer is located between the substrate and the upper electrode. The conductive layer is located over the upper electrode, wherein the conductive layer and the upper electrode are isolated from each other and the conductive layer and the doped regions are electrically connected to each other.

Abstract: A semiconductor device and method thereof. The example method may include forming a semiconductor device, including forming a first layer on a substrate, the first layer including aluminum nitride (AlN), forming a second layer by oxidizing a surface of the first layer and forming a third layer on the second layer, the first, second and third layers each being highly oriented with respect to one of a plurality crystallographic planes. The example semiconductor device may include a substrate including a first layer, the first layer including aluminum nitride (AlN), a second layer formed by oxidizing a surface of the first layer and a third layer formed on the second layer, the first, second and third layers each being highly oriented with respect to one of a plurality crystallographic planes.

Abstract: The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are formed within the memory array region, with such paired transistors sharing a source/drain region corresponding to a bitline contact location, and having other source/drain regions corresponding to capacitor contact locations. A peripheral transistor gate is formed over the peripheral region. Electrically insulative material is formed over the peripheral transistor gate, and also over the bitline contact location. The insulative material is patterned to form sidewall spacers along sidewalls of the peripheral transistor gate, and to form a protective block over the bitline contact location. Subsequently, capacitors are formed which extend over the protective block, and which electrically connect with the capacitor contact locations. The invention also includes semiconductor constructions.

Abstract: The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced. Furthermore, because the etching selection ratio of SiOC to SiCN as well as that of SiOC to SiC are small, if SiCN or SiC is used as the etching stopper film, the surface of the metal interconnection layer may be oxidized at the time of photoresist removal, which gives rise to a problem of high contact resistance.

Abstract: A technique for improving the quality factor of an inductor includes increasing a cross-sectional area of the inductor by increasing a vertical dimension associated with the inductor. An apparatus includes an inductor formed partially in a first integrated circuit die and formed partially in at least a second integrated circuit die. The inductor may be formed partially in at least one interconnect structure between the first integrated circuit die and the second integrated circuit die. In at least one embodiment of the invention, the inductor is self-shielding and is configured to generate a magnetic field in response to a current flowing through coupled conductor portions of the self-shielding inductor. The magnetic field of the self-shielding inductor is substantially confined to a core region of the self-shielding inductor.

Abstract: An embedded integrated circuit package system is provided forming a first conductive pattern on a first structure, connecting a first integrated circuit die on the first conductive pattern, forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern, forming a channel in the substrate forming encapsulation, and applying a conductive material in the channel.

Abstract: A semiconductor device includes a plurality of semiconductor chips and a memory device. The semiconductor chips are provided in a package. Each of the semiconductor chips includes a memory cell array having memory cells which stores data, an output buffer which outputs data read from the memory cell array to an exterior of the semiconductor chip and a control circuit which controls driving power of the output buffer. The memory device stores the number of semiconductor chips provided in the package. The control circuit controls the driving power according to the number of semiconductor chips stored in the memory device.

Abstract: Power semiconductor module comprising surface-mountable flat external contact areas and method for producing the same The invention relates to a power semiconductor module (1) comprising surface-mountable flat external contact areas (3) and a method for producing the same. The top sides (10) of the external contacts (3) form an inner housing plane (11), on which at least one power semiconductor chip (6) is fixed by its rear side (8) on a drain external contact (13). An insulation layer (14) covers the top side (7) over the edge sides (15 to 18) of the semiconductor chip (6) as far as the inner housing plane (11) whilst leaving free the source and gate contact areas on the top side (7) of the semiconductor chip (6) and also whilst partly leaving free the top sides (10) of the corresponding external contacts (19 and 20).

Abstract: A package for an optical device includes a plurality of ceramic layers 101, 102 and 103 stacked on a base 2 and a recessed portion 18 formed to mount an optical element at the center. Reversely rounded portions 11 are formed on the corners of the ceramic layers 100, 101 and 102 such that at least one of the four corners of the top ceramic layer 103 has an outside shape placed outside the outside shapes of the corners of the ceramic layers 100, 101 and 102 with respect to the center.

Abstract: A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads.

Abstract: A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

Abstract: A high reliability power module which includes a plurality of hermetically sealed packages each having electrical terminals formed from an alloy of tungsten copper and brazed onto a surface of a ceramic substrate.

Abstract: An embedded integrated circuit package-on-package system is provided forming a first integrated circuit package system, forming a second integrated circuit package system, and mounting the second integrated circuit package system over the first integrated circuit package system with the first integrated circuit package system, the second integrated circuit package system, or a combination thereof being an embedded integrated circuit package system or an embedded stacked integrated circuit package system.

Abstract: A ball grid array structure includes a substrate, wherein a plurality of electric contacts are arranged on its lower surface; a chip arranged on the upper surface of the substrate and electrically connecting with those electric-connecting points; at least a through hole on the substrate and arranged around the edge of the chip; a molding compound covering the chip and filling the through hole to form a window-type bump on the lower surface of the substrate; and a plurality of conductive balls arranged on those electric-connecting points on the substrate. The present invention utilizes the window-type bump to enhance the structure strength of the substrate to effectively decrease the warpage of package in the curing process and to provide a support to prevent the crack of the package from the external force.

Abstract: The present invention relates to a stackable semiconductor package, comprising a first substrate, a chip, a second substrate, a plurality of second wires, a plurality of supporting elements and a molding compound. The chip is disposed on and electrically connected to the first substrate. The second substrate is disposed above the chip, and the area of the second substrate is larger than that of the chip. The second substrate is electrically connected to the first substrate by the second wires. The supporting elements are disposed between the first substrate and the second substrate, and are used for supporting the second substrate. The molding compound encapsulates the first surface of the first substrate, the chip, the second wires, the supporting elements and part of the second substrate, and exposes a surface of the second substrate. The overhang portion of the second substrate will not shake or sway during wire bonding process.

Abstract: A semiconductor integrated circuit device is made by stacking a plurality of semiconductor chips. The semiconductor integrated circuit device includes: a penetrating electrode formed to penetrate the plurality of semiconductor chips; a plurality of electrodes formed in respective layers constituting each of the plurality of semiconductor chips and having respective openings within which the penetrating electrode penetrates; and a plurality of vias each of which electrically connects electrodes of the plurality of electrodes located in adjacent layers. The vias are each formed so that the side face thereof is in contact with the penetrating electrode.

Abstract: Solder ball assembly for a semiconductor device and method of fabricating the same is described. In one example, a solder mask is formed on a substrate having an aperture exposing at least a portion of a conductive pad of the substrate. A solder pillar is formed in the aperture and in electrical communication with the conductive pad. An insulating layer is formed on the solder mask exposing at least a portion of the solder pillar. The exposed portion of the solder pillar is removed to define a mounting surface. A solder ball is formed on the mounting surface in electrical communication with the solder pillar. The solder pillar may include high-temperature solder having a melting point higher than that of the solder ball.

Abstract: A semiconductor module includes a wiring board having a bottom surface and a top surface. A first solder electrode terminal has a given melting point, and is provided on the bottom surface of the wiring board. An electrode pad is provided on or above the top surface of the wiring board, and a second solder electrode terminal is soldered to the electrode pad at a temperature corresponding to the given melting point of the first solder electrode terminal by using a reflow process. The second solder electrode terminal contains an additional metal powder component diffused therein when being soldered to the electrode pad.

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked-systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Abstract: A method of protecting a microelectronic chip contained in a microelectronic assembly, including the steps of depositing a protective coating across the exposed faces of the chip. The coating, having a low modulus of elasticity, is applied across the chip so as to reduce the overall height of the assembly while still protecting the exposed face and corners of the chip from damage.

Abstract: A semiconductor package assembly having reduced stresses and a method for forming the same are provided. The method includes providing a package substrate comprising a base material, forming an interconnect structure overlying the package substrate, attaching at least one chip to a first surface of the package substrate, thinning the package substrate from a second surface opposite the first surface wherein the semiconductor material is substantially removed, and attaching ball grid array (BGA) balls to deep vias exposed on the second surface of the package substrate after thinning the package substrate.

Abstract: A heatsink architecture employing a combination of stiffeners and flex substrate to improve the sinking of heat from the integrated circuit. The stiffener may be employed in numerous locations, including above the integrated circuit, or interposed between the integrated circuit and an e-block. The flex substrate may be interposed between the integrated circuit and the stiffener, while in other embodiments the integrated circuit is directly coupled to the e-block via heat conductive epoxy and the like. Solder balls may be employed to connect the flex substrate to integrated circuit. The flex substrate may take different forms, and may or may not be connected to the e-block. The flex substrate may be connected directly to the e-block, or connected via an e-pin extending through layers including the flex substrate and/or the stiffener.

Abstract: The invention provides thermally enhanced BGAs and methods for their fabrication with a ground ring suitable for operably coupling to either the frontside or backside, or both, of an IC chip mounted on a substrate. The methods and devices of the invention disclosed include the fabrication of a ground ring on the surface of a BGA substrate prepared for receiving the frontside of the chip. A heat spreader has ground ring corresponding to substrate round ring and is attached at the backside of the chip with a conductive material. A conductive material is interposed between the heat spreader and substrate ground rings, electrically coupling them. Thus, the backside of the chip may be electrically connected to the ground ring as well as, or instead of, the frontside.

Abstract: According to some embodiments, an outer metal is cladded to a core metal to create a cladded heat sink fin, the cladded heat sink fin is inserted in a groove of a heat sink base, and the outer metal is heated to a reflow temperature of the outer metal. Embodiments may alternatively include a heat sink base, an upper metal cladded to an upper surface of the heat sink base, the upper metal defining at least one groove, and a heat sink fin disposed in the groove and secured to the upper metal. Further to the foregoing, embodiments may include a lower metal cladded to a lower surface of the heat sink base, and a pedestal secured to the lower cladding.

Abstract: A high frequency module and a manufacturing method thereof In the module, a substrate has a ground. A plurality of surface mounted devices are mounted on the substrate. A metal wall is connected to the ground of the substrate. A resin molding hermetically seals the surface mounted devices and the metal wall, the resin molding formed to expose a top surface of the metal wall. Also, a metal film is formed on the resin molding to contact the top surface of the exposed metal wall.

Abstract: A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.

Abstract: A semiconductor integrated circuit has: a power pad placed on a chip; and a circuit group connected to the power pad through a power wiring structure. The power wiring structure includes: a plurality of first power wirings and a plurality of second power wirings that are formed in different wiring layers and overlap with each other at a plurality of intersections; and vias connecting the plurality of first power wirings and the plurality of second power wirings. The circuit group includes a first functional block placed on a first region. The vias are not placed at a part of the plurality of intersections within a second region located between the first region and the power pad.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.

Abstract: A method for producing a semiconductor device of the present invention includes forming a surface electrode on a semiconductor element, forming a solder layer by plating on one principal surface of the surface electrode, mounting the semiconductor element on the sub-mount so that the solder layer contacts a principal surface of the sub-mount, and bonding the sub-mount and the semiconductor element to each other via the solder layer.

Abstract: An interconnect structure and method for manufacturing are described wherein an insulating material adjacent to or at least partially surrounding a conductive interconnect has a coefficient of thermal expansion (CTE) equal to or larger than the CTE of the interconnect. For example, a copper-based damascene interconnect layer may be provided, wherein an inter-layer dielectric (ILD) a least partially surrounds the interconnect layer and a cap insulator is disposed on the interconnect layer. In such an embodiment, the CTE of the ILD and/or the cap insulator would be at least as large as the CTE of the interconnect layer. This may result in no stress or compressive stress being applied by the insulating material to the interconnect layer when the device has cooled, such as to room temperature, after formation of the various layers.

Abstract: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

Abstract: An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and heat treatment stability under a hydrogen-containing atmosphere is provided. An electro-resistance element includes an electro-resistance layer that has two or more states in which electric resistance values are different and being switchable from one of the two or more states into another by applying a predetermined voltage or current. The electro-resistance layer includes first and second elements being capable of forming a nitride, and nitrogen.

Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: In the case where a first semiconductor chip and a second semiconductor chip are stacked, both the semiconductor chips are connected using micro bumps, such that a circuit block in the first semiconductor chip and a circuit block in the second semiconductor chip are connected by the micro bumps, and the circuit block in the second semiconductor chip is also connected to the external electrode by the micro bumps through the first semiconductor chip. Further, the micro bumps that connect circuit blocks of both the semiconductor chips and the micro bumps that connect the circuit block in one chip to an external electrode are arranged in different positions.

Abstract: An electric terminal device is provided with glass substrate 11, glass-substrate-side electric terminals 15 formed on glass substrate 11, tape carrier packages 16a and 16b which are larger in thermal expansion rate than glass substrate 11, and tape-side electric terminals 21 provided to correspond to glass-substrate-side electric terminals 15. Tape-side electric terminals 21 include alignment terminals 25 to align with terminals at the outer most edges of glass-substrate-side electric terminals 15, and connecting terminals 26 electrically and mechanically connected to glass-substrate-side electric terminals 15 due to thermal expansion of tape carrier packages 16a and 16b by thermo-compression bonding on a condition that alignment terminals 25 of tape-side electric terminals 21 are aligned with the terminals of glass-substrate-side electric terminals 15.

Abstract: An IC chip package, including a single chip package, two stacked chips package or a System-In-Package (SIP), is created to minimize the assembled volume, which basic structure comprises a chip, a circuited substrate provided for the chip electrically mounted thereon and an encapsulated means for covering the chip to constitute a package structure, wherein the chip has a processed substrate with an active side and an inactive side and one or more half-tunneling electrical contacts penetrating the processed substrate to form one or more electrical contacts on the inactive side of the chip, so that the chip is directly through the inactive side of the processed substrate electrically mounted to the circuited substrate without via bonding wires.

Abstract: A power semiconductor component (2) has a semiconductor body with a front face (7) and a rear face (9). The front face (7) has a front-face metallization (8), which provides at least one first contact pad (11). A structured metal seed layer (14) is provided as the front-face metallization (8), is arranged directly on the semiconductor body, and has a thickness d, where 1 nm?d?0.5 ?m.

Abstract: A method and apparatus related to a substrate support structure are provided. In accordance with one embodiment of the present invention, a method for manufacturing a substrate support structure including proximity pins and apparatus for supporting a substrate inside a semiconductor processing equipment are provided. The method includes providing a plate assembly comprising a plate and a plate surface and forming a plurality of recessed regions in the plate surface. Additionally, the method includes filling the recessed regions with a bonding material including epoxy material and placing a plurality of support members into the epoxy-coated recessed regions. The method further includes pushing the support members with a flat plate held up from the surface by shims to provide a uniform local height of the support members, followed by a curing step to fix the supporting members to the recessed regions.

Abstract: An IC device includes a die and a first package interposer stacked over a second package interposer. The IC device includes a first conductive connection from a first bond pad of the die directly to a bond pad of the first interposer and a second conductive connection from a second bond pad of the die directly to a bond pad of the second interposer. Another IC device includes a second die stacked over a separate first die and a first package interposer stacked over a separate second package interposer. The first die is stacked over the first interposer. A first conductive connection exists from a bond pad of the first die directly to a bond pad of the first interposer and a second conductive connection exists from a bond pad of the second die directly to a bond pad of the second interposer.