Abstract: A battery for a dockable electronic device is provided. The battery includes a housing having a recess, and at least one battery cell disposed in the housing. The recess of the housing is operable to receive a docking station platform when the dockable electronic device is docked at the docking station while the housing is coupled to a bottom surface of the dockable electronic device.

Abstract: A handheld computer having a housing with a midframe construction is described. The housing includes a front shell and a back shell coupled to a midframe. The handheld computer also includes two accessory slots for a stylus or other devices on the left and right sides of the housing. The handheld computer also includes an infrared port which is an integral portion of the housing.

Abstract: A notebook computer support seat which can be conveniently folded and carried is the support seat which is made by lightweight but stiff aluminum plates pivoted by hinges. A support arm on a base plate can be reversely inserted into an insertion hole of a front plate, projected support pieces can support the notebook computer, and insertion blocks at a tail end of a support plate or another coaxial inner support plate can be inserted into any set of insertion holes of the base plate according to an angle required by a user. The present invention can be folded into a plane shape, to facilitate being placed in a suitcase with the notebook computer, for carrying.

Abstract: A large capacity HDD is handled as a portable recording medium. In a state where a portable hard disk (PHD) unit is mounted on a cradle, data is written and read between the PHD unit and a host device. By having a first engagement section on the side of the PHD unit and a second engagement section on the side of a mounting section of the cradle mutually engaged while the PHD unit is mounted on the mounting section, a state where the PHD unit is mounted on the mounting section is maintained.

Abstract: Various embodiments of a media drive containment apparatus and methods are provided. In one representative embodiment a media drive containment apparatus includes a drivecage which supports at least one media drive. The drivecage is moveable along an axis from an operating position to a release position and the movement of the drivecage to the release position unlocks the media drive from the drivecage.

Abstract: An electronics chassis, such as a computer chassis including various active electronic components having various heat dissipation rates and operating tolerances. A power supply and various components are housed in an enclosure. A component cooling system causes a first fluid to flow through an area surrounding the electronic components to cool the electronic components through convection. A power supply cooling system causes a second fluid to flow through an area surrounding the power supply to cool the power supply through convection by drawing fluid from an area external of said enclosure and exhausting fluid to an area external of said enclosure. The second fluid is isolated from the first fluid within the enclosure.

Abstract: A power unit device which can be made small, with which special measures of plant and labor at the time of assembly are unnecessary, and of which assembly is easy and universality in its manufacturing aspect is excellent. The power unit device has a heat sink having a first heat-receiving part and formed on the opposite side from this a second heat-receiving part; a power module, in firm contact with the first heat-receiving part, containing a power semiconductor element for performing DC-AC conversion and/or AC-DC conversion for one phase; a smoothing condenser, in firm contact with the second heat-receiving part, for suppressing ripple current of the power semiconductor element; and fixing means passing through the power module, the heat sink and the smoothing condenser.

Abstract: The invention provided a heatsink thermal module with noise improvement, which has a heatsink thermal module additionally consisting of a heat pipe, a heatsink fins set and a fan module; the fan module is combined with the heatsink fins set which consists of multiple heatsink fins with different lengths and is combined to the fan module with its end with a special geometric shape having the function of lowering the wind drag; by lowering the wind drag, not only the heat dissipation efficiency can be increased, but the noise caused by the heatsink thermal module can also be improved.

Abstract: A heat dissipation device includes a heat sink, a retention module and a clip. The retention module includes a plurality of locking portions. The clip includes a main piece, an operating piece pivotally connecting with the main piece, and a buckling piece pivotally connecting with the operating piece. The main piece includes a pressing beam resting on the heat sink and a clamping portion engaging with a corresponding locking portion of the retention module. By operating the operating piece, the heat dissipation device has two positions, at a first of which a clamping portion of the buckling piece engages with a corresponding locking portion of the retention module and the pressing beam of the main piece presses the heat sink toward the retention module; at a second of the two positions, the clamping portion of the buckling piece disengages from the retention module.

Abstract: For cooling of an electronic equipment, a heat receiving jacket, to which piping extended outside the electronic equipment is connected, is mounted to a heat generating element in the electronic equipment, a radiator, a cooling-liquid tank, a pump, and a pipe, which joins them, are constructed as an external module, and the external module is mounted externally and fixed to a housing of the electronic equipment. Cooling liquid is circulated by the pump through the heat receiving jacket, the radiator, and the tank to achieve cooling.

Abstract: A electronic device and method for extracting heat from a heat producing component having front and back sides, the front side is disposed across from the back side, and the front side is attached to a substrate including multiple holes. A thermal interface material is disposed over the back side of the heat producing component. A heat sink including multiple pins corresponding to the multiple holes in the substrate is disposed over the thermal interface material such that the pins are disposed through the holes. The thermal interface material melts and wets to form a thermal coupling between the back side and the heat sink when passed over pre-heaters of a wave soldering machine. Further, the pins are soldered to form solder joints between the respective pins and the substrate when passed over a solder wave in the wave soldering machine to lock-in the thermal coupling formed during the preheating of the thermal interface material to provide a low-cost thermal solution.

Abstract: A heat radiating apparatus is provided which includes a heat sink configured to be positioned in thermal contact with a heat source in order to take heat from the heat source, at least one heat pipe having a portion connected to the heat sink and configured to transfer the heat from the heat sink, a heat exchanger in thermal communication with the at least one heat pipe, formed with a through chamber at a center thereof, and positioned adjacent to the heat sink, and a fan unit installed at least partially in the through chamber of the heat exchanger and configured to generate an airflow through the heat exchanger. Heat generated not only by a specified heat source but also by an interior of electronic equipment can be quickly radiated.

Abstract: A heat sink in an electric junction box has thermal diffusion portions having one of convex and concave shapes on the surface. The structure enlarges a surface area of the heat sink compared to a configuration in which a surface has no concavity or convexity, thereby allowing fast heat dissipation from the surface of the heat sink to the exterior of the junction box. Further, the heat sink has the thermal diffusion portions on the entire plate surface. The structure enlarges the surface area of the heat sink compared to a configuration in which the thermal diffusion portions are provided to only a portion of the surface, thereby further enhancing the heat dissipation.

Abstract: A memory module assembly (1) includes a printed circuit board (10) having an electronic heat-generating electronic component (40) thereon, a heat sink (20) and a clip (30) for securing the heat sink onto the heat-generating electronic component. The clip includes a pressing portion (32) and a pair of latching portions (33) respectively extending from two ends of the pressing portion. Each latching portion includes a latching leg (332) and a retaining hook section (334) formed at a bottom end of the latching leg. The retaining hook sections tightly engage a bottom face of the printed circuit board and the pressing portion presses the base toward the heat-generating electronic component. The latching legs extend through an opening and a through hole in the printed circuit board. The through hole has a L-shaped configuration and does not communicate with a periphery side of the printed circuit board.

Abstract: A heat dissipation system for a miniaturized form factor card allows a communications system for mobile information devices contained in the card to operate with high heat loads by employing a high conductivity pad on the printed circuit board of the mobile information device which contacts the case of the miniaturized form factor card. Additionally, heat dissipation plugs are integrated into the edge of the PCB with emitting surfaces adjacent radiation holes in the case of the mobile information device adjacent the PCB. Heat convection channels through layers of the PCB allow transfer of heat from the pad to other conductive layers in the PCB. High thermal conductivity packing in the miniaturized form factor card conducts heat from the internal components to the case of the card in contact with the high conductivity. Placement of high heat generation components within the card case adjacent the contact interface with the high conductivity pad is also employed for maximum heat dissipation.

Abstract: A mounting device for mounting a first element onto a second element includes a plurality of fastening elements. Each of the fastening elements includes a connecting member defining a clasping groove therein, and a guiding portion adjacent to the clasping groove. A ring-shaped clipping member snaps in the clasping groove of the connecting member after moving over the guiding portion to be expanded. A fixing member is coupled to the connecting member for sandwiching the first element and the second element therebetween. A resilient member adapts for being sandwiched between the connecting member and the first element to provide resilient force to urge the first element toward the second element.

Abstract: A heat dissipation device includes a heat sink, a retention module and a clip securing the heat sink to the retention module. The retention module includes a bottom wall and a plurality of sidewalls surrounding the bottom wall. The heat sink includes a plurality of the fins and a plurality of passages defined therebetween. The heat sink is located on the bottom wall of the retention module. The sidewalls of the retention module surround a bottom portion of the heat sink. The sidewalls define a plurality of voids therein for an airflow generated by a fan mounted on the heat sink passing therethrough. The airflow flows through the heat sink and then the voids in the sidewalls of the retention module to cool electronic components located beside the retention module.

Abstract: According to an embodiment, a circuit board device comprises a circuit board having a first surface and a second surface opposed thereto, a first electronic component mounted on the first surface of the circuit board, a stud set up on the first surface of the circuit board and fastened to the circuit board by a stud fixing screw threaded therein from the second surface side, a heat radiating member which is thermally connected to the first electronic component and radiates heat from the first electronic component, and a pressing member which is screwed to the stud from the first surface side of the circuit board and presses the heat radiating member against the first electronic component. A second electronic component is located on the second surface of the circuit board so as to overlap the stud fixing screw.

Abstract: A high strength, light weight crash survivable memory unit (CSMU). The CSMU includes memory storage devices surrounded by a heat resistive material. A housing surrounds the heat resistive material. The housing includes a plurality of panels that include Titanium. Two or more of the panels are fusion welded together. The welding is performed at tapered outer edges of one or more of the panels.

Abstract: A flexible printed circuit board includes a flexible substrate, which has a bonding zone, a folding zone, and a folding line between the bonding zone and the folding zone, two electrically conductive contacts respectively located at the bonding zone, two lead wires each having an extension portion respectively electrically connected to the electrically conductive contacts and arranged in parallel to the folding line and a connecting portion extending integrally from the extension portion toward the folding zone, and a protective layer covered on the flexible substrate over the lead wires. The protective layer has openings corresponding to the electrically conductive contacts.

Abstract: A combination current sensor and relay has an improved housing. In one aspect, the housing includes light emitting diodes on an upper surface that indicate open circuit and short circuit conditions. In another aspect, the housing includes a securement structure for a circuit board that includes the transformer and switches for device operation, together with aligned openings therein for routing wires to external devices. In another aspect, a multiple position switch is included on the upper surface that indicates multiple modes of operation of the device. In another aspect, the housing may be assembled in multiple parts by affixing a first portion to a support, a circuit board to the first portion, and a second portion to the first portion. In another aspect, the housing is suitable for engagement to alternatively a junction box and a duplex box. In another aspect, the configuration of the upper surface provides usability advantages.

Abstract: A circuit board includes: a substrate; a conductive pattern disposed on a surface of the substrate; a lower insulation layer disposed on the conductive pattern to cover the conductive pattern except for an opening, through which the conductive pattern is partially exposed from the lower insulation layer; a conductor disposed on the lower insulation layer and connecting to the conductive pattern through the opening; an upper insulation layer disposed on the conductor for covering the conductor and the lower insulation layer; and a test coupon disposed on the substrate for evaluating the conductor.

Abstract: A screwing control device of a computer chassis is composed of a computer chassis, a panel of which is pre-built with a plurality of positioning holes; a screw element, a center of which is provided with a screw hole and which is able to be locked and fixed into one of the positioning holes; and a bolt, which is transfixed into a through-hole of a board element, and is then screwed into the screw hole of the screw element. Therefore, a quantity of the screw elements which are actually used for screwing can be effectively controlled, and pre-built projected bolts which are not necessarily used for screwing can be eliminated.

Abstract: There is provided a high-efficiency DC-DC converter which comprises a voltage resonance circuit to which electric power from a low-voltage direct-current power supply, including a household fuel cell and a solar cell, is input and performs DC-AC conversion by zero-voltage switching, an insulating high-frequency transformer which transmits the converted power, a current resonance circuit which is provided on the secondary side of the transformer and performs zero-current switching, a rectifier circuit which rectifies the output from the current resonance circuit, and a smoothing circuit which rectifies the output from the rectifier circuit.

Abstract: An improved Single-Stage Buck-Boost inverter (S2B2 Inverter) is provided, using only three or four power semiconductor switches and two coupled inductors in a flyback arrangement. The inverter can handle a wide range of dc input voltages and produce a fixed ac output voltage. The inverter is well suited to distributed power generation systems such as photovoltaic and wind power and fuel cells, for standalone or grid connected applications. The inverter has a single charge loop, a positive discharge loop and a negative discharge loop.

Abstract: There is disclosed a power conversion circuit comprising a transformer having a primary side driven by an input section and a secondary side connected to first and second self-driven synchronous rectifiers. A shutdown section includes a control section adapted to detect a predetermined condition and means for shorting a winding of the transformer upon detection of the predetermined condition.

Abstract: A technique for controlling a power supply with power supply control element with a tap element. In one embodiment, a power supply regulator includes a power transistor having first, second, third and fourth terminals. A control circuit is included, which is coupled to the third and fourth terminals of the power transistor. The power transistor is configured to switch a current between the first and second terminals in response a control signal received from the control circuit at the third terminal. A voltage between the fourth and second terminals of the power transistor is substantially proportional to a current flowing between the first and second terminals when a voltage between the first and second terminals is less than a pinch off voltage. The voltage between the fourth and second terminals of the power transistor is substantially constant and less than the voltage between the first and second terminals when the voltage between the first and second terminals is greater than the pinch off voltage.

Abstract: A system and method are disclosed for controlling DC to AC power converters (inverters) that are operated as voltage sources and are paralleled on the AC side. This method allows for controlling frequency while sharing real power. The disclosed method requires no communication between inverters for proper load sharing, thus enhancing reliability of a system of parallel inverters. The only signals required for control are the AC voltage and frequency and their reaction to the inverter output current. The present invention allows a multiplicity of inverters or active rectifiers to share power in relation to their share of the available power capacity of the system. This makes it possible to parallel DG sources with various response times while they are connected to either a utility grid or in a stand-alone power network with no communications required between inverters. The addition of communications to the system allows the dispatch of energy for economic reasons and to fine tune load balance.

Abstract: An isolating type self-oscillating flyback converter is disclosed, which includes a coupled transformer, a FET, a transistor and an electro-optical coupled isolating feedback unit, wherein the input terminal of the circuit is connected to the source of the FET through a primary winding of the coupled transformer, the input terminal of the circuit is connected to the collector of the transistor through a resistor R1 and another resistor R2, the source of the FET is connected to the collector of the transistor, one branch of the drain of the FET is connected to the ground through a resistor, while the other branch is connected to the base of the transistor through the parallel connection body of a resistor and a capacitor, the base of the transistor is connected to the output terminal of a secondary output winding of the coupled transformer through the electro-optical coupled isolating feedback unit; the series connection joint between the said resistor R1 and the said resistor R2 is connected to the ground thr

Abstract: An improved switch for power factor correction circuits includes a six-terminal switch which has a first inductor connecting to a selection line which has a first switch terminal and a second switch terminal, and a second inductor connecting to a conductive line. When the switch is at a first position, the selection line is connected to the first switch terminal, and the conductive line is closed to determine the first and second inductors in a parallel coupling condition and the power conversion circuit in a first duty condition. When the switch is at a second position, the selection line is connected to the second switch terminal and the conductive line is open to determine the first and second inductors in a serial coupling condition, and the power conversion circuit in a second duty condition.

Abstract: Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on the memory modules are accessed from a database such that the operating current values may be implemented to improve system performance. Memory modules comprising a number of volatile memory devices may be fabricated. Operating current values corresponding to the specific memory devices on the memory module may be stored in a database and accessed during fabrication or during implementation of the memory modules in a system. System performance may be optimized by implementing the unique operating current values corresponding to the specific memory devices on the memory modules.

Abstract: The invention relates to a one-time programmable memory device. In order to make such a memory device particular simple and reliable, it is proposed that the device comprises a MOS selection transistor T1 and a MOS memory transistor T2 connected in series between a voltage supply line BL and ground Gnd. The device further comprises programming means for applying predetermined voltages Vsel, Vctrl, Vprog to the gate of the selection transistor T1, to the gate of the memory transistor T2 and to the voltage supply line BL. The applied voltages Vsel, Vctrl, Vprog are selected such that they force the memory transistor T2 into a snap-back mode resulting in a current thermally damaging the drain junction of the memory transistor T2. The invention relates equally to a corresponding method for programming a one time programmable memory.

Abstract: An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) an array low voltage control circuitry that provides an enhanced low operating voltage VESS to the SRAM array during at least a portion of an active mode thereof.

Abstract: A memory element having a first and second logic components, each having a first input, a second input, and an output. The first input of each of the logic components is connected to the output of the other logic component. The second inputs of each of the logic components are connected to a control line. The first and second logic components are embodied such that when a control signal having a first level is applied to the control line at the respective output, a signal is output which has an output level that is inverted with respect to the level of the signal present at the respective first input, and when a control signal having a second level is applied to the control line at the respective output, a signal is output which has a predetermined level independent of the level of the signal present at the respective first input.

Abstract: A write word line is disposed right under a MTJ element. The write word line extends in an X direction, and side and lower surfaces of the write word line are coated with a hard magnetic material and yoke material. The hard magnetic material is magnetized by a surplus current passed through the write word line, and a characteristic of the MTJ element is corrected by residual magnetization. A data selection line (read/write bit line) is disposed right on the MTJ element. The data selection line extends in a Y direction intersecting with the X direction, and a part of the surface of the data selection line is coated with the yoke material.

Abstract: Methods and apparatus are provided for testing a magnetoresistive random access memory (MRAM). A magnetoresistive tunnel junction (MTJ) has a first terminal, a second terminal, and a third terminal. A source measuring unit is coupled to a first terminal of a MTJ to provide DC biasing. A current preamp has an input coupled to a third terminal of the MTJ for receiving current corresponding to a resistance of the MTJ. A pulse generator is AC coupled to the MTJ for programming the MTJ. A method of insitu testing a MTJ in a manufacturing environment uses a probe station coupled to the MTJ. A probe station couples to the MTJ. The MTJ is DC biased for generating a current corresponding to the logic level stored in the MTJ. A pulse for programming the MTJ is AC coupled to the MTJ.

Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Abstract: Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

Abstract: A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.

Abstract: TA page buffer of a flash memory device has a page buffer that improves the program operation performance and program operation control method thereof. The page buffer has a flash memory device having a MLC. The page buffer stores input data in an upper bit register, initial data having the same value as that of the input that data are stored in a lower bit register.

Abstract: The memory area on a die required for row (X) and column (Y) decoders is reduced by a plurality of memory array blocks sharing wordlines to a single row decoder. During erase operations, the p-well of unselected memory array blocks is pulled negative to substantially the same potential as the wordline to avoid erase disturbances. During programming operations, the unselected p-wells are pulled high to avoid gate disturbances.

Abstract: Methods for erasing an integrated circuit memory device having a cell array region that includes a main cell array region, a first dummy cell array region on a first side of the main cell array region and a second dummy cell array region on a second side of the main cell array region are provided. A first erasure voltage is applied to a plurality of main control gate electrodes in the main cell array region. The plurality of main control gate electrodes include a first outermost main control gate electrode adjacent to the first dummy cell array region and a second outermost main control gate electrode adjacent to the second dummy cell array region. A second erasure voltage is applied to an integrated circuit substrate in the main cell array region. The second erasure voltage is greater than the first erasure voltage.

Abstract: A semiconductor memory device which is highly reliable, is operable at a low voltage and a high speed, and is produced at a high production yield is provided. A nonvolatile semiconductor memory device capable of reading and erasing data and holding the data even while no voltage is supplied comprises a plurality of memory cells each including a plurality of local charge portions each capable of storing a static charge corresponding to the data. Either two of the local charge portions store the charges in a complementary state.

Abstract: A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

Abstract: Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well structure that includes a substrate, the buried layer, and an epitaxial layer. The substrate, buried layer, and epitaxial layer include voltage contacts that allow for the wells to be biased to a dc voltage level. The memory cell includes a transistor which is formed on the epitaxial layer, the transistor including a source and drain region separated by a channel region. The trench bit line is formed within the buried layer, and is coupled to the drain region of the transistor by a bit contact.

Abstract: A non-volatile semiconductor memory device including a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a sense amplifier circuit for reading said memory cell array, wherein the sense amplifier circuit includes: a first transistor disposed between a bit line of the memory cell array and a sense node to serve for sensing bit line data, the first transistor being driven by a voltage generating circuit including a boost circuit to transfer a bit line voltage determined in response to data of a selected memory cell to the sense node; a second transistor coupled to the sense node for precharging the sense node prior to bit line data sensing; a data latch for judging a transferred bit line voltage level to store a sensed data therein; and a capacitor for boosting the sense node, one end thereof being connected to the sense node, the other end thereof being selectively driven by a boost-use voltage.

Abstract: A reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a predetermined expected value data; a second register holding data which was auto-loaded; and a data comparison circuit which performs a comparison between the data held in the second register and the expected value data stored in the first register, and generates the reset signal based on a result of the comparison.

Abstract: In an embodiment, an improved charge pump circuit is provided to control a threshold voltage increase of a charge transmission transistor during a charge transfer period, and to prevent a latch-up generation during a charge non-transfer period. A charge transmission transistor transmits the voltage of a boosting node to a high voltage generation terminal in response to the voltage of a control node. In a bulk connection switch, during the charge transfer period the high voltage generation terminal is connected to the bulk of the charge transmission transistor and during the charge non-transfer period the bulk is connected to the low voltage, being lower than that of the voltage appearing at the boosting node of the charge transmission transistor or the high voltage generation terminal. Charge transmission efficiency and pumping operation reliability are improved, increasing the reliability of data access operations in a semiconductor memory device, for example.

Abstract: A semiconductor memory device comprises: a memory cell array having a standard memory cell array part in which dynamic memory cells are arranged in a matrix pattern, and a redundant memory cell array having a redundant memory cell set up to replace a defective memory cell in the standard memory cell array part; an access control part controlling external access operation and refresh access operation regarding the memory cell array; and a redundancy judgment circuit executing redundancy judgment to determine whether the memory cell which is a subject to the external access operation or the refresh access operation is the redundant memory cell or not, controlling so as to access the redundant memory cell, if the subjected memory cell is the redundant memory cell, and controlling so as to access the memory cell in the standard memory cell array, if the subjected memory cell is not the redundant memory cell.