Abstract: The photodetector comprises a continuous active layer in which, in response to incident light a signal is generated that is proportional to the incident position of the light; it is characterized in that the active layer comprises a first (1) and a second organic semiconductors (2) distributed along a longitudinal gradient, corresponding to a relative concentration gradient, a structure gradient or both. The invention also relates to a method for obtaining the photodetector and to the method for measuring the response from the photodetector. It makes it possible to obtain a continuous sensor of larger dimensions than those known in the prior art, thereby increasing the operating range without altering the sensitivity thereof.

Abstract: The purpose of the present invention is to provide a transparent surface electrode that maintains high transparency, suppresses the occurrence of leak currents, and has superior storage stability and resistance to damage by bending, a method for manufacturing the same, and an organic electronic element using the same. This transparent surface electrode has a metal pattern conductive layer that contains a metal on a transparent base material, and the transparent surface electrode also has a transparent polymer conductive layer, which contains that base material and a conductive polymer, on that metal pattern conductive layer. The transparent surface electrode is characterized by the surface roughness (Ra (surface roughness provided for by JIS, B601 (1994))) of the metal pattern conductive layer being 20 nm or less, and the polymer conductive layer containing a non-conductive polymer having a hydroxyl group.

Abstract: The present invention provides an organic EL display panel and an organic EL display apparatus that can be driven at a low voltage and that exhibit excellent light-emitting efficiency. Sequentially fixated on a substrate are: a first electrode; auxiliary wiring; a hole injection layer; a functional layer; and a second electrode. The hole injection layer and the second electrode are both formed to be continuous above the first electrode and above the auxiliary wiring. The second electrode and the auxiliary wiring are electrically connected by the hole injection layer. The hole injection layer contains tungsten oxide and at least 2 nm thick so as to have, in an electronic state thereof, an occupied energy level in a range between 1.8 eV and 3.6 eV lower than a lowest energy level of a valence band in terms of a binding energy.

Abstract: A photoelectric conversion element having high photovoltaic conversion efficiency is provided. The photoelectric conversion element includes a first electrode, a second electrode arranged opposite to the first electrode, and an electron transport layer provided on a face of the first electrode, and the face is opposite to the second electrode. The photoelectric conversion element further includes a photosensitizer supported on the electron transport layer and a hole transport layer interposed between the first electrode and the second electrode. The electron transport layer contains a perylene imide derivative of [Chemical Formula 1].

Abstract: Embodiments of the present invention relate to a display device, an array substrate, and a thin film transistor. The thin film transistor comprises a gate, an active layer and a gate insulating layer disposed between the gate and the active layer, the active layer is an oxide semiconductor, and the gate insulating layer comprises at least one layer of inorganic insulating thin film. With the gate insulating layer of the thin film transistor, it is possible that an adverse effect on the oxide semiconductor given by hydrogen-containing groups is effectively avoided, stability of the whole TFT device is enhanced to the most extent, and yield of final products is increased.

Abstract: A method for evaluating an oxide semiconductor film, a method for evaluating a transistor including an oxide semiconductor film, a transistor which includes an oxide semiconductor film and has favorable switching characteristics, and an oxide semiconductor film which is applicable to a transistor and enables the transistor to have favorable switching characteristics are provided. A PL spectrum of an oxide semiconductor film obtained by low-temperature PL spectroscopy has a first curve whose local maximum value is found in a range of 1.6 eV or more and 1.8 eV or less and a second curve whose local maximum value is found in a range of 1.7 eV or more and 2.4 eV or less. A value obtained by dividing the area of the second curve by the sum of the area of the first curve and the area of the second curve is 0.1 or more and less than 1.

Abstract: A solid-state image sensing element including a transistor with stable electrical characteristics (e.g., significantly low off-state current) is provided. Two different element layers (an element layer including an oxide semiconductor layer and an element layer including a photodiode) are stacked over a semiconductor substrate provided with a driver circuit such as an amplifier circuit, so that the area occupied by a photodiode is secured. A transistor including an oxide semiconductor layer in a channel formation region is used as a transistor electrically connected to the photodiode, which leads to lower power consumption of a semiconductor device.

Abstract: A transistor including an oxide semiconductor film, in which the threshold voltage is prevented from being a negative value, is provided. A high quality semiconductor device having the transistor including an oxide semiconductor film is provided. A transistor includes an oxide semiconductor film having first to third regions. The top surface of the oxide semiconductor film in the first region is in contact with a source electrode or a drain electrode. The top surface of the oxide semiconductor film in the second region is in contact with a protective insulating film. The thickness of the second region is substantially uniform and smaller than the maximum thickness of the first region. The top surface and a side surface of the oxide semiconductor film in the third region are in contact with the protective insulating film.

Abstract: A multilayered structure is provided. The multilayered structure may include a silicon substrate and a film of gadolinium oxide disposed on the silicon substrate. The top surface of the silicon substrate may have silicon orientated in the 100 direction (Si(100)) and the gadolinium oxide disposed thereon may have an orientation in the 100 direction (Gd2O3(100)).

Abstract: A standard cell and a semiconductor integrated circuit which enable a reduction in layout area are provided. A power source line for supplying a high power source potential and a power source line for supplying a low power source potential are arranged in the same wiring layer, and a power source line for supplying a back-gate electrode with a voltage for controlling a threshold voltage is provided to overlap with one of the two power source lines. Further, standard cells each requiring a different number of power source lines are arranged in the same cell row, and a different number of power source lines are connected to each cell row, whereby the number of unnecessary power source lines is reduced so that layout area is reduced.

Abstract: A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

Abstract: Miniaturized transistors having high and stable electric characteristics using high precision microfabrication are provided with high yield. Further, high performance, high reliability, and high productivity also of a semiconductor device including the transistor are achieved. A semiconductor device includes a vertical transistor in which a first electrode layer, a first oxide film containing indium, gallium, zinc, and nitrogen as main components, an oxide semiconductor film containing indium, gallium, and zinc as main components, a second oxide film containing indium, gallium, zinc, and nitrogen as main components, and a second electrode layer are stacked in this order, and a first gate insulating film and a first gate electrode layer are provided at one side of the columnar oxide semiconductor film and a second gate insulating film and a second gate electrode layer are provided at the other side of the columnar oxide semiconductor film.

Abstract: An object is to provide a semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics. An oxide semiconductor layer including SiOx is used in a channel formation region, and in order to reduce contact resistance with source and drain electrode layers formed using a metal material with low electric resistance, source and drain regions are provided between the source and drain electrode layers and the oxide semiconductor layer including SiOx. The source and drain regions are formed using an oxide semiconductor layer which does not include SiOx or an oxynitiride film.

Abstract: Disclosed is a sputtering target that can suppress the occurrence of anomalous discharge in the formation of an oxide semiconductor film by sputtering method and can continuously and stably form a film. Also disclosed is an oxide for a sputtering target that has a rare earth oxide C-type crystal structure and has a surface free from white spots (a poor appearance such as concaves and convexes formed on the surface of the sputtering target). Further disclosed is an oxide sintered compact that has a bixbyite structure and contains indium oxide, gallium oxide, and zinc oxide. The composition amounts (atomic %) of indium (In), gallium (Ga), and zinc (Zn) fall within a composition range satisfying the following formula: In/(In+Ga+Zn)<0.

Abstract: A semiconductor device according to the present invention includes: a gate electrode (62) of a thin film transistor (10) and an oxygen supply layer (64), the gate electrode (62) and the oxygen supply layer (64) being formed on a substrate (60); a gate insulating layer (66) formed on the gate electrode (62) and the oxygen supply layer (64); an oxide semiconductor layer (68) of the thin film transistor (10), the oxide semiconductor layer (68) being formed on the gate insulating layer (66); and a source electrode (70S) and a drain electrode (70d) of the thin film transistor (10), the source electrode (70S) and the drain electrode (70d) being formed on the gate insulating layer (66) and the oxide semiconductor layer (68).

Abstract: A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion.

Abstract: A semiconductor structure includes at least a semiconductor body, a delimiting structure delimiting a cup-shaped recess in the body and a conductive region in the recess. The conductive region is made of a low-melting-temperature material, having a melting temperature lower than that of the materials forming the delimiting structure.

Abstract: Increase in the chip size of a semiconductor device is suppressed. The semiconductor device includes: circuit vias provided in an interlayer insulating film between upper and lower wiring layers and coupling these wiring layers together; a planar ring-shaped protecting via that is provided in the interlayer insulating film under an electrode pad and one side of which is coupled with the electrode pad; a protecting wiring layer comprised of a wiring layer coupled only with the other side of the protecting via; and a semiconductor element provided over the principal surface of a semiconductor substrate under the protecting wiring layer. The lower part of the electrode pad whose surface is exposed is encircled with the protecting via and the protecting wiring layer. The width of the protecting via is equal to or larger than the width of each circuit via.

Abstract: The present invention discloses a thin-film transistor (TFT) array substrate and a manufacturing method thereof. Depositing a transparent conductive layer and a first metal layer in turn on a substrate patterned by a first multi-tone mask (MTM) to form a gate, a common electrode and a reflecting layer; depositing a gate insulation layer and a semiconductor layer patterned by a second MTM to remain the semiconductor layer on the gate; and depositing a second metal layer patterned by a third MTM to form a source and a drain.

Abstract: A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including polycrystalline silicon is also used for a structure layer such as a movable electrode of a structure body. Therefore, the structure body and the electric circuit for controlling the structure body can be formed over one substrate. As a result, a micromachine can be miniaturized. Further, assembly and packaging are unnecessary, so that manufacturing cost can be reduced.

Abstract: The cost of liquid phase epitaxial growth of a monocrystalline silicon carbide is reduced. A feed material 11 is such that when a surface layer thereof containing a polycrystalline silicon carbide with a 3C crystal polymorph is subjected to X-ray diffraction, a diffraction peak corresponding to a (111) crystal plane and a diffraction peak other than the diffraction peak corresponding to the (111) crystal plane are observed as diffraction peaks corresponding to the polycrystalline silicon carbide with a 3C crystal polymorph.

Abstract: An organic film-forming polymer has a Tg of at least 70° C. and comprises a backbone comprising recurring units of Structure (A) shown in this application. These organic film-forming polymers can be used as dielectric materials in various devices with improved properties such as improved mobility.

Abstract: In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.

Abstract: The present invention discloses a thin-film transistor (TFT) array substrate and a manufacturing method thereof. Depositing a transparent conductive layer and a first metal layer on a substrate, which is patterned by a multi-tone mask (MTM) to form a gate, a common electrode and a reflecting layer; depositing a gate insulation layer, which is patterned by a first mask to remain the gate insulation layer on the gate; depositing a semiconductor layer, which is patterned by a second mask to remain the semiconductor layer on the gate; and depositing a second metal layer, which is patterned by a third mask to form a source and a drain.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a phosphor layer, and a transparent film. The semiconductor layer has a first face, a second face opposite to the first face, and a light emitting layer. The p-side electrode is provided on the second face in an area including the light emitting layer. The n-side electrode is provided on the second face in an area not including the light emitting layer. The phosphor layer is provided on the first face. The phosphor layer includes a transparent resin and phosphor dispersed in the transparent resin. The transparent film is provided on the phosphor layer and has an adhesiveness lower than an adhesiveness of the transparent resin.

Abstract: Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.

Abstract: Provided is a method of fabricating a gallium nitride semiconductor which enables activation of a p-type dopant with a heat treatment performed for a relatively short period of time. The fabricating method comprises the step of performing, in a vacuum, a heat treatment of a group III nitride semiconductor region, the group III nitride semiconductor region comprising a gallium nitride semiconductor, the gallium nitride semiconductor including a p-type dopant, the a group III nitride semiconductor region having a group III nitride semiconductor surface inclined with respect to a reference plane perpendicular to a reference axis, and the reference axis extending in a direction of a c-axis of the gallium nitride semiconductor.

Abstract: The invention relates to a method for fabricating a structure including a semiconductor material comprising: a) implanting one or more ion species to form a weakened region delimiting at least one seed layer in a substrate of semiconductor material, b) forming, before or after step a), at least one metallic layer on the substrate in semiconductor material, c) assembling the at least one metallic layer with a transfer substrate, then fracturing the implanted substrate at the weakened region, d) forming at least one layer in semiconductor material on the at least one seed layer, for example, by epitaxy.

Abstract: A silicon carbide Schottky diode solid state radiation detector that has an electron donor layer such as platinum placed over and spaced above the Schottky contact to contribute high energy Compton and photoelectrical electrons from the platinum layer to the active region of the detector to enhance charged particle collection from incident gamma radiation.

Abstract: The invention provides an SiC semiconductor element having fewer interface defects at the interface between the SiC and the insulating film of the SiC semiconductor, as well as improved channel mobility. The semiconductor element is provided with at least an SiC semiconductor substrate and an insulating film in contact with the substrate, wherein the insulating film is formed on a specific crystal plane of the SiC semiconductor substrate, the specific crystal plane being a plane having an off-angle of 10-20° relative to the {11-20} plane toward the [000-1] direction or at an off-angle of 70-80° relative to the (000-1) plane toward the <11-20> direction. Through the use of a specific crystal plane unknown in the prior art, interface defects between the SiC semiconductor substrate and the insulating film can be reduced, and channel mobility of the semiconductor element can be improved.

Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of single crystal silicon carbide is prepared. At a portion of the semiconductor substrate where a first electrode is to be formed, a metal thin film made of electrode material including an impurity is formed. After the metal thin film is formed, the first electrode including a metal reaction layer in which the impurity is introduced is formed by irradiating the metal thin film with a laser light.

Abstract: On a front surface of a region where a junction termination extension structure of a semiconductor device using silicon carbide is formed, a structure having an n-type semiconductor region with a concentration relatively higher than a concentration of an n?-type drift layer is formed. An edge of the junction termination extension structure located on a side away from an active region is surrounded from its bottom surface to its front surface by an n-type semiconductor region. By this means, it is possible to provide a device with a low resistance while ensuring a withstand voltage, or by decreasing the resistance of the device, it is possible to provide a device with low power loss.

Abstract: A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and second trench in a source electrode part (Schottky diode) are disposed close to each other, and the second trench is deeper than the first trench. A metal electrode is formed in the second trench to form a Schottky junction on a surface of an n-type drift layer in the bottom of the second trench. Further, a p+-type region is provided in part of the built-in Schottky diode part being in contact with the surface of the n-type drift layer, preferably in the bottom of the second trench. The result is a small wide band gap semiconductor device which is low in on-resistance and loss. Electric field concentration applied on a gate insulating film is relaxed to suppress lowering of withstand voltage and increase avalanche breakdown tolerance at turning-off time.

Abstract: An example includes subject matter (such as an apparatus) comprising a planar substrate including a first surface that is planar, at least one bare light emitting diode (“LED”) die coupled to the substrate and conductive ink electrically coupling the at least one bare LED die, wherein the conductive ink is disposed on the substrate and extends onto a surface of the LED that is out-of-plane from the first surface.

Abstract: A luminescent device and a manufacturing method for the luminescent device and a semiconductor device which are free from occurrence of cracks in a compound semiconductor layer due to the internal stress in the compound semiconductor layer at the time of chemical lift-off. The luminescent device manufacturing method includes forming a device region on part of an epitaxial substrate through a lift-off layer; forming a sacrificing portion, being not removed in a chemical lift-off step, around device region on epitaxial substrate; covering epitaxial substrate and semiconductor layer and forming a covering layer such that level of surface thereof in the region away from device region is lower than luminescent layer surface; removing covering layer on semiconductor layer, and that on sacrificing portion surface; forming a reflection layer on covering layer surface and semiconductor layer surface; and forming a supporting substrate by providing plating on reflection layer.

Abstract: A light-emitting device includes a support substrate; a light-emitting stacked layer; transparent-conductive bonding layer; and a semiconductor contact layer. The light-emitting stacked layer includes a first semiconductor layer; an active layer; and a second semiconductor layer, wherein a polarity of the first semiconductor layer is different from that of the semiconductor layer. A first pad is formed on an exposed portion of the first semiconductor layer and a second pad is formed on the semiconductor contact layer. A polarity of the semiconductor contact layer is different from that of the second semiconductor layer.

Abstract: A light emitting diode (LED) device includes at least one stacking LED unit. The stacking LED unit includes a plurality of epitaxial structures interleaved with tunnel junctions. For a given predetermined input power, the plurality of epitaxial structures may reduce an operating current density of the stacking LED unit as compared to an LED unit with a single epitaxial structure and the same horizontal size. The reduced operating current density approaches a quantum efficiency peak. Additionally, for a given predetermined input power, the stacking LED unit may operate in a current density interval corresponding to a quantum efficiency within 20% decrement of the quantum efficiency peak.

Abstract: According to one embodiment, a light emitting module includes a mounting substrate, a plurality of light emitting chips, a transparent layer, and a phosphor layer. The transparent layer is provided between the plurality of light emitting chips on the mounting face and on the light emitting chip. The transparent layer has a first transparent body and a scattering agent dispersed at least in the first transparent body between the plurality of light emitting chips. The scattering agent has a different refraction index from a refraction index of the first transparent body. The phosphor layer is provided on the transparent layer. The light emitting chip includes a semiconductor layer, a p-side electrode, an n-side electrode, a p-side external terminal, and an n-side external terminal.

Abstract: A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).

Abstract: A display device includes a laminated wiring formed of a low-resistance conductive film, and a low-reflection film mainly containing Al and functioning as an antireflective film which are sequentially arranged on a transparent substrate, a wiring terminal part provided at an end part of the laminated wiring and has the same laminated structure as that of the laminated wiring, and an insulating film for covering the laminated wiring and the wiring terminal part, in which the insulating film side serves as a display surface side, the wiring terminal part has a first opening part penetrating the insulating film and the low-reflection film and reaching the low-resistance conductive film, and an outer peripheral portion of the first opening part has a laminated structure of the low-resistance conductive film, the low-reflection film, and the insulating film, in at least one part.

Abstract: A semiconductor light emitting device including an active layer, a compound semiconductor layer on the active layer, a contact layer on the compound semiconductor layer, and an electrode on the contact layer, where the contact layer is substantially the same size as the electrode.

Abstract: An optoelectronic semiconductor component, the includes at least two optoelectronic semiconductor chips , which are located on a common mounting surface. An optical element is arranged downstream of the semiconductor chips in a main emission direction and is spaced from the semiconductor chips. In a direction transverse to the main emission direction the optical element has a transmission gradient in a transitional region. The transitional region does not overlap the semiconductor chips, when viewed in plan view onto the mounting surface.

Abstract: Light emitting elements (110) are situated on a film (210), then surrounded by a reflective structure (250) that is placed or formed on the film (210). Thereafter, the reflective structure (250) is filled with an encapsulant (270), affixing the light emitting element (110) within the reflective structure (250). The film (210) may then be removed, exposing the contacts (230) for coupling the light emitting element (110) to an external power source. The encapsulated light emitting elements (110) within the reflective structure (250) are diced/singulated to provide the individual light emitting devices. The encapsulant (270) may be molded or otherwise shaped to provide a desired optical function.

Abstract: A light emitting module including a substrate, a plurality of first light emitting diode (LED) chips and a plurality of second LED chips is provided. The substrate has a cross-shaped central region and a peripheral region surrounding the cross-shaped central region. The first LED chips are disposed on the substrate and at least located in the cross-shaped central region. The second LED chips are disposed on the substrate and at least located in the peripheral region. A size of each second LED chip is smaller than a size of each first LED chip. The number of the first LED chips located in the peripheral region is smaller than that in the cross-shaped central region. The number of the second LED chips located in the cross-shaped central region is smaller than that in the peripheral region.

Abstract: An optoelectronic semiconductor component includes a carrier which has an upper side and a lower side opposite to the upper side. At least one radiation-emitting semiconductor device is disposed on the upper side and has a radiation emission surface, through which at least a portion of the electromagnetic radiation, which is generated during operation of the semiconductor device, leaves the semiconductor device. A radiation-absorbing layer is arranged to absorb ambient light, which impinges upon the component, such that an outer surface of the component facing away from the carrier appears black at least in places.

Abstract: Provided are a light-emitting device package and a method of manufacturing the same. The light-emitting device package may include a plurality of light-emitting chips on one substrate (board). The plurality of light-emitting chips may produce colors around a target color. The target color may be produced by combinations of the colors of light emitted from the plurality of light-emitting chips. The colors around the target color may have the same hue as the target color and have color temperatures different from that of the target color. The plurality of light-emitting chips may have color temperatures within about ±250K of that of the target color.

Abstract: A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, a patterned sacrificial layer is utilized to form a self-aligned metallization stack and is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes.

Abstract: A light emitting device and manufacturing method thereof are disclosed. The light emitting device includes a substrate, a LED die, a first transparent layer, an optical wavelength conversion layer and a second transparent layer. The substrate has a die glue part. The LED die is disposed on the die glue part and has a base which is made of a transparent material. The first transparent layer is disposed on the side surface of the LED die. The optical wavelength conversion layer is evenly formed on the first transparent layer and the LED die. The second transparent layer is formed on the optical wavelength conversion layer.

Abstract: Light emitting devices comprising an optical layer comprising metal oxide particles having a polymer covalently bonded thereto and a light emitting layer, which is in optical communication with the optical layer are provided. Methods of fabricating a light emitting devices comprising: depositing an optical layer comprising metal oxide particles having a polymer covalently bonded thereto; and depositing a light emitting layer, which is in optical communication with the optical layer are also provided.

Abstract: According to an embodiment, a semiconductor light emitting device includes a semiconductor layer including a light emitting layer and a fluorescent substance excited by light emitted from the light emitting layer, a peak wavelength of a radiation spectrum of the light emitting layer at a room temperature being shorter than a peak wavelength of an excitation spectrum of the fluorescent substance.