Abstract: According to one embodiment, a semiconductor light emitting device includes a light emitting element, a phosphor layer, and a fluorescent reflection film. The phosphor layer has a transparent medium, a phosphor dispersed in the transparent medium, and a particle dispersed in the transparent medium. The phosphor is excited by the excitation light so as to emit a fluorescence. The particle is a magnitude of not more than 1/10 a wavelength of the excitation light. The particle has a different refractive index from a refractive index of the transparent medium. The fluorescent reflection film is provided between the light emitting element and the phosphor layer. The fluorescent reflection film has a higher reflectance with respect to a fluorescent wavelength of the phosphor, than a reflectance with respect to the wavelength of the excitation light.

Abstract: According to an embodiment, a method for manufacturing a semiconductor light emitting device includes steps for forming a fluorescent substance layer on a first face of a semiconductor layer and forming a light shielding film on the side face of the fluorescent substance layer. The fluorescent substance layer includes a resin and fluorescent substances dispersed in the resin, and have a light emitting face on a side opposite to the first face of the semiconductor layer and a side face connecting to the light emitting face with an angle of 90 degree or more between the light emitting face and the side face. The light shielding film shields a light emitted from a light emitting layer included in the semiconductor layer and a light radiated from the fluorescent substances.

Abstract: A light emitting diode includes a substrate, graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, a second electrode, and a reflection layer. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked on the substrate in sequence. The first electrode is electrically connected with the second semiconductor layer and the second electrode electrically is connected with the second part of the carbon nanotube layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer. The reflection layer covers the second semiconductor layer.

Abstract: An LED package structure includes a substrate and an LED chip formed on the substrate. The substrate has a first electrode and a second electrode formed on an upper surface thereof. The LED chip is formed on the first electrode of the substrate and electrically connected with the first electrode and the second electrode respectively. The substrate is made of a composite including a base material and ceramic fibers mixed in the base material.

Abstract: An LED light source device includes an LED light source, a first translucent structure covering the LED light source and a second translucent structure covering the first translucent structure. An interior of the first translucent structure has light scattering powder distributed therein. The LED light source is embedded in the first translucent structure. The LED light source is covered by the light scattering powder. The second translucent structure has a radius of R and an index of refraction of N1 , while the first translucent structure has a radius of r, wherein R, r and N1 satisfy the following relation: N1<R/(2r?R).

Abstract: Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, a third semiconductor layer between the active layer and the second conductive semiconductor layer, and a light extraction structure on the second conductive semiconductor layer. A top surface of the third semiconductor layer has a Ga-face.

Abstract: A method for manufacturing a light emitting diode (LED) package comprises: providing a substrate having a first electrode and a second electrode electrically insulated from the first electrode, wherein an LED die is mounted on the first electrode and electrically connected to the first electrode and the second electrode; forming a first encapsulant layer on the substrate to encapsulate the LED die therein, the first encapsulant layer being colloidal; forming a nitride compound phosphor layer distributed on an outer face of the first encapsulant layer; and heating the first encapsulant layer to solidify the first encapsulant layer. A second encapsulant layer is formed on the nitride compound phosphor layer to encapsulate the first encapsulant layer. An LED package formed by the method is also provided.

Abstract: A side-view LED package includes a substrate, a pair of electrodes connected to the substrate, an LED die electrically connected to the electrodes, a reflective cup formed on the substrate, an opening defined at a lateral side of the reflective cup, an encapsulation formed on the substrate to cover the LED die, and a reflective layer coated on a top of the encapsulation and a top of the reflective cup, wherein part of light emitting from the LED die is reflected by the reflective cup and the reflective layer and then emits out of the side-view LED package from the opening. The present disclosure also provides a method for manufacturing the side-view LED package described above.

Abstract: A patterned substrate includes a substrate and a plurality of protrusions. The protrusions are formed on the substrate. Each protrusion has a top face and a base. Each pair of immediately adjacent protrusions is minimally parted by 0 to 0.2 ?m. When the distance between the adjacent protrusions falls as 0 ?m, the bases thereof contact each other. A horizontal and a vertical light emitting diode structures using the patterned substrate are also discussed.

Abstract: A semiconductor light-emitting element includes: a laminated semiconductor layer in which an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer are laminated; a transparent conductive layer laminated on the p-type semiconductor layer of the laminated semiconductor layer and composed of a metal oxide having optical transparency to light emitted from the light-emitting layer; an insulating reflation layer laminated on the transparent conductive layer in which plural opening portions are provided to expose part of the transparent conductive layer; a metal reflection layer formed on the insulating reflection layer and inside the opening portions and composed of a metal containing aluminum; and a metal contact layer provided between the part of the transparent conductive layer exposed at the opening portion and the part of the metal reflection layer formed inside the opening portion, which contains an element selected from Group VIA and Group VIII of a periodic table.

Abstract: A method for producing at least one conversion lamina for a radiation-emitting semiconductor component is specified. A base material including a conversion substance contained therein is applied to a substrate by means of a double-layered stencil. Furthermore, a conversion lamina for a radiation-emitting semiconductor component includes a base material and a conversion substance embedded therein. The thickness of the conversion lamina is in a range of between 60 ?m and 170 ?m inclusive.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, a film covering a side face of the first metal pillar and a side face of the second metal pillar, and a resin layer. The semiconductor layer includes a light emitting layer, a first major surface, and a second major surface formed on a side opposite to the first major surface. The film has a solder wettability poorer than a solder wettability of the first metal pillar and a solder wettability of the second metal pillar. The resin layer covers at least part of the film.

Abstract: An embodiment of the disclosure includes a LED module. A substrate is provided. A light sensor is positioned in the substrate. A LED chip is attached to the substrate. The LED chip has a first side and a second side. The second side is covered by an opaque layer with an opening. The opening is substantially aligned with the light sensor. The light sensor receives a light output emitting from the LED chip through the opening.

Abstract: An emitting device including a first electrode, a second electrode spaced apart from the first electrode, an emitting pattern including a portion between the first electrode and the second electrode, and a block pattern including a portion between the emitting pattern and the first electrode and/or on a same level as the first electrode.

Abstract: Provided is a light-emitting device that has a high emission efficiency, excellent stability and temperature properties, and that generates light having a high color rendering property sufficient for practical use. This semiconductor light-emitting device (1) comprises a semiconductor light-emitting element (2) that emits blue light, a green phosphor (14) that absorbs the blue light and emits green light, and an orange phosphor (13) that absorbs the blue light and emits orange light, and is characterized in that the orange phosphor is an Eu-activated ?-SiAlON phosphor having an emission spectrum peak wavelength within a range of 595 to 620 nm.

Abstract: A light emitting diode includes a substrate, graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer is on the epitaxial growth layer of the substrate. The active layer is between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected with the second semiconductor layer and the second electrode electrically is connected with the second part of the carbon nanotube layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer.

Abstract: A light emitting diode includes a graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked with each other in sequence. The first electrode is located on and electrically connected with the second semiconductor layer. The second electrode is located on and electrically connected with the first semiconductor layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer.

Abstract: Various embodiments of light emitting dies and solid state lighting (“SSL”) devices with light emitting dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a light emitting die includes an SSL structure configured to emit light in response to an applied electrical voltage, a first electrode carried by the SSL structure, and a second electrode spaced apart from the first electrode of the SSL structure. The first and second electrode are configured to receive the applied electrical voltage. Both the first and second electrodes are accessible from the same side of the SSL structure via wirebonding.

Abstract: A light emitting device including a light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a first electrode disposed on the first conductive semiconductor layer, a conductive layer disposed on the second conductive semiconductor layer, a second electrode disposed on the conductive layer, a channel layer directly contacts with the light emitting structure and disposed at an adjacent region of the second electrode, a support substrate disposed on the channel layer, and wherein the conductive layer is separated into at least two unit conductive layers.

Abstract: A sapphire substrate having a principal surface for growing a nitride semiconductor to form a nitride semiconductor light emitting device comprises a plurality of projections on the principal surface. Each of the projections has a bottom that has a substantially polygonal shape. Each side of the bottom of the projections has a depression in its center. Vertexes of the bottoms of the respective projections extend in a direction that is within a range of ±10 degrees of a direction that is rotated counter-clockwise by 30 degrees from a crystal axis “a” of the sapphire substrate.

Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.

Abstract: Device structures, design structures, and fabrication methods for a silicon controlled rectifier. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. A doped region of a second conductivity type is formed in the well. A cathode of a silicon controlled rectifier and a cathode of a diode are formed in the device region. The silicon controlled rectifier comprises a first portion of the well and an anode comprised of a first portion of the doped region. The diode comprises a second portion of the well and an anode comprised of a second portion of the doped region.

Abstract: An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR.

Abstract: A bidirectional electrostatic discharge (ESD) protection device includes a substrate having a topside semiconductor surface that includes a first silicon controlled rectifier (SCR) and a second SCR formed therein including a patterned p-buried layer (PBL) including a plurality of PBL regions. The first SCR includes a first and second n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a first merged drain. The second SCR includes a third and a fourth n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a second merged drain. The plurality of PBL regions are directly under at least a portion of the sources while being excluded from being directly under either of the merged drains.

Abstract: A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the semiconductor surface by a lateral spacing distance. A first n+ diffusion region and a first p+ diffusion region are in the first nwell. A second n+ diffusion region is in the second nwell. A second p+ diffusion is between the first nwell and second nwell which provides a contact to the semiconductor surface. Dielectric isolation is between the first n+ diffusion region and first p+ diffusion region, along a periphery between the first nwell and the semiconductor surface, and along a periphery between the second nwell and the semiconductor surface. A resistor provides coupling between the second n+ diffusion region and second p+ diffusion.

Abstract: An epitaxial structure includes a substrate having an epitaxial growth surface, a first epitaxial layer, a graphene layer and a second epitaxial layer. The first epitaxial layer is stacked on the epitaxial growth surface. The graphene layer is coated on the first epitaxial layer. The second epitaxial layer is located on the first epitaxial layer and covers the graphene layer.

Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Abstract: A thin-body SOI CMOS structure and method for fabricating thin-body SOI CMOS structures with Si channels for NFETs and SiGe/Si or SiGe channels for PFETs. The CMOS structure imparts beneficial channel stress to PFETs while not degrading NFETs and leading to beneficial higher gate capacitance for PFETs.

Abstract: A thin-body SOI CMOS structure and method for fabricating thin-body SOI CMOS structures with Si channels for NFETs and SiGe/Si or SiGe channels for PFETs. The CMOS structure imparts beneficial channel stress to PFETs while not degrading NFETs and leading to beneficial higher gate capacitance for PFETs.

Abstract: A pseudomorphic high electron mobility transistor (pHEMT) comprises: a substrate comprising a Group III-V semiconductor material; buffer layer disposed over the substrate; and a channel layer disposed over the buffer layer. The buffer layer comprises microprecipitates of a Group V semiconductor element. A method of fabricating a pHEMT is also described.

Abstract: This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. One aspect of this disclosure is a bipolar transistor that includes a collector having a high doping concentration at a junction with the base and at least one grading in which doping concentration increases away from the base. In some embodiments, the high doping concentration can be at least about 3×1016 cm?3. According to certain embodiments, the collector includes two gradings. Such bipolar transistors can be implemented, for example, in power amplifiers.

Abstract: This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers.

Abstract: According to one embodiment, an electronic device includes a drive circuit on a semiconductor substrate, an insulating region including a first insulating part provided on the semiconductor substrate and formed of interlayer insulating films, and a second insulating part provided on the first insulating part, an element for a high-frequency provided on the insulating region and driven by the drive circuit, an interconnect including a first conductive part in the first insulating part, and a second conductive part in the second insulating part, and transmitting a drive signal from the drive circuit to the element, a first shield provided inside the insulating region and below the element, and a second shield provided inside the insulating region and below the second conductive part.

Abstract: A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure.

Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

Abstract: A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode.

Abstract: Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.

Abstract: The present application discloses a method for manufacturing a semiconductor structure, comprises the following steps: providing a substrate and forming a gate stack on the substrate; forming an offset spacer surround the gate stack and a dummy spacer surround the offset spacer; forming the S/D region on both sides of the dummy spacer; removing the dummy spacer and portions of the offset spacer on the surface of the substrate; forming a doped spacer on the sidewall of the offset spacer; forming the S/D extension region by allowing the dopants in doped spacer into the substrate; removing the doped spacer. Accordingly, the present application also discloses a semiconductor structure. In the present disclosure the S/D extension region with high doping concentration and shallow junction depth is formed by the formation of a heavily doped doped spacer, which can be removed in the subsequent procedures, in order to efficiently improve the performance of the semiconductor structure.

Abstract: A semiconductor device and a method for fabricating the same are disclosed. A fin of the semiconductor device including a fin-shaped channel region is configured in the form of a non-uniform structure, and a leakage current caused by the electric field effect generated in the semiconductor device is prevented from being generated, resulting in an increased operation stability of the semiconductor device.

Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.

Abstract: A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of aMOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of aMOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.

Abstract: A semiconductor module includes a semiconductor chip and a passive discrete component. The semiconductor chip includes on its top side and/or on the back side one or more contacts, which in its two-dimensional extent takes up the top side and/or the back side of the semiconductor chip virtually completely. The passive component, arranged in a package, is stacked on one of the contacts. The electrode of the passive component is electrically connected with one of the contacts. The counter electrode of the passive component is operatively connected with a control or signal electrode of the semiconductor chip or an electrode of a further semiconductor chip.

Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate; depositing a first material such that the first material overlaps the STI region and a portion of a top surface of the STI region is exposed; etching a recess in the STI region by a first etch, the recess having a bottom and sides; depositing a second material over the first material and on the sides and bottom of the recess in the STI region; and etching the first and second material by a second etch to form a floating gate of the device, wherein the floating gate extends into the recess.

Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.

Abstract: According to one exemplary implementation, a semiconductor device includes a channel, a source, and a drain situated in a first semiconductor fin. The channel is situated between the source and the drain. The semiconductor device also includes a control gate situated in a second semiconductor fin. A floating gate is situated between the first semiconductor fin and the second semiconductor fin. The semiconductor device can further include a first dielectric region situated between the floating gate and the first semiconductor fin and a second dielectric region situated between the floating gate and the second semiconductor fin.

Abstract: An apparatus of and method for making enhanced Schottky diodes having p-body regions operable to pinch a current flow path in a high-voltage n-well region and field plate structures operable to distribute an electric potential of the Schottky diode allow for a device with enhanced breakdown voltage properties. N-well regions implanted into the substrate over a p-type epitaxial layer may act as an anode of the Schottky diode and n-type well regions implanted in the high-voltage n-well regions may act as cathodes of the Schottky diode. The Schottky diode may also be used as a low-side mosfet structure device.

Abstract: A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.

Abstract: A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.