Abstract: A trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device includes a gate electrode embedded into a trench penetrating a base region. The gate electrode is disposed into a lattice shape in a planar view, and a protective diffusion layer is formed in a drift layer at the portion underlying thereof. At least one of blocks divided by the gate electrode is a protective contact region on which the trench is entirely formed. A protective contact for connecting the protective diffusion layer at a bottom portion of the trench and a source electrode is disposed on the protective contact region.

Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.

Abstract: Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.

Abstract: An integrated circuit can include first and second FETs of a particular conductivity type on a substrate, wherein a first source/drain region of the first FET is closer to a center of a first channel region of the first FET than a second source/drain region of the second FET is to a center of a second channel region of the second FET.

Abstract: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, and a channel region with a protrusion structure formed in the substrate of the first region, a gate insulating layer formed over the substrate, a first polysilicon layer filling the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.

Abstract: A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. A gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure.

Abstract: Semiconductor devices include a substrate, a first gate structure and a second gate structure positioned on the substrate, and a first source/drain formed in the substrate respectively at two sides of the first gate structure and a second source/drain formed in the substrate respectively at two sides of the second gate structure. The first gate structure and the second gate structure include a same conductivity type. The first source/drain and the second source/drain are different.

Abstract: A radiation-hardened transistor is formed in a p-type semiconductor body having an active region doped to a first level and surrounded by a dielectric filled shallow trench isolation region. N-type source/drain regions are disposed in the active region and spaced apart to define a channel. A gate is disposed above the channel, and is self-aligned with the source/drain regions. First and second p-type regions are disposed in the p-type semiconductor body on either side of one of the source/drain regions and are doped to a second level higher than the first doping level. The first and second p-type regions are self aligned with and extend outwardly from a first side edge of the gate. The ends of the gate extend past the first and second p-type regions.

Abstract: A semiconductor device manufacturing method includes: forming a first active region and a second active region in a semiconductor substrate; forming a first gate insulating film on the first active region and a second gate insulating film thinner than the first gate insulating film on the second active region by using material containing silicon oxide; forming first and second gate electrodes on the first and second gate insulating films respectively; forming an insulating film on the semiconductor substrate, and anisotropically etching the insulating film to leave first side wall insulating films on side walls of the first and second gate electrodes; removing the first side wall insulating film on the first gate electrode; and after removing the first side wall insulating film on the first gate electrode, thermally treating in an oxidizing atmosphere the semiconductor substrate to form a second side wall insulating film on the first gate electrode.

Abstract: A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance.

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more heavily doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where at least a portion of the second semiconductor region meets the first semiconductor region.

Abstract: An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.

Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

Abstract: A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.

Abstract: A semiconductor structure comprises: a first interlayer structure having a first dielectric layer and first contact vias; a second interlayer structure having a cap layer and second contact vias; and a third interlayer structure having a second dielectric layer and third contact vias. The first dielectric layer is flush with a gate stack or covers the gate stack, and the first contact vias penetrate through the first dielectric layer and are electrically connected with at least a portion of source/drain regions. The cap layer covers the first interlayer structure, and the second contact vias penetrate through the cap layer and are electrically connected with the first contact vias and the gate stack through a first liner. The second dielectric layer covers the second interlayer structure, and the third contact vias penetrate through the second dielectric layer and are electrically connected with the second contact vias through a second liner.

Abstract: Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.

Abstract: A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack.

Abstract: A microscale device comprises a patterned forest of vertically grown and aligned carbon nanotubes defining a carbon nanotube forest with the nanotubes having a height defining a thickness of the forest, the patterned forest defining a patterned frame that defines one or more components of a microscale device. A conformal coating of substantially uniform thickness at least partially coats the nanotubes, defining coated nanotubes and connecting adjacent nanotubes together, without substantially filling interstices between individual coated nanotubes. A metallic interstitial material infiltrates the carbon nanotube forest and at least partially fills interstices between individual coated nanotubes.

Abstract: A semiconductor device is formed such that a semiconductor substrate of the device has a non-uniform thickness. A cavity is etched at a selected side of the semiconductor substrate, and the selected side is then fusion bonded to another substrate, such as a carrier substrate. After fusion bonding, the side of the semiconductor substrate opposite the selected side is ground to a defined thickness. Accordingly, the semiconductor substrate has a uniform thickness except in the area of the cavity, where the substrate is thinner. Devices that benefit from a thinner substrate, such as an accelerometer, can be formed over the cavity.

Abstract: There are many inventions described and illustrated herein. In one aspect, present invention is directed to a thin film encapsulated MEMS, and technique of fabricating or manufacturing a thin film encapsulated MEMS including an integrated getter area and/or an increased chamber volume, which causes little to no increase in overall dimension(s) from the perspective of the mechanical structure and chamber. The integrated getter area is disposed within the chamber and is capable of (i) “capturing” impurities, atoms and/or molecules that are out-gassed from surrounding materials and/or (ii) reducing and/or minimizing the adverse impact of such impurities, atoms and/or molecules (for example, reducing the probability of adding mass to a resonator which would thereby change the resonator's frequency).

Abstract: According to one embodiment, a MEMS element comprises a first electrode fixed on a substrate, and a second electrode arranged above the first electrode, facing the first electrode, and vertically movable. The second electrode includes a second opening portion that penetrates from an upper surface to a lower surface of the second electrode. The first electrode includes a first opening portion at a position corresponding to at least a part of the second opening portion, the first opening portion penetrating from an upper surface to a lower surface of the first electrode.

Abstract: According to one embodiment, a MEMS device comprises a first electrode fixed on a substrate, a second electrode formed above the first electrode to face the first electrode, and vertically movable, a second anchor portion formed on the substrate and configured to support the second electrode, and a second spring portion configured to connect the second electrode and the second anchor portion. The second spring portion is continuously formed from an upper surface of the second electrode to an upper surface of the second anchor portion, and has a flat lower surface.

Abstract: A manufacturing method for hybrid integrated components having a very high degree of miniaturization is provided, which hybrid integrated components each have at least two MEMS elements each having at least one assigned ASIC element. Two MEMS/ASIC wafer stacks are initially created independently of one another in that two ASIC substrates are processed independently of one another; a semiconductor substrate is mounted on the processed surface of each of the two ASIC substrates, and a micromechanical structure is subsequently created in each of the two semiconductor substrates. The two MEMS/ASIC wafer stacks are mounted on top of each other, MEMS on MEMS. Only subsequently are the components separated.

Abstract: Hybrid integrated components including an MEMS element and an ASIC element are described, whose capacitor system allows both signal detection with comparatively high sensitivity and sensitive activation of the micromechanical structure of the MEMS element. The hybrid integrated component includes an MEMS element having a micromechanical structure which extends over the entire thickness of the MEMS substrate. At least one structural element of this micromechanical structure is deflectable and is operationally linked to at least one capacitor system, which includes at least one movable electrode and at least one stationary electrode. Furthermore, the component includes an ASIC element having at least one electrode of the capacitor system. The MEMS element is mounted on the ASIC element, so that there is a gap between the micromechanical structure and the surface of the ASIC element.

Abstract: A pressure sensor system comprising a pressure sensor chip is disclosed. The pressure sensor chip comprises a sensing side where pressure sensing is performed and one or more interconnections where electrical connections are made at the other side of the chip. The pressure sensor comprising an integrated circuit (1) forming a substrate, the substrate comprising a membrane shaped portion adapted for being exposed to the pressure, the integrated circuit (1) comprising both pressure signal sensing components and pressure signal processing components.

Abstract: A MEMS inertial sensor and a method for manufacturing the same are provided. The method includes: depositing a first carbon layer on a semiconductor substrate; patterning the first carbon layer to form a fixed anchor bolt, an inertial anchor bolt and a bottom sealing ring; forming a contact plug in the fixed anchor bolt and a contact plug in the inertial anchor bolt; forming a first fixed electrode, an inertial electrode and a connection electrode on the first carbon layer, where the first fixed electrode and the inertial electrode constitute a capacitor; forming a second carbon layer on the first fixed electrode and the inertial electrode; and forming a sealing cap layer on the second carbon layer and the top sealing ring. Under an inertial force, only the inertial electrode may move, the fixed electrode will almost not move or vibrate, which improves the accuracy of the MEMS inertial sensor.

Abstract: A method for producing an optical window device for a MEMS device, including applying a layer made of a transparent material onto a substrate having a recess, and deforming the layer so that it is folded and the deformed area of the layer forms an optical window.

Abstract: A MEMS device is described. The device includes a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, a semiconductor substrate including a second bonding layer, and a cap including a third bonding layer, the cap coupled to the semiconductor substrate by bonding the second bonding layer to the third bonding layer. The first bonding layer includes silicon, the semiconductor substrate is electrically coupled to the MEMS substrate by bonding the first bonding layer to the second bonding layer, and the MEMS substrate is hermetically sealed between the cap and the semiconductor substrate.

Abstract: An environment-resistant module which provides both thermal and vibration isolation for a packaged micromachined or MEMS device is disclosed. A microplatform and a support structure for the microplatform provide the thermal and vibration isolation. The package is both hermetic and vacuum compatible and provides vertical feedthroughs for signal transfer. A micromachined or MEMS device transfer method is also disclosed that can handle a wide variety of individual micromachined or MEMS dies or wafers, in either a hybrid or integrated fashion. The module simultaneously provides both thermal and vibration isolation for the MEMS device using the microplatform and the support structure which may be fabricated from a thin glass wafer that is patterned to create crab-leg shaped suspension tethers or beams.

Abstract: To provide a combined sensor that can detect a plurality of physical quantities. With the combined sensor, it is possible to realize, while maintaining performance, a reduction in size and a reduction in costs by increasing elements that can be shared among respective sensors. A weight M2 and a detection electrode DTE2 used in an angular-velocity detecting section are also used as a reference capacitive element of a Z-direction-acceleration detecting section configured to detect acceleration in a Z direction. That is, in the Z-direction-acceleration detecting section, a detection capacitive element including the weight M2 and the detection electrode DTE2 configuring the angular-velocity detecting section is used as a reference capacitive element for a detection capacitive element formed by a detection electrode DTE5 and a weight M4.

Abstract: A MEMS device, such as a microphone, uses a perforated plate. The plate comprises an array of holes across the plate area. The plate has an area formed as a grid of polygonal cells, wherein each cell comprises a line of material following a path around the polygon thereby defining an opening in the centre. In one aspect, the line of material forms a path along each side of the polygon which forms a track which extends at least once inwardly from the polygon perimeter towards the centre of the polygon and back outwardly to the polygon perimeter. This defines a meandering hexagon side wall, which functions as a local spring suspension.

Abstract: Disclosed is an ultrasonic probe comprising: CMUT cells (13) that mutually convert ultrasonic waves and electrical signals; a semiconductor substrate (15) that has a plurality of the CMUT cells (13) formed on the surface thereof; an acoustic lens (3) that is provided on the front face side of the CMUT cells (13); and a backing layer (5) that is provided on the rear face side of the semiconductor substrate (15). The backing layer (5) is formed by a first backing layer (27) that makes contact with the semiconductor substrate, and a second backing layer (29) that is provided on the rear face side of the backing layer (27). The acoustic impedance of the backing layer (27) is set based on the sheet thickness of the semiconductor substrate (15). The backing layer (29) is formed by attenuating material capable of attenuating ultrasonic waves transmitted through the backing layer (27).

Abstract: A micromechanical component, in particular a micromechanical sensor having a carrier substrate and having a cap substrate, and a manufacturing method are provided. The carrier substrate and the cap substrate are joined together with the aid of a eutectic bond connection or by a metallic solder connection or a glass solder connection (e.g., glass frit), in an edge area of the carrier substrate and the cap substrate. The connection of the carrier substrate and the cap substrate is established with the aid of connecting areas, and a stop trench or a stop protrusion or both a stop trench and a stop protrusion are situated within the edge areas in the bordering areas.

Abstract: A magnetic body device has a stacked structure comprising an underlying layer, a magnetic body layer, and a cap layer. The material for the underlying layer is different from that for the cap layer. The magnetic body layer has a free magnetization region having perpendicular magnetic anisotropy and a first characteristic change region and a second characteristic change region situated on both sides of the free magnetization region in a first in-plane direction. The perpendicular magnetic anisotropy of the first characteristic change region and the second characteristic change region is at a level lower than that of the free magnetization region. An external magnetic field containing a component in the first in-plane direction is applied to the free magnetization region. Further, a current in the first in-plane direction is supplied to the free magnetization region.

Abstract: In one embodiment a magnetic memory includes a memory device base and a plurality of memory cells disposed on the memory cell base, where each memory cell includes a layer stack comprising a plurality of magnetic and electrically conductive layers arranged in a stack of layers common to each other memory cell. The magnetic memory further includes an implanted matrix disposed between the memory cells and surrounding each memory cell, where the implanted matrix includes component material of the layer stack of each memory cell inter mixed with implanted species, where the implanted matrix comprises a non-conducting material and a non-magnetic material, wherein each memory cell is electrically and magnetically isolated from each other memory cell.

Abstract: A magnetic memory device is provided. The magnetic memory device includes a first vertical magnetic layer and a second vertical magnetic layer on a substrate, a tunnel barrier layer between the fist vertical magnetic layer and the second vertical magnetic layer, and an exchange-coupling layer between a first sub-layer of the first vertical magnetic layer and a second sub-layer of the first vertical magnetic layer.

Abstract: A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment a first color filter is formed over a first photosensitive diode and a second color filter is formed over a second photosensitive diode, and a gap is formed between the first color filter and the second color filter. The gap will serve to reflect light that otherwise would have crossed from the first color filter to the second color filter, thereby reducing cross-talk between the first photosensitive diode and the second photosensitive diode. A reflective grid may also be formed between the first photosensitive diode and the second photosensitive diode in order to assist in the reflection and further reduce the amount of cross-talk.

Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.

Abstract: A method for reducing cross talk in image sensors comprises providing a backside illuminated image sensor wafer, forming an isolation region in the backside illuminated image sensor wafer, wherein the isolation region encloses a photo active region, forming an opening in the isolation region from a backside of the backside illuminated image sensor wafer and covering an upper terminal of the opening with a dielectric material to form an air gap embedded in the isolation region of the backside illuminated image sensor wafer.

Abstract: There is provided a photosensitive transparent composition for a color filter of a solid-state imaging device, containing (A) a photopolymerization initiator, (B) a polymerizable compound, and (C) an alkali-soluble resin, wherein the cured film obtained from the photosensitive transparent composition has a refractive index of 1.60 to 1.90 for light at a wavelength of 633 nm.

Abstract: Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.

Abstract: Techniques are described for forming a waveguide photodetector. In one example, a method of forming a waveguide photodetector includes forming a waveguide on a substrate, e.g., silicon on insulator, depositing a first oxide coating over the waveguide and on the SOI substrate, creating a seed window through the first oxide coating to a bulk silicon layer of the SOI substrate, depositing a photodetector material into the seed window and on top of the first oxide coating over the waveguide, depositing a second oxide coating over the photodetector material and over the first oxide coating deposited over the waveguide and on the SOI substrate, and applying thermal energy to liquefy the photodetector material.

Abstract: An image sensor package and image sensor chip capable of being slenderized while enhancing the reliability with respect to physical impact are provided. The image sensor package includes an image sensor chip provided with a pixel domain at a central portion of an upper surface thereof, a substrate disposed at an upper side of the image sensor chip so as to be flip-chip bonded with respect to the image sensor chip, provided with a hole formed at a position corresponding to the pixel domain, and formed of organic material, a printed circuit board at which the substrate provided with the image sensor chip bonded thereto is mounted, and a solder ball configured to electrically connect the substrate to the printed circuit board.

Abstract: A semiconductor device comprising a first semiconductor section including a first wiring layer at one side thereof, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other, a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication.

Abstract: Embodiments relate to photo cell devices. In an embodiment, a photo cell device includes an array of transmission layers having different optical thicknesses and with photo diodes underneath. The transmission layers can include two different materials, such as a nitride and an oxide, that cover each diode with a different proportional area density in a damascene-like manner. Embodiments provide advantages over conventional devices, including that they can be integrated into a standard CMOS process and therefore simpler and less expensive to produce.

Abstract: A solid state imaging device 1 is provided with a photoelectric conversion portion 2 having photosensitive regions 13, and a potential gradient forming portion 3 arranged opposite to the photosensitive regions 13. A planar shape of each photosensitive region 13 is a substantially rectangular shape composed of two long sides and two short sides. The photosensitive regions 13 are juxtaposed in a first direction intersecting with the long sides. The potential gradient forming portion 3 has a first potential gradient forming region to form a potential gradient becoming lower along a second direction from one of the short sides to the other of the short sides, and a second potential gradient forming region to form a potential gradient becoming higher along the second direction. The second potential gradient forming region is arranged next to the first potential gradient forming region in the second direction.

Abstract: In a semiconductor device including unit cells which are aligned in one direction, wirings disposed along end portions in the one direction have high Young's moduli.