Abstract: The present disclosure provides a semiconductor device including a semiconductor element having a first surface and a second surface, which is opposite to the first surface, and a conductive via disposed on the semiconductor element. The semiconductor element includes a die; a first redistribution layer positioned on the first surface, wherein the first redistribution layer is configured to fan out the die; and a second redistribution layer positioned on the second surface of the semiconductor element. The conductive via is configured to electrically connect the first redistribution layer and the second redistribution layer, wherein the sizes of the two ends of the conductive via are different and the die can be electrically coupled to another semiconductor device through the conductive via.

Abstract: An integrated circuit (IC) includes a packaging body, multiple interface connectors, a functional chip, and an electrostatic discharge (ESD) protection chip. The interface connectors are located on an outer surface of the packaging body. The functional chip has an electronic functional circuit, and the ESD protection chip has an ESD protection circuit. The ESD protection circuit is connected electrically to an interface connector serving as a data exchange path.

Abstract: A circuit assembly includes a plurality of integrated circuits having stud bumps at each input/output pad, an interconnection circuit having wells filled with solder, said wells corresponding in a one-to-one relationship with said stud bumps of said integrated circuits, and electrical and mechanical bonding at each of said input/output pads, wherein each of said stud bumps connects with solder in each of said wells to form a permanent connection.

Abstract: A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.

Abstract: A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.

Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.

Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Abstract: A semiconductor device includes: a plurality of semiconductor chips to be mutually bonded via a bonding resin; a sealing resin to seal the plurality of semiconductor chips; and an anchor to be disposed in a first semiconductor chip included by the plurality of semiconductor chips and to seize the bonding resin.

Abstract: The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.

Abstract: Problem To improve the electromigration (EM) resistance of a solder joint. Solution The present invention provides a unique structure for an interfacial alloy layer which is able to improve the electromigration (EM) resistance of a solder joint, and a unique method of forming this structure. More specifically, in this unique structure, a controlled interfacial alloy layer is provided on both sides of a solder joint. In order to form this structure, aging (maintenance of high-temperature conditions) is performed until an interfacial alloy layer of Cu3Sn has a thickness of at least 1.5 ?m.

Abstract: A semiconductor package may include a semiconductor chip mounted on a substrate, a molding part protecting the semiconductor chip and having a top surface at a substantially equal height to a top surface of the semiconductor chip, a heat exhausting part on the molding part and the semiconductor chip, and an adhesive part between the heat exhausting part and the molding part and between the heat exhausting part and the semiconductor chip. An interface between the heat exhausting part and the adhesive part has a concave-convex structure.

Abstract: Disclosed herein are a semiconductor chip package and a manufacturing method thereof. The manufacturing method of the semiconductor chip package includes: a) mounting a semiconductor chip on a printed circuit board (PCB); b) inserting a warpage suppressing reinforcement member into an inner ceiling of a mold manufactured in order to package the PCB having the semiconductor chip mounted thereon; c) combining the mold having the warpage suppressing reinforcement member inserted into the ceiling thereof with the upper surface of the PCB so as to surround the PCB having the semiconductor chip mounted thereon; d) injection-molding and filling a molding material in the mold, and hardening the molding material by applying heat, and e) hardening the molding material and then removing the mold to complete the semiconductor chip package.

Abstract: A packaged device, wherein at least one sensitive portion of a chip is enclosed in a chamber formed by a package. The package has an air-permeable area having a plurality of holes and a liquid-repellent structure so as to enable passage of air between an external environment and the chamber and block the passage of liquids.

Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

Abstract: A packaged semiconductor device, comprising a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.

Abstract: A multi-chip module and a method for manufacturing the multi-chip module that mitigates wire breakage. A first semiconductor chip is mounted and wirebonded to a support substrate. A spacer is coupled to the first semiconductor chip. A support material is disposed on the spacer and a second semiconductor chip is positioned on the support material. The second semiconductor chip is pressed into the support material squeezing it into a region adjacent the spacer and between the first and second semiconductor chips. Alternatively, the support material is disposed on the first semiconductor chip and a die attach material is disposed on the spacer. The second semiconductor chip is pressed into the die attach material and the support material, squeezing a portion of the support material over the spacer edges. Wirebonds are formed between the support substrate and the first and second semiconductor chips.

Abstract: A method of attaching an IC wafer having a plurality of copper pillars (“CuP's) projecting from one face thereof to a substrate having a plurality of contact pads on one face thereof including applying a film having a substantial amount of filler particles therein to the one face of the wafer; applying an a-stage resin having substantially no filler particles therein to the one face of the substrate; and interfacing the film with the a-stage resin.

Abstract: A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar.

Abstract: A device includes a metal pad, and a passivation layer including portions overlapping edge portions of the metal pad. A Post-Passivation-Interconnect (PPI) includes a trace portion overlying the passivation layer, and a pad portion connected to the trace portion. A polymer layer includes an upper portion over the PPI, and a plug portion extending into, and encircled by, the pad portion of the PPI.

Abstract: The present invention provides a semiconductor package structure, which includes a die, a plurality of bonding wires, an encapsulant, and a plurality of first external terminals. The die has an active surface and a back surface. A first end of each of the bonding wires is connected to the back surface of the die, and a second end opposite to the first end is electrically connected to the active surface of the die. The encapsulant covers the back surface of the die and the bonding wires, wherein a portion of each of the bonding wires is exposed from the encapsulant. The first external terminals are disposed on the top surface of the encapsulant, and cover the exposed portions of the bonding wires respectively and are electrically connected to the bonding wires.

Abstract: A semiconductor package with improved redistribution layer design and fabricating method thereof are disclosed and may include a semiconductor die comprising bond pads, a first redistribution layer (RDL) formed on the semiconductor die. The first RDL has a first end coupled to a bond pad and a second end coupled to a solder bump via under bump metal layers. A second RDL is formed in a same plane of the semiconductor die as the first RDL and is electrically isolated from the first RDL. A first end of the second RDL may be coupled to a bond pad and the second RDL may pass underneath, but be electrically isolated from, the solder bump. A passivation layer may be formed on the first and second RDLs exposing the second end of the first RDL. The under bump metal layers may be formed on the second end of the first RDL exposed by the passivation layer.

Abstract: Copper (Cu)-to-Cu bonding techniques are provided. In one aspect, a bonding method is provided. The method includes the following steps. A first bonding structure is provided having at least one copper pad embedded in a first insulator and at least one via in the first insulator over the copper pad, wherein the via has tapered sidewalls. A second bonding structure is provided having at least one copper stud embedded in a second insulator, wherein a portion of the copper stud is exposed for bonding and has a domed shape. The first bonding structure is bonded to the second bonding structure by way of a copper-to-copper bonding between the copper pad and the copper stud, wherein the via and the copper stud fit together like a lock-and-key. A bonded structure is also provided.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed.

Abstract: A method for manufacturing a package on package structure includes the steps of: providing a connection substrate comprising a main body and electrically conductive posts, the main body comprising a first surface and an opposite second surface, each electrically conductive post passing through the first and second surfaces, and each end of the two ends of the electrically conductive post protruding from the main body; arranging a first package device on a side of the first surface of the connection substrate, arranging a package adhesive on a side of the second surface of the connection substrate, thereby obtaining a semi-finished package on package structure; and arranging a second package device on a side of the package adhesive furthest from the first package device, thereby obtaining a package on package structure.

Abstract: A method of manufacturing a chip fan-out structure, said method includes forming a dry film with a predetermined pattern. Providing a chip wherein the distribution of the pad is corresponding to the dry film's predetermined pattern. Contacting the surface of the pad with the dry film. Forming a molding compound to encapsulate the chip, and removing the dry film to expose the pads.

Abstract: Disclosed are photo sensitizers that include a polyol moiety covalently bonded to a fused aromatic moiety. Also disclosed is a method for improving UV laser ablation performance of a coating, such as a cationic UV curable coating, by incorporating an oxalyl-containing additive into the cationic UV curable or other coating. Oxalyl-containing sensitizers having the formula Q-O—C(O)—C(O)—O—R1 wherein Q represents a fused aromatic moiety and R1 is an alkyl or aryl group, are also disclosed, as are oxalyl-containing oxetane resins, oxalyl-containing polyester polyols, and cationic UV curable coating formulations that include oxalyl-containing additives.

Abstract: A semiconductor structure includes a semiconductor substrate, a metal layer formed on the semiconductor substrate, a conductive pillar, and a solder ball. The conductive pillar is formed on and electrically connected with the metal layer, wherein the conductive pillar has a bearing surface and a horizontal sectional surface under the bearing surface, and the contact surface area of the bearing surface is larger than the area of the horizontal sectional surface. The solder ball is located on the conductive pillar and covers the bearing surface.

Abstract: A semiconductor device includes a metal line and a metal pad formed at different integration levels of a semiconductor substrate, and an isolation layer by which the metal line and the metal pad are spaced apart from each other. The semiconductor device prevents short-circuiting between the metal pad and the metal line although the isolation layer is dislocated.

Abstract: A plastic ball grid array package having a reinforcement resin that may address the problem of delamination and cracks in a boundary region between a sealing resin and a substrate. The reinforcement resin is formed at an outer region of a sealing resin and has a height that is lower than that of the sealing resin. The reinforcement resin may be formed of the same material used to form the sealing resin and has a structure completely covering a first surface of the substrate. Accordingly, cracks and delamination defects of the semiconductor package may be reduced by absorbing stress that occurs by physical impact in a boundary region between the substrate and the sealing resin.

Abstract: A sintered connection is formed by pressing a semiconductor die against a substrate with a dried sintering material interposed between the substrate and the semiconductor die, the dried sintering material having sintering particles and a solvent. The substrate is heated to a temperature below a sintering temperature of the dried sintering material while the semiconductor die is pressed against the substrate to form local sinter connections between adjacent ones of the sintering particles. The local sinter connections collectively provide a stable joint that fixes the semiconductor die to the substrate prior to sintering. A sintered connection is then formed between the semiconductor die and the substrate from the dried sintering material, after the stable joint is formed.

Abstract: A method of making a semiconductor device can comprise forming a copper bond pad on an integrated circuit device; forming a first passivation layer on the integrated circuit device and the copper bond pad; forming a second passivation layer on the first passivation layer; forming a mask over the first and second passivation layers around the copper bond pad; etching the second passivation layer over the copper bond pad; and cleaning the first passivation layer over the copper bond pad. At least a portion of the first passivation layer remains over the copper bond pad after the etching the second passivation layer. A thickness of the first passivation layer over the copper bond pad is selected to protect the copper bond pad from oxidation and to allow wire bonding to the copper bond pad through the first passivation layer.

Abstract: A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating layer to provide recesses in the insulating layer above each of the electrical contacts, and depositing a deformable conductive material in each of the recesses. A mating IC is provided which includes conductive pins, preferably comprising nickel, positioned to align with the deformable conductive material in respective ones of the recesses on the first chip. The first and mating ICs are then hybridized by bringing the conductive pins into contact with the deformable conductive material in the recesses, such that the conductive material deforms and the pins make electrical contact with the first IC's electrical contacts.

Abstract: In a method for making graphitic ribbons in a face of a carbide crystal (110), in which an elongated trench (120) is formed along a predetermined path in the face (112) of the carbide crystal (110), the trench (120) including a horizontal floor (124) coupling two vertical walls (122), the trench (120) following a path on which it is desired to form a graphitic ribbon (130). The carbide crystal (110) and the trench (120) are subjected to an annealing environment for an amount of time sufficient to cause a graphene ribbon (130) having a V-shaped cross section to form along the predetermined path of the trench (120).

Abstract: An aluminum interconnection apparatus comprises a metal structure formed over a substrate, wherein the metal structure is formed of a copper and aluminum alloy, a first alloy layer formed underneath the metal structure and a first barrier layer formed underneath the first alloy layer, wherein the first barrier layer is generated by a reaction between the first alloy layer and an adjacent dielectric layer during a thermal process.

Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

Abstract: A method of forming an integrated circuit device includes forming a diffusion barrier layer in an opening defined in a substrate; forming a highly doped copper alloy seed layer over the diffusion barrier layer, the copper alloy seed layer having a minority alloy component having a concentration greater than 0.5% atomic; and forming a copper layer over the copper alloy seed layer so as to define a wiring structure of the integrated circuit device.

Abstract: According to one embodiment, a semiconductor device includes an insulating film, a catalytic layer and a wiring layer. The insulating film has a hole. The catalytic layer is formed at the bottom of the hole, at the peripheral wall of the hole, and on the upper surface of the insulating film outside the hole. A contact is formed of a carbon nanotube provided on the portion of the catalytic layer at the bottom of the hole. The wiring layer is formed of graphene and provided on the catalytic layer outside the hole in contact with the carbon nanotube. The catalytic layer at the bottom of the hole is a perforated film, and the catalytic layer outside the hole is a continuous film.

Abstract: A semiconductor device includes a lower conductor having a lower conductor sidewall, a barrier film having a barrier film sidewall formed directly on the lower conductor sidewall, and a via formed on a top surface of the lower conductor. A top portion of the barrier film sidewall is recessed, such that a top surface of the barrier film sidewall is at a level lower than the top surface of the lower conductor.

Abstract: The present disclosure relates diffusion barrier layers for backend layers for interconnects and their methods of manufacturing. A TaNx/Ta diffusion barrier layer used for backend interconnect is formed at a temperature between about 150-450° C. wherein the Ta film exhibits a body-centered-cubic (BCC) structure and a lower electrical resistivity. Other embodiments are described and claimed.

Abstract: One embodiment of the present invention is a device including at least a portion of a void-free electroplated metallic interconnect embedded in an opening, said opening having sidewalls, said sidewalls include at least one dielectric layer, wherein the opening has an aspect ratio in a range from 7:1 to 20:1, and wherein the portion of the electroplated metallic interconnect includes a material selected from a group consisting of Cu, Ag, and alloys including at least one of these metals.

Abstract: A semiconductor device includes: a first insulating film formed on a semiconductor substrate; a first interconnect formed on the first insulating film; a second insulating film formed on the first insulating film to cover the first interconnect; and a second interconnect formed on the second insulating film. The second interconnect includes a barrier layer formed on the second insulating film, and a plated layer formed on the barrier layer. The barrier layer prevents diffusion of atoms forming the plated layer into the second insulating film, and has a greater width than the plated layer.

Abstract: A method of manufacturing comprising providing a semiconductor layer having metal adhesion layer on a planar surface of the semiconductor layer and an alloy layer on the metal adhesion layer, the alloy layer comprising an alloy of gold and a non-gold metal. The method comprises removing a portion of the non-gold metal from the alloy layer to form a porous gold layer. The method comprises applying pressure between the porous gold layer and a metal layer to form a bond between the semiconductor layer and the metal layer.

Abstract: A semiconductor device includes: a contact hole formed over a structure including a conductive pattern; a contact plug formed in the contact hole; a first metal silicide film surrounding the contact plug; and a second metal silicide film formed over the contact plug.

Abstract: A semiconductor device includes a recess in a polymer layer between two adjacent metal lines and over passivation layer or anti-electromigration layers on redistribution metal lines to increase the resistance to electromigration.

Abstract: An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanr with a top surface of the first metal line.

Abstract: Embodiments of the invention provide an approach for bottom-up growth of a low resistivity gate conductor. Specifically, a low resistivity metal (e.g., aluminum or cobalt) is selectively grown directly over metal layers in a set of gate trenches using a chemical vapor deposition or atomic layer deposition process to form the gate conductor.

Abstract: An integrated circuit device includes spaced apart conductive patterns on a substrate surface, and a supporting pattern on the substrate surface between adjacent ones of the conductive patterns and separated therefrom by respective gap regions. The adjacent ones of the conductive patterns extend away from the substrate surface beyond a surface of the supporting pattern therebetween. A capping layer is provided on respective surfaces of the conductive patterns and the surface of the supporting pattern. Related fabrication methods are also discussed.

Abstract: This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.

Abstract: An interconnection structure for being formed on bonding pads of a substrate in a semiconductor package is provided. The interconnection structure includes a nickel layer formed on each of the bonding pads, a metal layer formed on the nickel layer, and a solder material formed on the metal layer. The metal layer is made of one of gold, silver, lead and copper, and has a thickness in the range of 0.5 to 5 um. As such, when the solder material is reflowed to form solder bumps, no nickel-tin compound is formed between the solder bumps and the metal layer, thereby avoiding cracking or delamination of the solder bumps.

Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate. A lower-layer wiring is provided above a surface of the semiconductor substrate. An interlayer dielectric film is provided on the lower-layer wiring and includes a four-layer stacked structure. A contact plug contains aluminum. The contact plug is filled in a contact hole formed in the interlayer dielectric film in such a manner that the contact plug reaches the lower-layer wiring. Two upper layers and two lower layers in the stacked structure respectively have tapers on an inner surface of the contact hole. The taper of two upper layers and the taper of two lower layers have different angles from each other.