Abstract: An IC chip package and a chip-on-glass structure using the same are provided. The IC chip package includes an IC chip having a circuit surface, and plural copper (Cu) bumps formed on the circuit surface. Moreover, a non-conductive film (NCF) could be formed on the circuit surface to cover the Cu bumps. The chip-on-glass structure includes a glass substrate, plural electrodes such as aluminum (Al) electrodes formed on the glass substrate, and a conductive film formed on the electrodes. The conductive film contains a number of conductive particles. When the IC chip package is coupled to the glass substrate, the Cu bumps can be coupled to the corresponding electrodes via conductive particles.

Abstract: Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

Abstract: An integrated circuit package includes a package module formed from successive build-up layers which define circuit interconnections, a cavity formed on a top-side of the package module, a chip having a front side with forward contacts and having a back-side, the chip disposed such that in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and a top layer coupled to the back-side of the chip covering at least a part of the chip and the top-side of the package module.

Abstract: A semiconductor device includes a substrate, first and second bond pad structures supported by the substrate and spaced from one another by a gap, and a wire bond foot jumper extending across the gap and bonded to the first and second bond pad structures.

Abstract: A manufacturing method of a package carrier includes the following steps. Firstly, two base metal layers are bonded together. Then, two supporting layers are laminated onto the base metal layers respectively. Next, two release metal films are disposed on the supporting layers respectively, wherein each of the release metal films includes a first metal film and a second metal film separable from each other. Next, two patterned metal layers are formed on the release metal films respectively, wherein each of the patterned metal layers is suitable for carrying and electrically connected to a chip. Then, the base metal layers are separated from each other to form two package carriers independent from each other. A package carrier formed by the manufacturing method described above is also provided.

Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

Abstract: An apparatus for a stacked silicon interconnect technology (SSIT) product comprises an interposer die, a plurality of integrated circuit dies, a plurality of active components forming an active connection between the integrated circuit dies and the interposer die, and a plurality of dummy components at the interposer die, the dummy components not forming an active connection between the integrated circuit dies and the interposer die. At least a subset of the dummy components forms a pattern, and the pattern comprises an identifier for the interposer die.

Abstract: A semiconductor device includes a substrate (102) with a cavity (112) formed therein for receiving a semiconductor die. In examples, the semiconductor die is a controller die (114). The controller die (114) may be electrically connected to the substrate (102) with electrical traces (120) which may be formed for example by printing. After the controller die (114) is electrically connected to the substrate (102), one or more memory die (150) may be affixed to the substrate (102), over the cavity (112) and controller die (114).

Abstract: A method is disclosed that includes the steps outlined below. A first oxide layer is formed to divide a first semiconductor substrate into a first part and a second part. A second oxide layer is formed on the first part of the first semiconductor substrate. The first oxide layer is bonded to a third oxide layer of a second semiconductor substrate. The second part of first semiconductor substrate and the first oxide layer are removed to expose the first part of the first semiconductor substrate.

Abstract: The instant disclosure provides a light-emitting module and a method of manufacturing a single light-emitting structure. The light-emitting module includes two identical light-emitting structures disposed on the same plane. One of the two light-emitting structures disposed on the plane is rotated by 180 degrees relative to the other light-emitting structure, and the two light-emitting structures are connected to each other. Each light-emitting structure includes a base, a conducting element, a light-emitting element and an encapsulation element. The conducting element includes a plurality of conductors separated from each other and passing through the base body, where the number of the conductors is N and N>1. The light-emitting element includes at least one light-emitting chip electrically connected between at least two of the conductors. The encapsulation element includes a transparent encapsulation body disposed on the base to cover the conducting element and the light-emitting element.

Abstract: An integrated circuit for controlling a boost converter. The integrated circuit includes a gate pin, a source pin, a feedback pin, a current mirror sub-circuit, and a control sub-circuit. The current mirror sub-circuit is connected to the source pin to produce an output current from a reference current flowing between the source pin and ground, the reference current being larger than the output current. The control sub-circuit is connected to the current mirror sub-circuit, the gate pin and the feedback pin to control a gate voltage provided to the gate pin based on the output current and a feedback voltage at the feedback pin.

Abstract: An integrated circuit ESD protection circuit (270) is formed with a combination device consisting of a gated diode (271) and an output buffer MOSFET (272) where the body tie fingers of a first conductivity type (307) are formed in the substrate (301, 302) and isolated from the drain regions of a second conductivity type (310) using a plurality of diode poly fingers (231, 232) which are interleaved with a plurality of poly gate fingers (204, 205) forming the output buffer MOSFET (272).

Abstract: A semiconductor device according to the embodiments includes: a first normally-off transistor including a first source terminal, a first drain terminal, and a first gate terminal; a normally-on transistor including a second source terminal connected to the first drain terminal, a second drain terminal, and a second gate terminal connected to the first source terminal; a protection element provided between the first gate terminal and the second drain terminal, and having breakdown voltage lower than breakdown voltage of the normally-on transistor; and a first diode including a first anode connected to the second drain terminal and a first cathode connected to the protection element.

Abstract: Fin contacted electrostatic discharge (ESD) devices with improved heat distribution and methods of manufacture are disclosed. The method includes forming a plurality of fins on a substrate which is aligned with at least one well region in the substrate. The method further includes forming at least one electrostatic discharge (ESD) device spanning two or more of the plurality of fins. The forming of the ESD device includes forming an epitaxial material spanning the two or more of the plurality of fins and forming one or more contacts on the epitaxial material.

Abstract: Devices, systems and methods are provided for switching a load with true reverse current blocking (TRCB). The device may include an input port coupled to a supply voltage; an output port coupled to the load; a TRCB circuit coupled to the input port and the output port; and a switch control port coupled to the TRCB circuit. The TRCB circuit may be configured to couple the input port to the output port in response to a switch close signal applied to the switch control port and to de-couple the input port from the output port in response to a switch open signal applied to the switch control port. The TRCB circuit may further be configured to block current flow from the output port to the input port in response to both the switch open signal and the switch close signal.

Abstract: There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device may be configured to include one or both of a reduced output resistance due to, for example, a modified body implant and a reduced transconductance due to, for example, a modified oxide thickness to cause a gain of the composite semiconductor device to be less than approximately 10,000.

Abstract: A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.

Abstract: Various aspects of the technology include an integrated circuit device comprising a compound semiconductor layer and a plurality of input, switch, and ground ohmic metal fingers fabricated on the compound semiconductor layer in a repeating sequence. A control gate may be disposed between each input finger and adjacent switch finger, and a sync gate may be disposed between each ground finger and adjacent switch finger. A sync gate and a control gate may be disposed adjacent each switch finger. The device further includes a plurality of control gate pads, each control gate pad at an end of two control gates, and a control gate pad at opposite ends of each control gate, and a plurality of sync gate pads, each sync gate pad at an end of two sync gates, and a sync gate pad at opposite ends of each sync gate.

Abstract: A method of fabricating a semiconductor device includes forming a first metal gate electrode over a substrate, forming a second metal gate electrode over the substrate, removing at least a part of the first metal gate electrode to form a first opening, and filling the first opening with a non-conductive material.

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (104), a resistance value of the resistance variable layer varying reversibly according to an electric signal applied between the electrodes (103), (105), and the resistance variable layer (104) comprises at least a tantalum oxide, and is configured to satisfy 0<x<2.5 when the tantalum oxide is represented by TaOx.

Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Abstract: The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.

Abstract: A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.

Abstract: A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face.

Abstract: Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer (10) in region B is also grown from the surface of a substrate which is exposed when only the surface of STI (2) in region B is drawn back, so that a facet (F) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer (11) in region B. Accordingly, short circuit between semiconductor layers on source/drain electrodes of transistors in region A is prevented, and uniformity of the junction depth of the layer (11) of the source/drain electrodes including an ESD region in a transistor of region B is obtained, thereby restricting the short channel effect.

Abstract: After forming a plurality of gate structures over a substrate having a plurality of active regions separated from each other by at least one shallow trench isolation (STI) regions, inter-gate dielectric contact structures extending through an interlevel dielectric (ILD) layer that surrounds the gate structures are formed. Each inter-gate dielectric contact structure encloses a corresponding gate structure and is in contact with a dielectric gate cap and a dielectric gate spacer of the corresponding gate structure and a portion of the at least one STI region abutting the dielectric gate spacer of the corresponding gate structure. The inter-gate dielectric contact structure is electrically insulated from a gate conductor in the corresponding gate structure by the dielectric gate cap and the dielectric gate spacer and serves as a control gate in a memory cell of a flash memory array.

Abstract: A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween.

Abstract: Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.

Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.

Abstract: A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.

Abstract: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.

Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, at least one end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. The NAND string also includes a memory film located between the semiconductor channel and the plurality of control gate electrodes and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. The NAND string also includes a plurality of discrete cover silicon oxide segments located between the memory film and each respective clam-shaped portion of the blocking dielectric containing a respective control gate electrode. Each of the plurality of cover silicon oxide segments has curved upper and lower sides and substantially straight vertical sidewalls.

Abstract: A composite spacer structure is formed on vertical sidewalls of a gate structure that is formed straddling a semiconductor fin. In one embodiment, the composite spacer structure includes an inner low-k dielectric material portion and an outer nitride material portion.

Abstract: Device structures and design structures for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: A liquid crystal display device includes a gate electrode; a gate insulating layer on the gate electrode; an active layer on the gate insulating layer corresponding to the gate electrode; source and drain electrodes on the active layer; a first passivation layer on the source and drain electrodes; a common electrode on the first passivation layer; a second passivation layer on the common electrode, covering the common electrode, and having a separate region from the first passivation layer at a thickness of the common electrode; a pixel electrode on the second passivation layer and connected to the drain electrode through a drain contact hole; and a common line at a same layer as the pixel electrode and connected to the common electrode.

Abstract: A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an interlayer insulating film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks.

Abstract: A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.

Abstract: A voltage regulator circuit includes a transistor and a capacitor. The transistor includes a gate, a source, and a drain, a first signal is inputted to one of the source and the drain, a second signal which is a clock signal is inputted to the gate, an oxide semiconductor layer is used for a channel formation layer, and an off-state current is less than or equal to 10 aA/?m. The capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a high power source voltage and a low power source voltage are alternately applied to the second electrode.

Abstract: A display apparatus includes a first insulating substrate including a front surface that provides an image and a rear surface opposite to the front surface, a low reflection layer provided on the rear surface, a gate wiring part provided on the low reflection layer, a data wiring part provided on the rear surface, the data wiring part that is insulated from the gate wiring part; and a pixel which is connected to the data wiring part and displays the image, where the low reflection layer includes a polymer resin having a black color.

Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. In the manufacturing method, the needed patterns can be formed by just three photolithography processes, wherein the semiconductor layer and the etch stop layer are formed by just one photolithography process. The method reduces one photolithography process compared to the method of the state of the art, which forms the pattern of the semiconductor layer and the etch stop layer by two photolithography processes respectively, thereby greatly reducing the manufacturing cost and improving the production efficiency.

Abstract: A photoelectric conversion apparatus in which each of a plurality of pixels includes a photoelectric conversion element configured to generate an electric charge by a photoelectric conversion, an impurity diffusion region, and a gate electrode configured to transfer the electric charge from the photoelectric conversion element to the impurity diffusion region. The photoelectric conversion apparatus includes a gate control line composed of a metal wiring extending in a first direction and being connected electrically to the gate electrode. Some or all of the impurity diffusion regions of the plurality of pixels are mutually connected. A read out circuit region is arranged in an outside in a second direction from a pixel arranged at a most outside among all of the plurality of pixels. A metal wiring layer arranged in a pixel array region is composed of only a single wiring layer including a plurality of wirings in the same height.

Abstract: An image sensor arranged inside and on top of a semiconductor substrate, having a plurality of pixels, each including: a photosensitive area, a read area, and a storage area extending between the photosensitive area and the read area; at least one first insulated vertical electrode extending in the substrate between the photosensitive area and the storage area; and at least one second insulated vertical electrode extending in the substrate between the storage area and the read area.

Abstract: A solid-state image sensing element including a transistor with stable electrical characteristics (e.g., significantly low off-state current) is provided. Two different element layers (an element layer including an oxide semiconductor layer and an element layer including a photodiode) are stacked over a semiconductor substrate provided with a driver circuit such as an amplifier circuit, so that the area occupied by a photodiode is secured. A transistor including an oxide semiconductor layer in a channel formation region is used as a transistor electrically connected to the photodiode, which leads to lower power consumption of a semiconductor device.

Abstract: An integrated-circuit image sensor that includes an array of pixel regions composed of binary pixel circuits. Each binary pixel circuit includes a binary amplifier having an input and an output. The binary amplifier generates a binary signal at the output in response to whether an input voltage at the input exceeds a switching threshold voltage level of the binary amplifier. A light-detecting element of the binary pixel circuit is coupled to the input of the binary amplifier. Initialization circuitry of the binary pixel circuit is coupled to the input of the binary amplifier. The initialization circuitry sets the input voltage to a level that is offset relative to the switching threshold voltage level of the binary amplifier by an offset voltage amount, the offset voltage amount representing a threshold amount of light incident on the light detecting element.