Abstract: In a solid-state image pickup device including a pixel that includes a photoelectric conversion portion, a carrier holding portion, and a plurality of transistors, the solid-state image pickup device further includes a first insulating film disposed over the photoelectric conversion portion, the carrier holding portion, and the plurality of transistors, a conductor disposed in an opening of the first insulating film and positioned to be connected to a source or a drain of one or more of the plurality of transistors, and a light shielding film disposed in an opening or a recess of the first insulating film and positioned above the carrier holding portion.

Abstract: Embodiments are disclosed of an apparatus comprising a color filter arrangement including a set of color filters. The set of color filters includes a pair of first color filters, each having first and second hard mask layers formed thereon, a second color filter having the first hard mask layer formed thereon, and a third color filter having no hard mask layer formed thereon. Other embodiments are disclosed and claimed.

Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.

Abstract: A color filter 5 is formed above a semiconductor substrate SB, in an area above a predetermined light receiving portion among a plurality of light receiving portions 1. A sacrificial layer 8 is formed on upper and side of the first color filter 5. Color filters 6 and 7 are formed above the semiconductor substrate SB, in areas above other light receiving portions adjacent to the predetermined light receiving portion, to expose at least part of the upper surface area of the first color filter 5 on the sacrificial layer 8. The sacrificial layer 8 is etched to remove the upper and side areas of the color filter 5 on the sacrificial layer 8 to form hollow portions 9 between the color filter 5 and the color filter 6 and between the color filter 5 and the color filter 7.

Abstract: A light-emitting device includes a substrate, and a plurality of light-emitting elements that are mounted on the substrate and each include an LED chip and a phosphor layer on a surface thereof. A maximum deviation in a value of a chromaticity coordinate x of light emitted from the plurality of light-emitting elements is not less than 0.0125.

Abstract: The invention relates to a device comprising a substrate supporting a matrix of diodes organized in rows and columns, and a peripheral substrate contact is arranged on at least one side of the matrix, characterized in that the substrate comprises one or several buried conducting lines having no direct electrical connection with the peripheral substrate contact and being positioned between at least two adjacent columns of diodes and between at least two adjacent rows of diodes.

Abstract: A memory cell with a substrate; a first transistor comprising a first gate width and a terminal; resistive memory elements above the transistor, each element comprising an element width, a first and second end; parallel conductive lines above the first memory elements and coupled to the first elements at their first ends; a second plurality of resistive memory elements disposed above the conductive lines, each element comprising the width, the first end, and the second end and coupled to the conductive lines at their first ends; a second transistor disposed above the second plurality of resistive memory elements and comprising a gate width and a terminal, the first memory elements is jointly coupled to the terminal of the first transistor at their second ends; the second memory elements is jointly coupled to the terminal of the second transistor at their second ends; and the gate width is larger than the element width.

Abstract: A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type.

Abstract: A light emitting device having a high definition, a high aperture ratio and a high reliability is provided. The present invention realizes a high definition and a high aperture ratio for a flat panel display of full colors using luminescent colors of red, green and blue without being dependent upon the film formation method and deposition precision of an organic compound layer by forming the laminated sections 21, 22 by means of intentionally and partially overlapping different organic compound layers of adjacent light emitting elements. Moreover, the protective film 32a containing hydrogen is formed and the drawback in the organic compound layer is terminated with hydrogen, thereby realizing the enhancement of the brightness and the reliability.

Abstract: An organic light emitting display device and a method of manufacturing the same are provided. The organic light emitting display device includes a substrate including red, green, and blue sub-pixel regions, reflective electrodes on the substrate, a reflective protective film on the substrate and surrounding sides and front surfaces of each reflective electrode, the reflective electrodes being on the reflective protective film, first electrodes on the substrate, the reflective protective film being on the first electrodes, the first electrodes including different respective thicknesses in the respective red, green, and blue sub-pixel regions, a second electrode facing the first electrodes, and a white organic common layer between the first and second electrodes.

Abstract: A flexible organic light-emitting display device and a method of manufacturing the flexible organic light-emitting display device are provided. The flexible organic light-emitting display device comprises a lower flexible substrate assembly and an upper flexible substrate assembly that are bonded by a bonding layer. The lower flexible substrate assembly includes a first flexible substrate, a thin film transistor formed on the first flexible substrate, a white organic light-emitting element formed on the thin film transistor, and an encapsulation layer formed on the white organic light-emitting element. The upper flexible substrate assembly comprises a second flexible substrate, an interlayer and a touch sensing unit formed on the interlayer layer. The interlayer may be at least one of a color filter layer, a transparent resin layer, an insulating film layer and a second flexible substrate.

Abstract: An in-cell active matrix OLED touch panel structure of narrow border includes first and second substrates, an OLED layer configured between the first and second substrates, first and second sensing electrode layers, and a thin film transistor layer. The first sensing electrode layer includes M first conductor blocks and N connection lines arranged in a first direction. The second sensing electrode layer includes N second conductor blocks arranged in a second direction. Each second conductor block makes use of a corresponding i-th connection line to be extended to one edge of the panel structure. The thin film transistor layer includes K gate lines and L source lines. The M first conductor blocks, the N connection lines, and the N second conductor blocks are disposed at positions corresponding to those of the K gate lines and L source lines of the thin film transistor layer.

Abstract: Provided is a display panel having a plurality of pixels arranged in a matrix of rows and columns. Each of the pixels is composed of a plurality of first sub-pixels emitting light of different colors. Each of the first sub-pixels is composed of a plurality of second sub-pixels emitting light of the same color. Each of the second sub-pixels includes: a first electrode; a second electrode above the first electrode; and a light-emitting layer between the first electrode and the second electrode.

Abstract: In an organic light-emitting display device and a method of manufacturing the same, the organic light-emitting display device includes: a first insulating layer, a transparent conductive layer, and a second insulating layer which are sequentially formed on a substrate; a thin film transistor including an active layer formed under the first insulating layer, a gate electrode including a part of the transparent conductive layer as a lower electrode layer, and source and drain electrodes connected to both sides of the active layer; an organic light-emitting device including a sequentially stacked structure comprising a part of the transparent conductive layer as a pixel electrode, an intermediate layer which includes an emission layer, and an opposite electrode; and a capacitor including a first electrode and a second electrode, which includes a part of the transparent conductive layer as a lower electrode layer; wherein the transparent conductive layer and the second insulating layer include a hole.

Abstract: According to one embodiment, a flat-panel display device includes a first substrate including an output pad to which a signal necessary for displaying an image on an active area is supplied from a signal supply source, a dummy pad juxtaposed with the output pad, a signal line connected to the output pad, a switching element connected to the signal line, a pixel electrode connected to the switching element in the active area, a first dummy line connected to the dummy pad, spaced apart from the signal line and including a first projection protruding in a direction crossing a direction of extension of the first dummy line, and a second dummy line spaced apart from the dummy pad and the signal line and including a second projection opposed to the first projection.

Abstract: There is provided a light emitting apparatus provided with a pixel circuit which is provided with a plurality of transistors including a first transistor and a light emitting element in which a current is supplied by the first transistor, in which, in at least one of the plurality of transistors, a wiring is connected to a gate electrode at a position overlapping a channel region in plan view.

Abstract: Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. A second interlayer insulation layer covers the first interlayer insulation layers and the conductive patterns. A resistor is formed in the second interlayer insulation layer in the second region of the substrate.

Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.

Abstract: A structure including an oxide semiconductor layer which is provided over an insulating surface and includes a channel formation region and a pair of low-resistance regions between which the channel formation region is positioned, a gate insulating film covering a top surface and a side surface of the oxide semiconductor layer, a gate electrode covering a top surface and a side surface of the channel formation region with the gate insulating film positioned therebetween, and electrodes electrically connected to the low-resistance regions is employed. The electrodes are electrically connected to at least side surfaces of the low-resistance regions, so that contact resistance with the source electrode and the drain electrode is reduced.

Abstract: A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers.

Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.

Abstract: A termination region structure of a semiconductor device is provided, which includes: a semiconductor layer; a plurality of trenches, formed on a surface of the semiconductor layer; a connecting trench, formed on the surface of the semiconductor layer, for connecting two adjacent trenches in the plurality of trenches; a first insulating layer, formed on surfaces of the plurality of trenches, the connecting trench, and the semiconductor layer; a conductive material, formed in the plurality of trenches and the connecting trench; a second insulating layer, covering part of a surface of the first insulating layer and part of a surface of the conductive material; and a metal layer, covering part of a surface of the second insulating layer.

Abstract: A graphene base transistor with reduced collector area comprising an electron injection region, an electron collection region, and a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.

Abstract: A Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an N-type substrate and an epitaxial structure on a front-side of the N-type substrate. The epitaxial substrate includes a P-type layer adjacent to the N-type substrate and one or more additional SiC layers on the P-type layer opposite the N-type substrate. The semiconductor device also includes one or more openings through the N-type substrate that extend from a back-side of the N-type substrate to the P-type layer and a back-side contact on the back-side of the N-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the N-type substrate.

Abstract: A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer.

Abstract: Tunneling field effect transistors are provided. The tunneling field effect transistor includes a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a first region adjacent to the source region and a second region adjacent to the drain region. A first energy band gap of the first region is lower than a second energy band gap of the second region, and the first region has a direct energy band gap.

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface having an element formation region, a guard ring, a guard ring electrode, a channel stopper region, a channel stopper electrode, and a field plate disposed over and insulated from the semiconductor substrate. The field plate includes a first portion located between the main surface of the semiconductor substrate and the guard ring electrode, and a second portion located between the main surface of the semiconductor substrate and the channel stopper electrode. The first portion has a portion overlapping with the guard ring electrode when viewed in a plan view. The second portion has a portion overlapping with the channel stopper electrode when viewed in the plan view. In this way, a semiconductor device allowing for stabilized breakdown voltage can be obtained.

Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.

Abstract: A semiconductor device includes a substrate and a plurality of transistors arranged on the substrate in an array. The transistor includes a first electrode, a plurality of second electrodes, and a gate electrode. The second electrodes are arranged around the first electrode. The gate electrode is located between the first electrode and the second electrodes. The first electrode is a polygon. The gate electrode is around the first electrode, and an edge of the gate electrode facing the first electrode has a shape corresponding to that of the first electrode. The first electrode and the edge of the gate electrode facing the first electrode are regular polygons, and have the same center.

Abstract: A semiconductor device includes a junction region on both sides of a trench in a semiconductor substrate, a first gate electrode with a first workfunction buried in the trench, and a second gate electrode formed of a polycide layer having a second workfunction overlapping with the junction region at an upper part of the first gate electrode.

Abstract: When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.

Abstract: A method for manufacturing a nitride-based semiconductor device includes: preparing a substrate; forming a buffer layer on the substrate, the buffer layer preventing dislocation with the substrate; forming a spacer on the buffer layer; forming a barrier layer on the spacer, the barrier layer forming a hetero-structure with the spacer; forming a protecting layer on the barrier layer; and forming an HfO2 layer the protecting layer through RF sputtering.

Abstract: Methods and apparatuses are described for integration of integrated circuit die and silicon-based trench capacitors using silicon-level connections to reduce connection lengths, parasitics and necessary capacitance magnitudes and volumes. A trench capacitor can be fabricated on silicon and mounted on or embedded in a chip or one or more sides of a through silicon interposer (TSI) for silicon-level connections to chip circuitry. Aspect ratio dependent, as opposed to trench diameter or trench depth dependent, trench capacitors formed by a dense array of high aspect ratio trenches with thin, high permittivity dielectric increase capacitance per unit area and volume, resulting in thin, high capacitance trench capacitors having thickness equal to or less than chip thickness.

Abstract: High electron mobility transistors (HEMTs) having improved I-V characteristics and reliability are provided. According to one embodiment, a selective implantation is performed to form a damage region in a gate-to-drain region of, for example, an I?A?N/GaN HEMT. The selective implantation can be performed by irradiating some or all of a gate-to-drain region of an InAlN/GaN HEMT on a substrate with protons or other ions such as Ge ions, He ions, N ions, or O ions. The damage region can extend in a region below a 2DEG interface of the HEMT.

Abstract: Methods of fabricating quantum well field effect transistors are provided. The methods may include forming a first barrier layer including a first delta doped layer on a quantum well layer and forming a second barrier layer including a second delta doped layer selectively on a portion of the first barrier layer in a first region of the substrate. The methods may also include patterning the first and second barrier layers and the quantum well layer to form a first quantum well channel structure in the first region and patterning the first barrier layer and the quantum well layer to form a second quantum well channel structure in a second region. The methods may further include forming a gate insulating layer on the first and second quantum well channel structures of the substrate and forming a gate electrode layer on the gate insulating layer.

Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.

Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a bottom anti-reflective coating (BARC), baking to induce cross-linking in the BARC, CMP to remove a first portion of the BARC and form a planar surface, then plasma etching to effectuate a planar recessing of the BARC. The plasma etching can have a low selectivity between the BARC and the material being recessed, whereby the BARC and the material are recessed simultaneously. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The method can be particularly effective when an abrasive used during CMP forms ester linkages with the BARC.

Abstract: A semiconductor device having asymmetric spacers and steps for forming the same are disclosed. The spacers have difference capacitances, with the spacer having a higher capacitance formed over a source region of the device and the spacer having a lower capacitance formed over a drain region of the device. Embodiments of the disclosed invention include spacers made from different materials, having different or substantially equal thicknesses.

Abstract: In the present method of fabricating a semiconductor device, initially, a semiconductor substrate is provided. An oxide layer is provided on and in contact with the substrate, and a polysilicon layer is provided on and in contact with the oxide layer. A layer of photoresist is provided on the polysilicon layer, and the photoresist is patterned to provide a photoresist body, which is used as a mask to etch away polysilicon and oxide, forming a polysilicon element thereunder. The photoresist body is then removed. A nickel layer is provided on the resulting structure, and a reaction step is undertaken to provide that nickel diffuses into the exposed top and side portions of the polysilicon body, forming nickel silicide. After the reaction step, the remaining nickel is removed, and a chemical-mechanical polishing step is undertaken to remove nickel silicide so that a pair of nickel silicide bodies remain, separated by polysilicon.

Abstract: A high-voltage LDMOS device with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming a continuous gate structure over a deep well region and a body of a substrate. The method further includes forming oppositely doped, alternating segments in the continuous gate structure. The method further includes forming a contact in electrical connection with a tip of the continuous gate structure and a drain region formed in the substrate. The method further includes forming metal regions in direct electrical contact with segments of at least one species of the oppositely doped, alternating segments.

Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into a drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. The Schottky barrier controlling layer controls Schottky barrier height of a Schottky diode formed by the contact electrode and the drain.

Abstract: A method of fabricating an array substrate includes: forming a line or an electrode on a substrate on which a pixel region is defined, forming a protection layer on the line or the electrode, the protection layer formed of silicon nitride (SiNX), forming photoresist patterns on the protection layer, and loading the substrate having the photoresist pattern into a chamber of a dry etching apparatus, and performing a first dry etching process on the protection layer exposed between the photoresist patterns using a first gas mixture containing nitrogen trifluoride (NF3) gas to form a contact hole exposing the line or the electrode.

Abstract: A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.

Abstract: According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

Abstract: A method of fabricating a thin-film transistor, the method including: film-forming an active layer, that contains as a main component thereof an oxide semiconductor structured by O and at least two elements among In, Ga and Zn, in a film formation chamber into which at least oxygen is introduced, and b) heat treating the active layer at less than 300° C. in a dry atmosphere, wherein the film-forming a) and the heat treating are carried out such that, given that an oxygen partial pressure with respect to an entire pressure of an atmosphere within the film formation chamber in the film-forming is PO2depo (%), and an oxygen partial pressure with respect to an entire pressure of an atmosphere during the heat treating is PO2anneal (%), the oxygen partial pressure PO2anneal (%) at the time of the heat treating b) satisfies a relationship: ?20/3PO2depo+40/3?PO2anneal??800/43PO2depo+5900/43.

Abstract: A thin film transistor substrate includes an active pattern which is disposed on a base substrate and includes a channel, a source electrode and a drain electrode, the channel which includes an oxide semiconductor, the source electrode and the drain electrode connected the channel, a gate electrode overlapped with the channel, a passivation layer which covers the source electrode, the drain electrode and the gate electrode and a fluorine deposition layer disposed between the active pattern and the passivation layer.

Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

Abstract: A method for manufacturing thin film transistor array substrate is disclosed. The method includes sequentially depositing a semiconductor layer and an ohmic contact layer on the base substrate formed with a gate insulator and patterning the semiconductor layer and the ohmic contact layer, wherein the material of the semiconductor layer is zinc oxide, and the material of the ohmic contact layer is GaxZn1-xO, where 0<x?1.

Abstract: A bipolar transistor includes a semiconductor structure including an emitter area, a base area and a collector area. The emitter area is electrically connected to an emitter contact of the bipolar transistor. Further, the emitter area has a first conductivity type. The base area is electrically connected to a base contact of the bipolar transistor. Further, the base area has at least mainly a second conductivity type. The collector area is electrically connected to a collector contact of the bipolar transistor and has at least mainly the first conductivity type. Further, the collector area includes a plurality of enclosed sub areas having the second conductivity type or the base area includes a plurality of enclosed sub areas having the first conductivity type.

Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.