Abstract: A semiconductor device is disclosed. The semiconductor device is capable of obtaining a high reverse recovery resistant amount by allowing sheet resistance of a peripheral portion in a p type diffusion region that is in contact with a metal electrode through an insulating film on a surface to be as high as possible and reducing an increase in cost if possible. The semiconductor device includes: a p type diffusion region that is disposed in a surface layer of the one main surface of an n type semiconductor substrate; and a voltage-resistant region that surrounds the p type diffusion region.

Abstract: A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n+ emitter region and an n? drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the n+ emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.

Abstract: A III-nitride semiconductor device which includes a charged floating gate electrode.

Abstract: A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

Abstract: A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.

Abstract: A circuit can include at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and a bias circuit configured to provide bias currents to the drains of the DDC transistors; wherein each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the first conductivity type formed below the channel region.

Abstract: Provided are methods of depositing hafnium or zirconium containing metal alloy films. Certain methods comprise sequentially exposing a substrate surface to alternating flows of an organometallic precursor and a reductant comprising M(BH4)4 to produce a metal alloy film on the substrate surface, wherein M is selected from hafnium and zirconium, and the organometallic precursor contains a metal N. Gate stacks are described comprising a copper barrier layer comprising boron, a first metal M selected from Hf and Zr, and a second metal N selected from tantalum, tungsten, copper, ruthenium, rhodium, cobalt and nickel; and a copper layer overlying the copper barrier seed layer.

Abstract: According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×1016 (atoms/cm3).

Abstract: The invention discloses a high-voltage LDMOS integrated device, which is interdigitally structured in a plan view and which including: a first area corresponding to a source fingertip area, wherein a first sectional structure of the first area particularly includes: a first drain; and a first longitudinal voltage-withstanding buffer layer located below the first drain and consisted of a first deep N-well and a first low-voltage N-well, wherein the first low-voltage N-well is located in the first deep-N well, and the first deep-N well is located in a P-type substrate; and a second area non-overlapping with the first area, wherein a second sectional structure of the second area particularly includes: a second drain; and a second longitudinal voltage-withstanding buffer layer located below the second drain and consisted of a second deep N-well and a second low-voltage N-well.

Abstract: A semiconductor power device and a method of fabricating the same are provided. The semiconductor power device involving: a first conductivity type semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a second conductivity type well formed in the semiconductor substrate and the epitaxial layer; a drain region formed in the well; an oxide layer that insulates a gate region from the drain region; a first conductivity type buried layer formed in the well; a second conductivity type drift region surrounding the buried layer; and a second conductivity type TOP region formed between the buried layer and the oxide layer.

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

Abstract: A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

Abstract: A memcapacitor device includes a pair of opposing conductive electrodes. A semiconductive material including mobile dopants within a dielectric and a mobile dopant barrier dielectric material are received between the pair of opposing conductive electrodes. The semiconductive material and the barrier dielectric material are of different composition relative one another which is at least characterized by at least one different atomic element. One of the semiconductive material and the barrier dielectric material is closer to one of the pair of electrodes than is the other of the semiconductive material and the barrier dielectric material. The other of the semiconductive material and the barrier dielectric material is closer to the other of the pair of electrodes than is the one of the semiconductive material and the barrier dielectric material. Other implementations are disclosed, including field effect transistors, memory arrays, and methods.

Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.

Abstract: A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

Abstract: Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

Abstract: Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions.

Abstract: A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide.

Abstract: One method disclosed includes, among other things, removing a sacrificial gate structure to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to define a fin structure in a layer of semiconductor material using a patterned hard mask exposed within the replacement gate cavity as an etch mask and forming a replacement gate structure in the replacement gate cavity around at least a portion of the fin structure.

Abstract: One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure.

Abstract: Semiconductor devices and methods for forming devices with ultraviolet curing. One method includes, for instance: obtaining a wafer; forming at least one mandrel; forming spacers adjacent to the at least one mandrel; performing an ultraviolet treatment to at least one set of spacers; and etching to form hard mask regions below at least the spacers. An intermediate semiconductor device includes, for instance: a substrate; a stop layer over the substrate; a first barrier layer over the stop layer; at least one first mandrel and at least one second mandrel on the first barrier layer; at least one first set of spacers positioned adjacent to the first mandrel; at least one second set of spacers positioned adjacent to the second mandrel; and a second barrier layer over the at least one first mandrel and the at least one first set of spacers.

Abstract: The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Abstract: A FinFET having a backgate and a barrier layer beneath the fin channel of the FinFET, where the barrier layer has a bandgap greater than that of the backgate. The barrier layer serves as an etch stop layer under the fin channel, resulting in reduced fin channel height variation. The backgate provides improved current control. There is less punchthrough due to the higher bandgap barrier layer. The FinFET may also include deeply embedded stressors adjacent to the source/drain diffusions through the high bandgap barrier layer.

Abstract: A thin film transistor, a pixel, and an organic light emitting diode (OLED) display including the same are disclosed. The thin film transistor includes a connection to the channel region separate from connections to the source and drain.

Abstract: A thin film transistor substrate with an adhesive strength between a semiconductor layer and a source electrode, and between a semiconductor layer and a drain electrode; and an LCD device using the thin film transistor substrate. The thin film transistor substrate includes a substrate, a gate electrode on the substrate, a gate insulating film on the gate electrode, an active layer on the gate insulating film, an ohmic contact layer on the active layer, a barrier layer on the ohmic contact layer. The barrier layer is formed of a material layer containing Ge. A source electrode and a drain electrode are on the barrier layer. The source and drain electrodes are provided at a predetermined interval from each other.

Abstract: A multiple vertical transistor device includes a polymeric material post on a substrate. An inorganic material cap extends beyond first and second edge of the post to define first and second reentrant profiles. First and second portions of a conformal conductive gate layer define first and second gates in the first and second reentrant profiles, respectively. A conformal electrically insulating layer maintains the first and second reentrant profiles and is in contact with the first and second gates. First and second portions of a semiconductor layer, maintaining the first and second reentrant profiles, are in contact with the conformal electrically insulating layer that is in contact with the first and second gates, respectively. The first and second portions of the semiconductor layer are electrically independent from each other. First and second electrodes are associated with the first gate. Third and fourth electrodes are associated with the second gate.

Abstract: A method of manufacturing a substrate having a thin film thereabove includes: forming a thin film above the substrate; and crystallizing at least a predetermined area of the silicon thin film into a crystallized area through relative scan of the silicon thin film which is performed while the thin film is being irradiated with a continuous wave light beam, wherein in the crystallizing, a projection of the light beam on the thin film has a major axis in a direction crossing a direction of the relative scan, and the formed crystallized area includes a strip-shaped first area extending in the direction crossing the direction of the relative scan and a second area adjacent to the strip-shaped first area, the strip-shaped first area including crystal grains having an average grain size larger than that of crystal grains in the second area.

Abstract: A thin film transistor is equipped with a silicon substrate, a channel layer, a source electrode and a drain electrode. The channel layer, the source electrode and the drain electrode are arranged on the main surface of the silicon substrate. The channel layer is composed of multiple carbon nanowall thin films, wherein the multiple carbon nanowall thin films are arranged in parallel to each other between the source electrode and the drain electrode, one end of each of the multiple carbon nanowall thin films is in contact with the source electrode, and the other end of each of the multiple carbon nanowall thin films is in contact with the drain electrode. An insulating film and a gate electrode are arranged on the rear surface side of the silicon substrate.

Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

Abstract: A transistor including an oxide semiconductor film, in which the threshold voltage is prevented from being a negative value, is provided. A high quality semiconductor device having the transistor including an oxide semiconductor film is provided. A transistor includes an oxide semiconductor film having first to third regions. The top surface of the oxide semiconductor film in the first region is in contact with a source electrode or a drain electrode. The top surface of the oxide semiconductor film in the second region is in contact with a protective insulating film. The thickness of the second region is substantially uniform and smaller than the maximum thickness of the first region. The top surface and a side surface of the oxide semiconductor film in the third region are in contact with the protective insulating film.

Abstract: A field effect transistor including: a gate insulating film; an oxide semiconductor layer that serves as an active layer and whose main structural elements are Sn, Zn and O, or Sn, Ga, Zn and O; and an oxide intermediate layer that is disposed between the gate insulating film and the oxide semiconductor layer, and whose resistivity is higher than that of the oxide semiconductor layer.

Abstract: An active device provided by the invention is disposed on a substrate and includes a gate, a gate insulating layer, an oxide semiconductor channel layer, a plurality of nano conductive wires, a source and a drain. The gate insulating layer is disposed between the gate and the oxide semiconductor channel layer. The nano conductive wires are distributed in the oxide semiconductor channel layer, in which the nano conductive wires do not contact the gate insulating layer and the nano conductive wires are arranged along a direction and not intersected with each other. The source and the drain are disposed on two sides opposite to each other of the oxide semiconductor channel layer, in which a portion of the oxide semiconductor channel layer is exposed between the source and the drain.

Abstract: A p-type transparent oxide semiconductor includes tin oxide compounds represented by below chemical formula 1: Sn1-xMxO2??[Chemical Formula 1] wherein, in the chemical formula 1, the M is tri-valent metal and the X is a real number of 0.01˜0.05. The p-type transparent oxide semiconductor is applicable to active semiconductor devices such as TFT-LCD and transparent solar cell, due to excellent electrical and optical properties and shows superior properties in aspects of visible light transmittance (T), carrier mobility (?) and rectification ratio as well as transparency.

Abstract: A field effect transistor (FET) is provided. The active layer of this FET is composed of at least two different amorphous metal oxide semiconductor layer stacked together. Therefore, the two opposite surfaces of the active layer can have different band gap values.

Abstract: There are provided an oxide TFT, a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the display device. The oxide thin film transistor includes: a gate electrode formed on a substrate; a gate insulating layer formed on the entire surface of the substrate including the gate electrode; an active layer pattern formed on the gate insulating layer above the gate electrode and completely overlapping the gate electrode; an etch stop layer pattern formed on the active layer pattern and the gate insulating layer; and a source electrode and a drain electrode formed on the gate insulating layer including the etch stop layer pattern and the active layer pattern and spaced apart from one another, and overlapping both sides of the etch stop layer pattern and the underlying active layer pattern.

Abstract: The invention provides a thin film transistor that can reduce an off-current flowing in end-parts in a channel width direction of a channel layer and a manufacturing method therefor.

Abstract: The method for fabricating a semiconductor device is provided. A doped semiconductor layer is formed over the substrate. The doped semiconductor layer is patterned to form a plurality of doped semiconductor patterns. An implantation process is performed to implant a dopant into the doped semiconductor patterns. A process temperature of the implantation process is no more than about ?50° C. The dopants of the implantation process and the doped semiconductor patterns have the same conductivity type.

Abstract: A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. The first poly and the second poly have substantially a same planarized height above the substrate. The first poly extends from a device region to a strap region, and extends substantially parallel to a first length of the second poly. A second length of the second poly extends away from the first poly in the strap region and includes a salicide. A first diffusion region crosses the first poly and the second poly in the device region. A masked width of the first length of the second poly is defined by an etched spacer. A low resistance contact is coupled to the second length of the second poly in the strap region.

Abstract: Junction field-effect transistors and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.

Abstract: A Schottky barrier diode and a method of manufacturing the Schottky barrier diode are provided. The diode includes an n? type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and having an upper surface, a lower surface, and an inclined surface that connects the upper surface and the lower surface. A p region is disposed on the inclined surface of the n? type epitaxial layer and a Schottky electrode is disposed on the upper surface of the n? type epitaxial layer and the p region. In addition, an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate.

Abstract: A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.

Abstract: In accordance with certain embodiments, semiconductor dies are at least partially coated with a polymer and a conductive adhesive prior being bonded to a substrate having electrical traces thereon.

Abstract: A connection part for connecting an interconnector is separated from a region having a photoelectric conversion layer formed thereon to improve a strength of the connection pad, thereby provide a solar cell suppressing cracks, breaks, and the like. A solar cell includes a photoelectric conversion layer, an electrode pad formed on the photoelectric conversion layer, an interconnector connected to the electrode pad, a metal thin film formed under the photoelectric conversion layer, a relay terminal being spaced apart from the photoelectric conversion layer and the metal thin film and connected to the metal thin film by connection conductor, and a connection pad formed on the relay terminal.

Abstract: A method for controlling a group of photovoltaic energy generators, the method includes providing, to a junction that is coupled to a component of a first photovoltaic energy generator (PEG), power generated by at least a second PEG such as to increase the power that is generated from the group of photovoltaic energy generators (PEGs); wherein the group of PEGs comprises the first PEG and the second PEG.

Abstract: A solar cell and a method for manufacturing the same are discussed. The solar cell includes a semiconductor substrate, a first doped region of a first conductive type, a second doped region of a second conductive type opposite the first conductive type, a back passivation layer having contact holes exposing a portion of each of the first and second doped regions, a first electrode formed on the first doped region exposed through the contact holes, a second electrode formed on the second doped region exposed through the contact holes, an alignment mark formed at one surface of the semiconductor substrate, and a textured surface that is formed at a light receiving surface of the semiconductor substrate opposite the one surface of the semiconductor substrate in which the first and second doped regions are formed.

Abstract: A conductive silver via paste comprising particulate conductive silver, a vanadium-phosphorus-antimony-zinc-based-oxide, a tellurium-boron-phosphorus-based-oxide or a tellurium-molybdenum-cerium-based-oxide and an organic vehicle is particularly useful in providing the metallization of the holes in the silicon wafers of MWT solar cells. The result is a metallic electrically conductive via between the collector lines on the front side and the emitter electrode on the back-side of the solar cell. The paste can also be used to form the collector lines on the front-side of the solar cell and the emitter electrode on the back-side of the solar cell. Also disclosed are metal-wrap-through silicon solar cells comprising the fired conductive silver paste.

Abstract: The photoelectric conversion element includes a semiconductor substrate, a first amorphous film of a first conductivity type disposed on an entire surface of one surface of the semiconductor substrate, a first conductive oxide layer disposed on the first amorphous film, a second amorphous film of the first conductivity type disposed on a part of the other surface of the semiconductor substrate, a second conductive oxide layer disposed on the second amorphous film, a third amorphous film of a second conductivity type disposed on the other part of the other surface of the semiconductor substrate, and a third conductive oxide layer disposed on the third amorphous film. Electric conductivity of the first conductive oxide layer is lower than electric conductivities of the second and the third conductive oxide layer. Transmittance of the first conductive oxide layer is higher than transmittances of the second and the third conductive oxide layer.

Abstract: Disclosed herein is a solid-state image pickup element, including: a photoelectric conversion region; a transistor; an isolation region of a first conductivity type configured to isolate the photoelectric conversion region and the transistor from each other; a well region of the first conductivity type having the photoelectric conversion region, the transistor, and the isolation region of the first conductivity type formed therein; a contact portion configured to supply an electric potential used to fix the well region to a given electric potential; and an impurity region of the first conductivity type formed so as to extend in a depth direction from a surface of the isolation region of the first conductivity type in the isolation region of the first conductivity type between the contact portion and the photoelectric conversion region, and having a sufficiently higher impurity concentration than that of the isolation region of the first conductivity type.

Abstract: Systems and methods for producing nanoscale textured low reflectivity surfaces may be utilized to fabricate solar cells. A substrate may be patterned with a resist prior to an etching process that produces a nanoscale texture on the surface of the substrate. Additionally, the substrate may be subjected to a dopant diffusion process. Prior to dopant diffusion, the substrate may be optionally subjected to liquid phase deposition to deposit a material that allows for patterned doping. The order of the nanoscale texture etching and dopant diffusion may be modified as desired to produce post-nano emitters or pre-nano emitters.