Abstract: An organic light-emitting display device, which may be configured to prevent moisture or oxygen from penetrating the organic light-emitting display device from the outside is disclosed. An organic light-emitting display device, which is easily applied to a large display device and/or may be easily mass produced is further disclosed. Additionally disclosed is a method of manufacturing an organic light-emitting display device. An organic light-emitting display device may include, for example, a thin-film transistor (TFT) including a gate electrode, an active layer insulated from the gate electrode, source and drain electrodes insulated from the gate electrode and contacting the active layer and an insulating layer disposed between the source and drain electrodes and the active layer; and an organic light-emitting diode electrically connected to the TFT.

Abstract: A semiconductor device includes a semiconductor layer over a substrate. The semiconductor layer changes direction at least twice and has at least two different widths in the same plane. The length of a current path through the semiconductor layer is greater than a shortest path through the semiconductor layer in the same plane.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a thin film transistor comprising an active layer, a gate electrode, a source electrode, and a drain electrode. A first insulating layer is formed at least between the active layer and the gate electrode and a second insulating layer formed at least between the gate, source, and drain electrodes. The OLED display also includes a third insulating layer covering the source and drain electrodes and a pixel electrode including a first portion formed in first and second openings respectively defined in the second and third insulating layers and a second portion formed outside of the second opening. A pixel defining layer is formed over the second portion of the pixel electrode and the third insulating layer and has a third opening. The third opening has an area greater than that of the second opening.

Abstract: A display unit includes a plurality of light emitting devices, each of the light emitting devices including a function layer including at least an organic layer is sandwiched between a first electrode and a second electrode, and which have a resonator structure for resonating light by using a space between the first electrode and the second electrode as a resonant section and extracting the light through the second electrode are arranged on a substrate, wherein in the respective light emitting devices, the organic layer is made of an identical layer, and a distance of the resonant section between the first electrode and the second electrode is set to a plurality of different values.

Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

Abstract: A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices.

Abstract: Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N2O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.

Abstract: The semiconductor device has an insulation layer formed over a semiconductor substrate, a conductor plug 46 buried in the insulation layer, a capacitor formed above the insulation layer and the conductor plug and including a lower electrode formed of the first conduction film and the second conduction film formed over the first conduction film and formed of Pt, Pt alloy, Pd or Pd alloy, a capacitor dielectric film formed of a ferroelectric or a high dielectric formed over the lower electrode and an upper electrode formed over the capacitor dielectric film, the capacitor dielectric film contains a first element of Pb or Bi, and the concentration peak of the first element diffused in the lower electrode from the capacitor dielectric film positioning in the interface between the first conduction film and the second conduction film.

Abstract: A method of forming a dielectric material, comprising doping a zirconium oxide material, using a dopant precursor selected from the group consisting of Ti(NMe2)4; Ti(NMeEt)4; Ti(NEt2)4;TiCl4; tBuN?Nb(NEt2)3; tBuN?Nb(NMe2)3; t-BuN?Nb(NEtMe)3; t-AmN?Nb(NEt2)3; t-AmN?Nb(NEtMe)3; t-AmN?Nb(NMe2)3; t-AmN?Nb(OBu-t)3; Nb-13; Nb(NEt2)4; Nb(NEt2)5; Nb(N(CH3)2)5; Nb(OC2H5)5; Nb(thd)(OPr-i)4; SiH(OMe)3; SiCU; Si(NMe2)4; (Me3Si)2NH; GeRax(ORb)4.x wherein x is from 0 to 4, each Ra is independently selected from H or C1-C8 alkyl and each Rb is independently selected from C1-C8 alkyl; GeCl4; Ge(NRa2)4 wherein each Ra is independently selected from H and C1-C8 alkyl; and (Rb3Ge)2NH wherein each Rb is independently selected from C1-C8 alkyl; bis(N,N?-diisopropyl-1,3-propanediamide) titanium; and tetrakis(isopropylmethylamido) titanium; wherein Me is methyl, Et is ethyl, Pr-i is isopropyl, t-Bu is tertiary butyl, t-Am is tertiary amyl, and thd is 2,2,6,6-tetramethyl-3,5-heptanedionate.

Abstract: Disclosed are non-planar capacitors with finely tuned capacitances and methods of forming them. The capacitors each incorporate one or more semiconductor bodies and one or more gate stacks traversing the one or more semiconductor bodies. At least one first semiconductor body is etched so that it is shorter in length than the others, which are incorporated into other non-planar devices and/or into the same non-planar capacitor. Additionally, at least one gate stack can be formed so that it traverses a first portion and, particularly, an end portion of the shortened semiconductor body and further so that it extends laterally some distance beyond that first portion. In such capacitors, the length of the first portion of the shorted semiconductor body, which corresponds to a capacitor conductor and which is traversed by the gate stack, which corresponds to a capacitor dielectric and another capacitor conductor, is predetermined to achieve a desired capacitance.

Abstract: A semiconductor device production method includes forming a transition metal film, irradiating a surface of the transition metal film with a mono-silane gas to form a silicon-containing transition metal film, and oxidizing the silicon-containing transition metal film by an oxygen plasma treatment, thereby forming a transition metal silicate film.

Abstract: Integrated circuits with MIM capacitors and methods for producing them with metal and oxide hard masks are provided. Embodiments include disposing a dielectric layer over an ILD, the ILD including a contact therethrough in a first region; forming a capacitor trench in the dielectric layer in a second region; forming a MIM hard mask by: disposing a first metal hard mask in the first region and in the capacitor trench in the second region; disposing an oxide hard mask over the first metal hard mask; and disposing a second metal hard mask over the oxide hard mask; forming a metal line trench through the MIM hard mask in the first region, including over the contact, while masking the second region; and removing portions of the MIM hard mask in the capacitor trench, wherein a remaining portion of the first metal hard mask comprises a bottom plate of an MIM capacitor.

Abstract: A method for fabricating a capacitor of a semiconductor device includes forming a mold layer over a substrate, forming a plurality of preliminary openings by selectively etching the mold layer, forming a plurality of openings where each opening is formed to have a given linewidth by forming a sacrificial layer on sidewalls of the preliminary openings, and forming a plurality of storage nodes in the plurality of openings.

Abstract: An integrated circuit includes a guard ring structure including a guard ring with integrated well taps to reduce the silicon area required for the guard ring structure. In some embodiments, the guard ring structure includes an N-type guard ring surrounded by inner and outer P-type guard rings. The N-type guard ring is formed with interleaving deep N-wells and P-wells that are formed on an N-type buried layer and are electrically shorted together. The inner and outer P-type guard rings are formed in P-wells. The interleaving deep N-wells and P-wells of the N-type guard ring may be connected to ground or be left floating. By integrating P-well contacts in the N-type guard ring, P-well contacts, or P-taps, for the P-type guard ring can be eliminated.

Abstract: The thin film transistor includes a gate, a gate insulating layer, a semiconductor layer, and a source and a drain. The gate insulating layer covers the gate. The semiconductor layer is located on the gate insulating layer which is disposed above the gate. The source and the drain are disposed above the gate insulating layer and are electrically connected to the semiconductor layer, respectively. The source and the drain are respectively located in different layers. A first contact resistance is existed between the semiconductor layer and the source, a second contact resistance is existed between the semiconductor layer and the drain, and. the first contact resistance is less than the second contact resistance.

Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a cavity is formed. Thereafter an ion implant step through the cavity results in a localized increase in well-doping directly beneath the cavity. The implant is activated by a microsecond annealing which causes minimum dopant diffusion. Within the cavity a recess into the well area is formed in which an active region is formed using an un-doped or lightly doped epitaxial layer. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.

Abstract: A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type made of silicon carbide; and a second semiconductor layer of a second conductivity type made of silicon carbide, placed in junction with the first semiconductor layer, and containing an electrically inactive element.

Abstract: In a semiconductor device, a YAG substrate is formed as a single-crystal substrate of any of surface orientations (100), (110), and (111). In the fabrication of the semiconductor device, a TMAl gas is first fed onto the YAG substrate so as to form a nucleation layer made of aluminum, which is a group-III element. Then, an NH3 gas is fed onto the nucleation layer. This turns the surface of the nucleation layer into a group-V element and then forms a group-III-V compound layer of AlN. Then, a mixed gas of TMAl gas and NH3 gas is fed onto the group-III-V compound layer so as to form another group-III-V compound layer. Finally, a group-III nitride semiconductor layer is crystal-grown on the group-III compound layer.

Abstract: A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.

Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

Abstract: A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate.

Abstract: A method for forming a field effect power semiconductor device includes providing a semiconductor body comprising a main horizontal surface and a conductive region arranged next to the main horizontal surface, forming an insulating layer on the main horizontal surface, and etching a narrow trench through the insulating layer so that a portion of the conductive region is exposed, the narrow trench comprising, in a given vertical cross-section, a maximum horizontal extension. The method further includes forming a vertical poly-diode structure comprising a horizontally extending pn-junction. Forming the vertical poly-diode structure includes depositing a polycrystalline semiconductor layer comprising a minimum vertical thickness of at least half of the maximum horizontal extension and maskless back-etching of the polycrystalline semiconductor layer to form a polycrystalline region in the narrow trench.

Abstract: A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

Abstract: A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process.

Abstract: In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.

Abstract: A method comprising steps of removing a first dielectric material, including a hard mask layer and one or more spacer material layers, from a semiconductor device having a sacrificial gate whose sidewalls being covered by said spacer material layers, and a raised source and a raised drain region with both, together with said sacrificial gate, being covered by said hard mask layer, wherein the removing is selective to the sacrificial gate, raised source region and raised drain region and creates a void between each of the raised source region, raised drain region and sacrificial gate. The method includes depositing a conformal layer of a second dielectric material to the semiconductor device, wherein the second material conforms in a uniform layer to the raised source region, raised drain region and sacrificial gate, and fills the void between each of the raised source region, raised drain region and sacrificial gate.

Abstract: In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern. A first photoresist layer is formed on the first and second active regions of the substrate and the first anti-reflective layer. The first photoresist layer is partially etched to form a first photoresist pattern covering the first active region. Impurities are implanted into the second active region to form a first impurity region.

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.

Abstract: Disclosed is a method for fabricating an array substrate, comprising: forming a pattern layer comprising a gate and a gate connection on a substrate; sequentially forming an insulation layer film and an active layer film on the substrate, and forming a pattern of a gate insulation layer having a first via hole and a pattern of an active layer through a single patterning process, wherein the first via hole is located above the gate connection; sequentially forming a transparent conductive film and a metal film on the substrate, and forming a pattern layer comprising a first electrode and a pattern layer comprising a data line, a source, a drain and a TFT channel through a single patterning process.

Abstract: After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure. A contact via cavity is formed through the planarization dielectric material layer by an anisotropic etch process that employs a fluorocarbon gas as an etchant. The carbon in the carbon-doped semiconductor material portion retards the anisotropic etch process, and the carbon-doped semiconductor material portion functions as a stopping layer for the anisotropic etch process, thereby making the depth of the contact via cavity less dependent on variations on the thickness of the planarization dielectric layer or pattern factors.

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.

Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

Abstract: The present invention provides a manufacturing method of a fin-shaped field effect transistor (FinFET), comprises the following steps. Firstly, providing a substrate having a fin structure; forming a gate structure on the fin structure perpendicular to a extending direction of the fin structure; performing an amorphous implantation to form an amorphous layer on a exposed portion of the fin structure exposed by the gate structure and a light-doping implantation; forming a sacrificial spacer on sides of the gate structure covering a portion of the amorphous layer on the fin structure; forming a trench on the fin structure adjacent to the sacrificial spacer; growing an alloy in the trench; and then removing the sacrificial spacer. The invention also provides a FinFET device thereof.

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a semiconductor layer on a fin, where the fin and the semiconductor layer include first and second semiconductor materials, respectively. Moreover, the method includes defining first and second active fins that include the second semiconductor material, by removing at least a portion of the fin. Related semiconductor devices are also provided.

Abstract: A semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed. The transistor including the oxide semiconductor film subjected to the dehydration or dehydrogenation by the heat treatment and the oxygen doping treatment is a transistor having high reliability in which the amount of change in threshold voltage of the transistor by the bias-temperature stress test (BT test) can be reduced.

Abstract: To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.

Abstract: An all-electric spin field effect transistor is disclosed, which includes an injection node, injecting an electron in a first spin direction; a detection node, detecting the electron in the first spin direction; and a gate, disposed between the injection node and the detection node such that the electron changes from the first spin direction to a second spin direction by carrying out precession; if the second spin direction is parallel to the first spin direction, the electron is able to pass through the detection node; if the second spin direction is antiparallel to the first spin direction, the electron is unable to pass through the detection node.

Abstract: A semiconductor component is described herein. In accordance with one example of the invention, the semiconductor component includes a semiconductor body, which has a top surface and a bottom surface. A body region, which is doped with dopants of a second doping type, is arranged at the top surface of the semiconductor body. A drift region is arranged under the body region and doped with dopants of a first doping type, which is complementary to the second doping type. Thus a first pn-junction is formed at the transition between the body region and the drift region. A field stop region is arranged under the drift region and adjoins the drift region. The field stop region is doped with dopants of the same doping type as the drift region. However, the concentration of dopants in the field stop region is higher than the concentration of dopants in the drift region. At least one pair of semiconductor layers composed of a first and a second semiconductor layer are arranged in the drift region.

Abstract: Disclosed is a semiconductor device including two oxide semiconductor layers, where one of the oxide semiconductor layers has an n-doped region while the other of the oxide semiconductor layers is substantially i-type. The semiconductor device includes the two oxide semiconductor layers sandwiched between a pair of oxide layers which have a common element included in any of the two oxide semiconductor layers. A double-well structure is formed in a region including the two oxide semiconductor layers and the pair of oxide layers, leading to the formation of a channel formation region in the n-doped region. This structure allows the channel formation region to be surrounded by an i-type oxide semiconductor, which contributes to the production of a semiconductor device that is capable of feeding enormous current.

Abstract: A transistor includes source region and drain regions, a channel region, a drift region, a gate, a dummy gate, a gate dielectric layer and an interconnection line. The source and drain regions of a first conductivity type are in a substrate. The channel region of a second conductivity type is in the substrate and surrounds the source region. The drift region of the first conductivity type is beneath the drain region and extends toward the channel region. The gate is over the substrate and overlapped with the channel region and the drift region. The dummy gate is over the drift region and laterally adjacent to the gate. The gate dielectric layer is between the gate and the substrate and between the dummy gate and the drift region. The interconnection line is electrically connected to the dummy gate and configured to provide a voltage potential thereto.

Abstract: A silicon carbide semiconductor device and method of manufacture thereof is made by providing a channel control zone which has impurity concentration distribution increased gradually from a first doping boundary to reach a maximum value between the first doping boundary and a second doping boundary, then decreased gradually toward the second doping boundary, so that the silicon carbide semiconductor device is formed with a lower conduction resistance and increased drain current without sacrificing threshold voltage.

Abstract: An extended-drain transistor is formed in a semiconductor layer arranged on one side of an insulating layer with a semiconductor region being arranged on the other side of the insulating layer. The semiconductor region includes a first portion of a first conductivity type arranged in front of the source and at least one larger portion of the gate and a second portion of a second conductivity type arranged in front of at least the larger portion of the extended drain region, each of the first and second portions being coupled to a connection pad.

Abstract: A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed.

Abstract: Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSFET devices while maintaining a footprint equal to or less than conventional MOSFET devices.

Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in an inverted -symbol shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.