Patents Issued in June 21, 2016
  • Patent number: 9373719
    Abstract: A semiconductor device is provided. The semiconductor device includes an active fin region, at least a gate strip, and a dummy fin region. The active fin region comprises at least an active fin. The gate strip is formed on the active fin region and extending across the active fin. The dummy fin region, comprising a plurality of dummy fins, is formed on two sides of the active fin region, and the dummy fins are formed on two sides of the gate strip.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: June 21, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Fang Hong, Chung-Yi Chiu
  • Patent number: 9373720
    Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: June 21, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Ralf Richter, Peter Javorka
  • Patent number: 9373721
    Abstract: One device disclosed includes a gate structure positioned around a perimeter surface of the fin, a layer of channel semiconductor material having an axial length in the channel length direction of the device that corresponds approximately to the overall width of the gate structure being positioned between the gate structure and around the outer perimeter surface of the fin, wherein an inner surface of the layer of channel semiconductor material is spaced apart from and does not contact the outer perimeter surface of the fin. One method disclosed involves, among other things, forming first and second layers of semiconductor material around the fin, forming a gate structure around the second semiconductor material, removing the portions of the first and second layers of semiconductor material positioned laterally outside of sidewall spacers and removing the first layer of semiconductor material positioned below the second layer of semiconductor material.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: June 21, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Ruilong Xie, Michael Hargrove
  • Patent number: 9373722
    Abstract: The present invention provides a semiconductor structure comprising: a semiconductor base located on an insulating layer, wherein the insulating layer is located on a semiconductor substrate; source/drain regions, which are in contact with first sidewalls of the semiconductor base opposite to each other; gates located on second sidewalls of the semiconductor base opposite to each other; an insulating via located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer sandwiched between the insulating via and the semiconductor base. The present invention further provides a method for manufacturing a semiconductor structure comprising: forming an insulating layer on a semiconductor substrate; forming a semiconductor base on the insulating layer; forming a void within the semiconductor base, wherein the void exposes the semiconductor substrate; forming an epitaxial layer in the void through selective epitaxy; and forming an insulating via within the void.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: June 21, 2016
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 9373723
    Abstract: The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions. And impurity regions provided in the semiconductor film which is not overlapped with the conductive film and provided adjacent to the source and drain regions.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: June 21, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tamae Takano, Atsuo Isobe
  • Patent number: 9373724
    Abstract: Disclosed is a method of driving a transistor including a semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, and a second conductive layer such that the semiconductor layer is disposed between the first and second insulating layers, one surface of the first insulating layer opposite the other surface in contact with the semiconductor layer is in contact with the first conductive layer, one surface of the second insulating layer opposite the other surface in contact with the semiconductor layer is in contact with the second conductive layer. The method includes applying a voltage VBG that satisfies the relation of VBG?VON1×C1/(C1+C2) to the second conductive layer.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: June 21, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hisae Shimizu, Katsumi Abe, Ryo Hayashi
  • Patent number: 9373727
    Abstract: A semiconductor diode includes a semiconductor substrate having a lightly doped region with a first conductivity type therein. A first heavily doped region with a second conductivity type opposite to the first conductivity type is in the lightly doped region. A second heavily doped region with the first conductivity type is in the lightly doped region and is in direct contact with the first heavily doped region. A first metal silicide layer is on the semiconductor substrate and is in direct contact with the first heavily doped region. A second metal silicide layer is on the semiconductor substrate and is in direct contact with the second heavily doped region. The second metal silicide layer is spaced apart from the first metal silicide layer.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: June 21, 2016
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Tung-Hsing Lee
  • Patent number: 9373728
    Abstract: A trench MOS PN junction diode structure includes a first conductive type substrate, a plurality of trenches defined on a face of the first conductive type substrate, a gate oxide layer formed at least on inner sidewalls of the trenches, a polysilicon layer formed in the trenches, a second conductive type low-concentration ion-implanted region formed at least in the first conductive type substrate, a high-concentration ion-implanted region formed below the trenches, and an electrode layer covering the first conductive type substrate, the second conductive type low-concentration ion-implanted region, the gate oxide and the polysilicon layer. The high-concentration ion-implanted region below the trenches provides pinch-off voltage sustention in reversed bias operation to reduce leakage current of the trench MOS PN junction diode structure.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: June 21, 2016
    Assignee: PFC DEVICE HOLDINGS LIMITED
    Inventor: Mei-Ling Chen
  • Patent number: 9373729
    Abstract: Provided is a solar cell. The solar cell includes: a substrate including through lines opposing to each other; a semiconductor layer on a top side of the substrate; bus lines at both edges of a top side of the semiconductor layer; and bus bars connected electrically to the bus lines, respectively, and extending to a rear side of the substrate through the through lines.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: June 21, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Myoung Seok Sung, Se Han Kwon
  • Patent number: 9373730
    Abstract: An optical device manufacturing apparatus includes an encapsulating device for encapsulating an optical semiconductor element 4 mounted on a substrate 2 by a liquid resin R in a lens shape, and a curing device for curing the liquid resin R, wherein the encapsulating device includes a dispenser capable of vertically moving a nozzle 25 for supplying the liquid resin R, and brings the tip of the nozzle 25 close to the optical semiconductor element 4 and then supplies the liquid resin R while raising the nozzle 25. According to this optical device manufacturing apparatus, an optical device having the desired optical properties can be obtained promptly and easily.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: June 21, 2016
    Assignee: SANYU REC CO., LTD.
    Inventors: Yoshiteru Miyawaki, Jun Oki, Daisuke Kounou, Nobuhiko Iwasaki
  • Patent number: 9373731
    Abstract: A dielectric, structure and a method of forming a dielectric structure for a rear surface of a silicon solar cell are provided. The method comprises forming a first dielectric layer over the rear surface of the silicon solar cell, and then depositing a layer of metal such as aluminum over the first dielectric layer. The metal layer is then anodized to form a porous layer and a material layer is deposited over a surface of the porous layer such that the material deposits on the surface of the porous layer without contacting the silicon surface.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: June 21, 2016
    Assignee: NEWSOUTH INNOVATIONS PTY LIMITED
    Inventors: Alison Joan Lennon, Zhongtian Li, Stuart Ross Wenham, Pei Hsuan Lu
  • Patent number: 9373732
    Abstract: An image sensor may be provided having a pixel array that includes optical cavity image pixels. An optical cavity image pixel may include a photosensitive element in a substrate and a reflective cavity formed from a frontside reflector that is embedded in an intermetal dielectric stack, a backside reflector formed in a dielectric layer above the photosensor that partially covers the photosensor, and sidewall reflectors formed in the substrate between adjacent photosensors using deep trench isolation techniques. Each optical cavity image pixel may also include a light-guide trench above the photosensor that guides light into the reflective cavity for that pixel. Each optical cavity pixel may also include color filter material in the trench. Light that is guided into the reflective cavity by the light-guide trench may experience multiple reflections from the reflectors of the reflective cavity before being absorbed and detected by the photosensor.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: June 21, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Sergey Velichko
  • Patent number: 9373733
    Abstract: A semiconductor light-receiving device includes a substrate having a principal surface including first and second areas; a post disposed on the first area, the post including a semiconductor mesa; and a resin layer disposed on the second area in contact with a side surface of the post. The resin layer has, on a ray extending from a first point within the first area through a second point within the second area, a first thickness and a second thickness respectively at a third point and a fourth point that are located within the second area at different distances from the first point. The distance from the first point to the fourth point is larger than the distance from the first point to the third point. The first thickness is larger than the second thickness. The resin layer has a surface that monotonically changes from the first thickness to the second thickness.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: June 21, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yasuhiro Iguchi
  • Patent number: 9373734
    Abstract: A high-efficiency solar cell including an Indium, Gallium, Aluminum and Nitrogen (in a combination comprising InGaN, or InAlN, or InGaAlN) alloy which may be blended with a polyhedral oligomeric silsesquioxane (POSS) material, and which may include an absorption-enhancing layer including one of more of carbon nanotubes, quantum dots, and undulating or uneven surface topography.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: June 21, 2016
    Assignee: Lockheed Martin Corporation
    Inventors: Gregory T. Daly, Michael P. Whelan, Robert C. Bowen, Jr.
  • Patent number: 9373735
    Abstract: A polyimide-metal laminate comprising a polyimide film and a metal layer for use as an electrode, which is formed on the side (Side B) of the polyimide film which was in contact with a support when producing a self-supporting film in the production of the polyimide film, is used to produce a CIS solar cell.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: June 21, 2016
    Assignee: UBE INDUSTRIES, LTD.
    Inventors: Hiroto Shimokawa, Takeshi Uekido, Naoyuki Matsumoto, Ken Kawagishi, Hiroaki Yamaguchi
  • Patent number: 9373736
    Abstract: Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: June 21, 2016
    Assignee: InVisage Technologies, Inc.
    Inventors: Edward Hartley Sargent, Jason Paul Clifford, Gerasimos Konstantatos, Ian Howard, Ethan J. D. Klem, Larissa Levina
  • Patent number: 9373737
    Abstract: Biaxially stretched film with polymeric constituents formed mainly of polyester in which the film includes at least one copper salt and one halide, with the resulting film having an AC (alternating current) dielectric strength of at least 100 kV/mm at 23° C. and 50 Hz. The invention further relates to the use of the film of the invention, in particular in solar modules, and also to a process for its production.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: June 21, 2016
    Assignees: Mitsubishi Polyester Film GmbH, Advansa SaSa Polyester Sanayi A.S.
    Inventors: Holger Kliesch, Bodo Kuhmann, Dagmar Klein, Annegrete Bursch, Rainer Kurz, Dirk Broeder, Ahmet Celalettin Turan, Engin Kuçukaltun, Murat Kolbasi
  • Patent number: 9373738
    Abstract: Provided is a solar module with improved reliability. A solar module (1) is provided with a solar cell (10), a wiring member (11), a resin adhesive layer (12), and a buffer region (40). The wiring member (11) is electrically connected to the solar cell (10). The resin adhesive layer (12) bonds the solar cell (10) and the wiring member (11) to one another. The buffer region (40) is provided at least partially between the wiring member (11) and the solar cell (10). The buffer region (40) contains a non-crosslinked resin.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: June 21, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kenichi Maki, Haruhisa Hashimoto
  • Patent number: 9373739
    Abstract: A solar energy plant/system includes different combinations of solar energy receivers and arrangements of the receivers that make it possible to optimize solar energy collection and conversion into other forms of energy to maximize value.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: June 21, 2016
    Assignee: RAYGEN RESOURCES PTY LTD
    Inventor: John Beavis Lasich
  • Patent number: 9373740
    Abstract: Provided is a wavelength converting structure for near-infrared rays and a solar cell using the same. More particularly, provided is a novel wavelength converting structure for near-infrared rays using gap plasmon characteristics and up-conversion nanoparticles. When applying the wavelength converting structure for near-infrared rays to a solar cell, it is possible to convert the light within a wavelength range of near-infrared rays into electric energy so that the photoconversion efficiency may be improved.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: June 21, 2016
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyungduk Ko, Ho Seong Jang, Doo-Hyun Ko, Il Ki Han, Gi Yong Lee
  • Patent number: 9373741
    Abstract: A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: June 21, 2016
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9373742
    Abstract: Plasma-assisted techniques are provided for fabricating semiconductor devices. In one aspect, a plasma is applied to a substrate before exfoliating layers of a multi-layer structure of atomically thin two-dimensional sheets onto the substrate. The exfoliated layers serve as the basis for constructing a semiconductor device. In another aspect, a p-n junction is formed by applying a plasma to top layers of a multi-layer structure of atomically thin two-dimensional sheets and then exfoliating a portion of the multi-layer structure onto a bottom electrode.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 21, 2016
    Assignee: The Regents Of The University Of Michigan
    Inventors: Xiaogan Liang, Hongsuk Nam, Sungjin Wi, Mikai Chen
  • Patent number: 9373743
    Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: June 21, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9373744
    Abstract: Methods for treating a semiconductor material, and for making devices containing a semiconducting material, are presented. One embodiment is a method for treating a semiconductor material that includes a chalcogenide. The method comprises contacting at least a portion of the semiconductor material with a chemical agent. The chemical agent comprises a solvent, and an iodophor dissolved in the solvent.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: June 21, 2016
    Assignee: First Solar, Inc.
    Inventor: Donald Franklin Foust
  • Patent number: 9373745
    Abstract: A light emitting device according to the embodiment includes a first conductive semiconductor layer; an active layer over the first conductive semiconductor layer; a second conductive semiconductor layer over the active layer; a bonding layer over the second conductive semiconductor layer; a schottky diode layer over the bonding layer; an insulating layer for partially exposing the bonding layer, the schottky diode layer, and the first conductive semiconductor layer; a first electrode layer electrically connected to both of the first conductive semiconductor layer and the schottky diode layer; and a second electrode layer electrically connected to the bonding layer.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 21, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventor: June O Song
  • Patent number: 9373746
    Abstract: A semiconductor light emitting device includes a substrate, a semiconductor laminate disposed on the substrate and divided to a plurality of light emitting cells with an isolation region, and a wiring unit electrically connecting the plurality of light emitting cells. A region of lateral surfaces of each of the light emitting cells in which the wiring unit is disposed has a slope gentler than slopes of other regions of the lateral surfaces of each of the light emitting cells.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: June 21, 2016
    Inventors: Hae Youn Hwang, Pun Jae Choi, Jung Jae Lee
  • Patent number: 9373747
    Abstract: A method for producing an optoelectronic component is provided. A transfer layer, containing InxGa1-xN with 0<x<1, is grown onto a growth substrate. Subsequently, ions are implanted into the transfer layer to form a separation zone, a carrier substrate is applied, and the transfer layer is separated by way of heat treatment. A further transfer layer, containing InyGa1-yN with 0<y?1 and y>x, is grown onto the previously grown transfer layer, ions are implanted into the further transfer layer to form a separation zone, a further carrier substrate is applied, and the further transfer layer is separated by way of heat treatment. Subsequently, a semiconductor layer sequence, containing an active layer, is grown onto the surface of the further transfer layer facing away from the further carrier substrate.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: June 21, 2016
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Joachim Hertkorn, Tetsuya Taki, Karl Engl, Johannes Baur, Berthold Hahn, Volker Haerle, Ann-Kathrin Haerle, Jakob Johannes Haerle, Johanna Magdalena Haerle
  • Patent number: 9373748
    Abstract: The present invention discloses a nitride semiconductor light emitting device with improved light efficiency. The nitride semiconductor light emitting device includes a n-type nitride layer and p-type nitride layer, an active layer disposed between the n-type and p-type nitride layers and with a multiple quantum well structure wherein a plurality of quantum well layers and a plurality of quantum barrier layers are stacked alternatively in the active layer, and a superlattice layer between the active layer and the p-type nitride layer with asymmetric structure. Herein, a thickness of a well layers gradually increases from the p-type nitride layer to the active layer and the height of the barrier layers gradually increases from the active layer to the p-type nitride layer and therefore, an injection efficiency of a hole supplied from p-type nitride layer to an active layer is increased.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 21, 2016
    Assignee: INTELLECTUAL DISCOVERY CO., LTD.
    Inventors: Seong-Ju Park, Sang-Jun Lee, Sang-Hyun Hong, Sang-Jo Kim
  • Patent number: 9373749
    Abstract: Phosphors formed using silicon nanoparticles are provided. The phosphors exhibit bright fluorescence and high quantum yield, making them ideal for lighting applications. Methods for making the silicon phosphors are also provided, along with lighting devices that incorporate the silicon phosphors.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: June 21, 2016
    Assignee: University of Washington through its Center for Commercialization
    Inventors: Chang-Ching Tu, Guozhong Cao, Lih Y. Lin
  • Patent number: 9373750
    Abstract: The present invention provides a Group III nitride semiconductor light-emitting device which exhibits improved light emission efficiency. The light-emitting layer has a MQW structure in which a plurality of layer units are repeatedly deposited, each layer unit comprising a well layer, a capping layer, and a barrier layer sequentially deposited. The well layer is formed of InGaN, the capping layer has a structure in which a GaN layer and an AlGaN layer are deposited in this order on the well layer, and the barrier layer is formed of AlGaN. The AlGaN layer has a higher Al composition ratio than that of the barrier layer. The AlGaN layer in the former portion has a lower Al composition ratio than that of the AlGaN layer in the latter portion when the light-emitting layer is divided into a former portion at the n-cladding layer side and a latter portion at the p-cladding layer side in a thickness direction.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: June 21, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Koji Okuno
  • Patent number: 9373751
    Abstract: A light emitting element includes a first conductivity-type semiconductor layer, a first electrode, a second conductivity-type semiconductor layer and a second electrode. The second conductivity-type semiconductor layer has a square peripheral shape. The first electrode includes a first connecting portion on a first diagonal line and a first extending portion extending from the first connecting portion onto the first diagonal line. The second electrode includes a second connecting portion on the first diagonal line facing the first connecting portion via the first extending portion. Two second extending portions extend from the second connecting portion and having a first portion and a second portion respectively. The first connecting portion includes an end portion closer to the second connecting portion than a straight line intersecting the tip ends of the two second extending portions, and a center portion at a side father from the second connecting portion than the second diagonal line.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 21, 2016
    Assignee: NICHIA CORPORATION
    Inventor: Kosuke Sato
  • Patent number: 9373752
    Abstract: A semiconductor light-emitting element includes, a first semiconductor layer, a second semiconductor layer, a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer, a first electrode connected to the first semiconductor layer, and a second electrode provided on the second semiconductor layer. A side of the second electrode facing to the second semiconductor layer is composed of at least any one of silver and silver alloy. The second electrode has a void having a width of emission wavelength or less of the light-emitting layer in a plane of the second electrode facing to the second semiconductor layer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: June 21, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Katsuno, Yasuo Ohba, Kei Kaneko
  • Patent number: 9373753
    Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structure body and an electrode. The stacked structure body has a first conductivity type first semiconductor layer including a nitride-based semiconductor, a second conductivity type second semiconductor layer including a nitride-based semiconductor, and a light emitting layer provided between the first and second semiconductor layers. The electrode has first, second and third metal layers. The first metal layer is provided on the second semiconductor layer and includes silver or silver alloy. The second metal layer is provided on the first metal layer and includes at least one element of platinum, palladium, rhodium, iridium, ruthenium, osmium. The third metal layer is provided on the second metal layer. A thickness of the third metal layer along a direction from the first toward the second semiconductor layer is equal to or greater than a thickness of the second metal layer.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: June 21, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Katsuno, Yasuo Ohba, Shinji Yamada, Mitsuhiro Kushibe, Kei Kaneko
  • Patent number: 9373754
    Abstract: A laminate capable of emitting light comprises a reflective layer. The reflective layer increases the amount of light output from the laminate. A lighting apparatus containing the improved laminate is also provided.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 21, 2016
    Assignee: NthDegree Technologies Worldwide Inc
    Inventors: Erik John Hasenoehrl, Kenneth Stephen McGuire
  • Patent number: 9373755
    Abstract: A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: June 21, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chen-Hua Yu, Hung-Ta Lin, Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu
  • Patent number: 9373756
    Abstract: Disclosed are a light emitting device. The light emitting device includes first and second light emitting cells on a conductive support member and having a hole. The first and second light emitting cells includes first and second semiconductor layers, and an active layer. First and second conducive layers are between the first light emitting cell and the conductive support member, and a third and fourth conductive layers are between the second light emitting cell and the conductive support member. First insulating layer is between the second and fourth conductive layers and the conductive support member. Second insulating layer is disposed in the hole. The second conductive layer is electrically connected to the first light emitting cells through the hole and the third conductive layer.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: June 21, 2016
    Assignee: LG Innotek Co., Ltd.
    Inventors: Sang Youl Lee, Jung Hyeok Bae, Ji Hyung Moon, Jun O Song
  • Patent number: 9373757
    Abstract: To provide an illumination method and a light-emitting device which are capable of achieving, under an indoor illumination environment where illuminance is around 5000 lx or lower when performing detailed work and generally around 1500 lx or lower, a color appearance or an object appearance as perceived by a person, will be as natural, vivid, highly visible, and comfortable as though perceived outdoors in a high-illuminance environment, regardless of scores of various color rendition metric. Light emitted from the light-emitting device illuminates an object such that light measured at a position of the object satisfies specific requirements. A feature of the light-emitting device is that light emitted by the light-emitting device in a main radiant direction satisfies specific requirements.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 21, 2016
    Assignee: CITIZEN ELECTRONICS CO., LTD.
    Inventor: Hideyoshi Horie
  • Patent number: 9373758
    Abstract: The present disclosure provides a light emitting diode (LED) apparatus. The LED apparatus includes an LED emitter having a top surface; and a phosphor feature disposed on the LED emitter. The phosphor feature includes a first phosphor film disposed on the top surface of the LED emitter and having a first dimension defined in a direction parallel to the top surface of the LED emitter; a second phosphor film disposed on the first phosphor film and having a second dimension defined in the direction; and the second dimension is substantially less than the first dimension.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: June 21, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chi Xiang Tseng, Hsiao-Wen Lee, Tien-Ming Lin, Min-Sheng Wu
  • Patent number: 9373759
    Abstract: The invention relates to a light-emitting semiconductor component, having: a light-emitting semiconductor chip (1) with an active region (11) which, in operation, emits light (31) having a first spectrum; a wavelength conversion element (2) which is positioned remote from the semiconductor chip (1), is downstream of the semiconductor chip (1) in the beam path of the light (31) having the first spectrum and converts the light (31) having the first spectrum at least partially into light (32) having a second spectrum; and a filter layer (3), which reflects at least a part (34) of a light (33) incident on the semiconductor component from the outside. The part (34) of the light (33) incident on the semiconductor component from the outside that is reflected by the filter layer (3) has a visible wavelength range and overlaps a color impression produced by the wavelength conversion element when the semiconductor component is in a switched-off state.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: June 21, 2016
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Alexander Wilm
  • Patent number: 9373760
    Abstract: The invention relates to an optoelectronic semiconductor element that emits mixed-color radiation when in operation. The optoelectronic semiconductor component comprises an optoelectronic semiconductor chip, a conversion element that has a curvature, and a spacer element that is arranged between the optoelectronic semiconductor chip and conversion element. The spacer has a curved surface that faces the conversion element, with the conversion element being in direct contact with the curved surface.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: June 21, 2016
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Alexander Baumgartner, Markus Richter, Hans-Christoph Gallmeier, Tony Albrecht
  • Patent number: 9373761
    Abstract: There is herein described a patterned thin-film wavelength converter which comprises a substrate having a first patterned surface with a first pattern, and a thin film deposited on the first patterned surface. The thin film consists of a wavelength converting material and has a second patterned surface that is distal from the substrate. The second patterned surface has a second pattern that is substantially the same as the first pattern of the substrate. An advantage of the patterned thin-film wavelength converter is that post-deposition processing is not required to produce a textured surface on the wavelength converting material. A method of making the patterned thin-film wavelength converter is also described.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: June 21, 2016
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: Darshan Kundaliya, Jörg Frischeisen, Alan Lenef, Jörg-Erich Sorg, Norwin von Malm
  • Patent number: 9373762
    Abstract: An electronic part package comprises a sealing resin layer, an electronic part and a metal plating pattern layer. The sealing resin layer is provided with a principal surface including a first region that has a bellows-like shape having alternate ridges and valleys and a second region that is flat. The electronic part includes an electrode having a principal surface and is covered by the sealing resin layer except the principal surface, which is surrounded by the second region. The metal plating pattern layer is integrally provided on the first and second regions and on the principal surface of the electrode. A portion of the metal plating pattern layer, the portion located on the first region, has a bellows-like shape having alternate ridges and valleys along an outline of the first region.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: June 21, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Susumu Sawada, Yoshihiro Tomita, Koji Kawakita, Masanori Nomura
  • Patent number: 9373763
    Abstract: LED light source having at least one light-emitting component. The light-emitting component is at least partly protected with a transparent protective material, which contains aliphatic thermoplastic polyurethane (TPU). A light-source band also includes at least one light-emitting component.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: June 21, 2016
    Assignee: MARIMILS OY
    Inventor: Temmo Pitkänen
  • Patent number: 9373764
    Abstract: A semiconductor light emitting element includes: a laminated semiconductor layer in which an n-type semiconductor layer, a light emitting layer and a p-type semiconductor layer are laminated; plural n-side electrodes that are laminated on the n-type semiconductor layer, electrically connected to the n-type semiconductor layer and arranged to surround at least a partial region of the light emitting layer and the p-type semiconductor layer as viewed from a lamination direction; and a p-side electrode that is provided on the p-type semiconductor layer, provided with a reflective property to light outputted from the light emitting layer and electrically connected to the p-type semiconductor layer, the p-side electrode including a connecting portion, which is used for electrical connection with an outside, at a region surrounded by the plural n-side electrodes as viewed from the lamination direction.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: June 21, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Takashi Hodota
  • Patent number: 9373765
    Abstract: An optoelectronic semiconductor chip includes a semiconductor body of semiconductor material, a p-contact layer and an n-contact layer. The semiconductor body includes an active layer intended for generating radiation. The semiconductor body includes a p-side and an n-side, between which the active layer is arranged. The p-contact layer is intended for electrical contacting the p-side. The n-contact layer is intended for electrical contacting the n-side 1b. The n-contact layer contains a TCO layer and a mirror layer, the TCO-layer being arranged between the n-side of the semiconductor body and the mirror layer.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: June 21, 2016
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Markus Maute, Karl Engl, Sebastian Taeger, Robert Walter, Johannes Stocker
  • Patent number: 9373766
    Abstract: An optoelectronic semiconductor component includes an optoelectronic semiconductor chip having a first surface. The semiconductor chip is embedded in a mold body. The first surface is elevated with respect to a top side of the mold body. A reflective layer is arranged on the top side of the mold body.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: June 21, 2016
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Matthias Sabathil, Stefan Illek, Thomas Schwarz
  • Patent number: 9373767
    Abstract: A light emitting device of the invention includes a substrate having a metal on a surface thereof; a light emitting element installed on the surface of the substrate; a wire that connects the light emitting element and the metal; and a light reflecting member that covers the metal, the wire having a first bonding ball that is disposed on a surface of the metal, and an extension that extends above the first bonding ball, and the light reflecting member having a protrusion over the first bonding ball.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: June 21, 2016
    Assignee: NICHIA CORPORATION
    Inventor: Shinya Okura
  • Patent number: 9373768
    Abstract: A flip-chip light-emitting diode (LED) unit includes a substrate, an electrode pad set disposed on the substrate, and three flip-chip LEDs disposed on the electrode pad set in a flip-chip manner and including one first LED and two second LEDs that are spaced apart from the first LED and that are electrically coupled to the first LED in a series configuration.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: June 21, 2016
    Assignee: Genesis Photonics Inc.
    Inventors: Cheng-Yen Chen, Sie-Jhan Wu, Po-Jen Su
  • Patent number: 9373769
    Abstract: A solar energy heat to electricity conversion device is provided that includes a thermally conductive solar receiver having a cylinder with an open end and a cup-shape closed end and a thermally conductive fin disposed on an outside surface of the cup-shape closed end, where the thermally conductive solar receiver is capable of absorbing solar energy directed into the cylinder, a thermoelectric module (TEM) that includes a first plate and a second plate, where the first plate is in contact with a surface of the thermally conductive fin, where the conductive fin is capable of transferring heat to the first plate, and a thermally conductive water block in contact with the TEM that is capable of cooling the TEM, where the water block includes a fluid input and a fluid output, where the TEM generates electricity according to a temperature difference between the first plate and the second plate.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 21, 2016
    Assignee: Santa Clara University
    Inventors: Hohyun Lee, Claire Kunkle, Mark F. Wagner, Rachel Donohoe
  • Patent number: 9373770
    Abstract: An industrial thermoelectric generation assembly and method are provided. A plurality of thermoelectric generation elements is provided. Each element has a first side, a second side opposite the first side, and a lateral surface. A thermally insulative material surrounds the lateral surface of each thermoelectric element. The first side of each thermoelectric element is disposed to contact a process heat source, and the second side is configured to be exposed to an ambient environment. At least two of the plurality of thermoelectric generation elements are wired in series. The thermoelectric generation elements, being good thermal insulators, provide good thermal insulation to the process. Withholding heat within the process (which is desired), is converted to electricity.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: June 21, 2016
    Assignee: Rosemount Inc.
    Inventor: Swapan Chakraborty