Abstract: A technique relates to forming a semiconductor device. A field-effect transistor structure having a substrate, a fin structure patterned in the substrate, a gate stack structure, and an insulator layer is first provided. A non-capacitor region and a capacitor region are then formed on the field-effect transistor structure by masking portions of the field-effect transistor structure with a mask such that a non-capacitor region is masked and a capacitor region is exposed, and etching the insulator layer to further recess the fin structure and gate stack structure within the capacitor region such that a revealed height of the fins within the capacitor region is increased relative to the revealed height of the fins in the non-capacitor region. A high-k layer can be deposited over the recessed fins and gate stack structures and a gate metal can fill the recessed portions therein.

Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor.

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

Abstract: An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use.

Abstract: An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function.

Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.

Abstract: A method for manufacturing a semiconductor device including a plurality of fin field-effect transistor (FinFET) devices, comprises forming a plurality of fins on a substrate, wherein a first portion of the fins corresponds to p-type field-effect transistors, and a second portion of the fins corresponds to n-type field-effect transistors, forming a plurality of gate electrodes on the plurality of the fins, growing a p-type doped epitaxial region at each of a plurality of source/drain regions between predetermined gate electrodes of the p-type field-effect transistors, and growing an n-type doped epitaxial region at one or more areas between gate electrodes of respective adjacent p-type field-effect transistors to create one or more p-n junctions electrically isolating the adjacent p-type field-effect transistors from each other.

Abstract: A semiconductor device including a storage node contact that surrounds three sidewalls of an active region to increase the contact area between the storage node contact and the active region is provided.

Abstract: An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

Abstract: A memory device is provided. The memory device includes a plurality of stack structures, a plurality of first stepped contacts, and a plurality of second stepped contacts. Each of the stack structures extends in a first direction, and includes a first semiconductor layer and a second semiconductor layer. The second semiconductor layer is disposed above the first semiconductor layer. Each of the first stepped contacts extends in a second direction, and a bottom surface thereof is electrically connected to the first semiconductor layers of an i+1th stack structure and an i+2th stack structure, wherein i is an odd number. Each of the second stepped contacts extends in the second direction, and a bottom surface thereof is electrically connected to the second semiconductor layers of an nth stack structure and the i+1th stack structure. The first direction is different from the second direction.

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first stacked layer structure including first to nth semiconductor layers (n is a natural number greater than or equal to 2) stacked in a first direction, and extending in a second direction, and first to nth memory cells provided on surfaces of the first to nth semiconductor layers facing a third direction. The ith memory cell (1?i?n) comprises a second stacked layer structure in which a first insulating layer, a charge storage layer, a second insulating layer, and a control gate electrode are stacked. The second insulating layer has an equivalent oxide thickness smaller than that of the first insulating layer.

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. SSLs run above the conductive layers, each intersection of a pillar and an SSL defining a respective select gate of the pillar. Bit lines run above the SSLs. The pillars are arranged on a regular grid which is rotated relative to the bit lines. The grid may have a square, rectangle or diamond-shaped unit cell, and may be rotated relative to the bit lines by an angle ? where tan(?)=±X/Y, where X and Y are co-prime integers. The SSLs may be made wide enough so as to intersect two pillars on one side of the unit cell, or all pillars of the cell, or sufficiently wide as to intersect pillars in two or more non-adjacent cells.

Abstract: A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.

Abstract: A semiconductor memory device may include stacks arranged in a first direction and vertical channel structures provided through the stacks. Each of the stacks may include gate electrodes and insulating layers alternately stacked on a substrate. Each of the vertical channel structures may include a semiconductor pattern connected to the substrate and a vertical channel pattern connected to the semiconductor pattern. Each of the semiconductor patterns may have a recessed sidewall, and the semiconductor patterns may have minimum widths different from each other.

Abstract: Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material. A channel material panel extends through the stack and along a first direction. The panel divides the stack into a first section on a first side of the panel and a second section on a second side of the panel. Memory cell stacks are between the channel material panel and the control gate material. The memory cell stacks include cell dielectric material shaped as containers having open ends pointing toward the channel material panel, and include charge-storage material within the containers. Some embodiments include methods of forming semiconductor constructions.

Abstract: An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.

Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.

Abstract: A method of forming a field effect transistor (FET) device includes forming a recess in a PFET region of a starting semiconductor substrate comprising a bulk semiconductor layer an epitaxial n+ layer formed on the bulk semiconductor layer, a buried insulator (BOX) layer formed on the epitaxial n+ layer, and an active semiconductor or silicon-on-insulator (SOI) layer formed on the BOX layer, the recess being formed completely through the SOI layer, the BOX layer, and partially into the epitaxial n+ layer; epitaxially growing a silicon germanium (SiGe) transition layer on the epitaxial n+ layer, the SiGe transition layer having a lower dopant concentration than the epitaxial n+ layer; and epitaxially growing embedded source/drain (S/D) regions on the SiGe transition layer and adjacent the SOI layer in the PFET region, the embedded S/D regions comprising p-type doped SiGe.

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Abstract: Disclosed are field effect transistor (FET) formation methods using a final gate cut process and the resulting structures. One method forms an elongated gate across first and second semiconductor bodies for first and second FETs, respectively. An opening is formed in a portion of the elongated gate between the semiconductor bodies, cutting at least the gate conductor layer. The opening is filled with an isolation layer, thereby forming an isolation region that segments the elongated gate into first and second gates for the first and second FETs, respectively. Another method forms at least three gates across an elongated semiconductor body. An isolation region is formed that extends, not only through a portion of a center one of the gates, but also through a corresponding portion of the elongated semiconductor body adjacent to that gate, thereby segmenting the elongated semiconductor body into discrete semiconductor bodies for first and second FETs.

Abstract: The present disclosure provides a thin film transistor and method for repairing the same, GOA circuit and a display device, which aims to solve the problem that the source and/or drain of thin film transistor can not be repaired once it is short circuited with other conductive functional layers. The thin film transistor comprises a source, a drain, and a gate. The source and the drain have a comb shape and respectively comprise a plurality of comb-tooth portions and comb-handle portions for connecting each comb-tooth portion, and the gate is insulated from the source and the drain. Comb-tooth portions of the source are arranged by an interval with respect to comb-tooth portions of the drain. The comb-handle portion of the source and the gate do not overlap in their projections in the vertical direction, and the comb-handle portion of the drain and the gate do not overlap in their projections in the vertical direction.

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.

Abstract: A voltage programmed pixel circuit, display system having the pixel circuit and driving method thereof is provided. The pixel circuit includes a light emitting device, a driving transistor connected to the light emitting device and a programming circuit. The programming circuit adjusts a pixel current during a programming cycle of the pixel circuit.

Abstract: The present invention discloses a polysilicon TFT device and the manufacturing method thereof. The polysilicon TFT device comprises: a scanning line and a data line arranged alternately; a semiconductor layer electrically connected with the scanning line and the data line; and a pixel electrode electrically connected with the semiconductor layer. Multiple channel regions and multiple doped regions are provided sequentially with interval between the connecting point of the semiconductor layer with the data line and the connecting point of the semiconductor layer with the pixel electrode, the channel regions are the portions of the semiconductor layer overlapping the scanning line, the rest portions are the doped regions, the width of at least one said doped region is 0.5˜3 ?m, the ion doping concentration is 2*E11˜5*E15.

Abstract: A thin film transistor array panel includes: first to third gate lines extending in one direction and parallel to each other; a data line insulated from and intersecting the first to third gate lines; a first thin film transistor connected to the first gate line and the data line; a second thin film transistor connected to the second gate line and an output terminal of the first thin film transistor; a third thin film transistor connected to the third gate line and the data line; a fourth thin film transistor connected to the second gate line and an output terminal of the third thin film transistor; and first to fourth sub-pixel electrodes respectively connected to the first to fourth thin film transistors.

Abstract: This semiconductor device (100A) includes: an oxide layer (15) which includes a semiconductor region (5) and a conductor region (7) that contacts with the semiconductor region; a source electrode (6s) and a drain electrode (6d) which are electrically connected to the semiconductor region; an insulating layer (11) formed on the source and drain electrodes; a transparent electrode (9) arranged to overlap at least partially with the conductor region with the insulating layer interposed between them; a source line (6a) formed out of the same conductive film as the source electrode; and a gate extended line (3a) formed out of the same conductive film as a gate electrode (3). The source line is electrically connected to the gate extended line via a transparent connecting layer (9a) which is formed out of the same conductive film as the transparent electrode.

Abstract: The invention belongs to the field of display technology, and particularly provides an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and a thin film transistor and driving electrodes provided on the base substrate, the thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain, the driving electrodes include a slit-shaped electrode and a plate-shaped electrode which are located in different layers and at least partially overlap with each other in the orthographic projection direction, the source, the drain and the active layer are formed so that part of their bottom surfaces are located in the same plane, and a resin layer is further provided between the thin film transistor and the plate-shaped electrode.

Abstract: A TFT array substrate is disclosed. The TFT array substrate includes a TFT area, which includes a TFT first electrode layer, a TFT second electrode layer, a TFT insulation layer, and a TFT etching stop layer. The TFT array substrate also includes also includes a storage capacitor, which includes a capacitor first electrode layer, a capacitor second electrode layer, a capacitor insulation layer, and a capacitor etching stop layer. The TFT first electrode layer and the capacitor first electrode layer are formed in a shared first electrode layer, the TFT second electrode layer and the capacitor second electrode layer are formed in a shared second electrode layer, the TFT insulation layer and the capacitor insulation layer are formed in a shared insulation layer, and the TFT etching stop layer and the capacitor etching stop layer are formed in a shared etching stop layer.

Abstract: A display device includes a first substrate including a protrusion electrode pattern, a second substrate disposed opposite to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The protrusion electrode pattern is made of a conductive polymer material, and a state of the liquid crystal layer changes from an isotropic state to an anisotropic state when an electric field is applied.

Abstract: Provided are a display apparatus and a method of manufacturing the display apparatus. The display apparatus includes: a substrate having a major surface; and a capacitor disposed over the substrate. The capacitor includes a first electrode, and a second electrode disposed over the first electrode. The second electrode includes a first region, a second region and an opening when viewed in a direction perpendicular to the major surface. The first region has a first thickness, and a second region has a second thickness that is greater than the first thickness.

Abstract: An image sensor package includes a crystalline handler having opposing first and second surfaces, and a cavity formed into the first surface. At least one step extends from a sidewall of the cavity, wherein the cavity terminates in an aperture at the second surface. A cover is mounted to the second surface and extends over and covers the aperture. The cover is optically transparent to at least one range of light wavelengths. A sensor chip is disposed in the cavity and mounted to the at least one step. The sensor chip includes a substrate with front and back opposing surfaces, a plurality of photo detectors formed at the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the photo detectors.

Abstract: A solid-state imaging device includes pixels respectively having photoelectric conversion units and arranged in matrix in basic pattern units, and an optical member arranged on the incidence side of incident light than the pixels and having constituent elements respectively corresponding to the pixels. The pixels include first, second and third wavelength range light pixels. Each basic pattern is comprised of a combined arrangement pattern of the wavelength range light pixels. Misregistration constituent elements with the occurrence of misregistration exist in the constituent elements. The misregistration increases toward the misregistration constituent elements separated from a center position of a pixel array of the pixels.

Abstract: An imaging device includes: a photoelectric conversion region that generates photovoltaic power for each pixel depending on irradiation light; and a first element isolation region that is provided between adjacent photoelectric conversion regions in a state of surrounding the photoelectric conversion region.

Abstract: Image sensor and method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including a pixel area, a voltage connection area, and a pad area, a plurality of photoelectric conversion devices in the pixel area, an anti-reflective layer on a back side of the semiconductor substrate and on the plurality of photoelectric conversion devices, a device isolation structure between the plurality of photoelectric conversion devices, at least one voltage connection structure in the voltage connection area, and electrically connected to the device isolation structure, at least one voltage applying device electrically connected to the at least one voltage connection structure, an internal circuit including at least one conductive inner wire and at least one conductive inner via in an insulating layer, and a through via structure in the pad area.

Abstract: A system and method for fabricating a 3D image sensor structure is disclosed. The method comprises providing an image sensor with a backside illuminated photosensitive region on a substrate, applying a first dielectric layer to the first side of the substrate opposite the substrate side where image data is gathered, and applying a semiconductor layer that is optionally polysilicon, to the first dielectric layer. A least one control transistor may be created on the first dielectric layer, within the semiconductor layer and may optionally be a row select, reset or source follower transistor. An intermetal dielectric may be applied over the first dielectric layer; and may have at least one metal interconnect disposed therein. A second interlevel dielectric layer may be disposed on the control transistors. The dielectric layers and semiconductor layer may be applied by bonding a wafer to the substrate or via deposition.

Abstract: A method for manufacturing a solid-state image pickup device is provided. The image pickup apparatus includes a photoelectric conversion portion disposed on the semiconductor substrate, a first insulating film over the photoelectric conversion portion, functioning as an antireflection film, a second insulating film on the first insulating film, disposed corresponding to the photoelectric conversion portion, and a waveguide having a clad and a core whose bottom is disposed on the second insulating film. The method includes forming an opening by anisotropically etching part of a member disposed over the photoelectric conversion portion, thereby forming the clad, and forming the core in the opening. In the method, the etching is performed under conditions where the etching rate of the second insulating film is lower than the etching rate of the member.

Abstract: One or more methods of manufacturing a solid-state image pickup apparatus and one or more methods of manufacturing a light reflection member are provided herein, and one or more embodiments thereof may include forming a first insulating film and forming a photoresist pattern on the first insulating film. Furthermore, one or more embodiments of such methods may include forming an opening portion by removing the first insulating film while having the photoresist pattern serve as a mask and forming a light reflection member on a sidewall of the opening portion formed in the first insulating film.

Abstract: An image sensor package, and method of making same, that includes a printed circuit board having a first substrate with an aperture extending therethrough, one or more circuit layers, and a plurality of first contact pads electrically coupled to the one or more circuit layers. A sensor chip mounted to the printed circuit board and disposed at least partially in the aperture. The sensor chip includes a second substrate, a plurality of photo detectors formed on or in the second substrate, and a plurality of second contact pads formed at the surface of the second substrate which are electrically coupled to the photo detectors. Electrical connectors each electrically connect one of the first contact pads and one of the second contact pads. A lens module is mounted to the printed circuit board and has one or more lenses disposed for focusing light onto the photo detectors.

Abstract: Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. In some embodiments, the electrostatic discharge device and the solid state emitter share a common first contact and a common second contact. In further embodiments, the solid state lighting device and the electrostatic discharge device share a common epitaxial substrate. In still further embodiments, the electrostatic discharge device is positioned between the solid state lighting device and a support substrate.

Abstract: A display panel including: a cathode electrode formed in a cathode region of the display panel, the cathode electrode entirely covering an active region of the display panel a plurality of pixel units in columns and rows in the active region of the display panel; a ring-shaped edge negative voltage line formed in a ring-shaped edge portion of the cathode electrode configured to supply a negative power supply voltage to the cathode electrode; and a plurality of compensation negative voltage lines connected to the ring-shaped edge negative voltage line, the compensation negative voltage lines extending along a column direction of the display panel and arranged along a row direction of the display panel.

Abstract: The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.

Abstract: A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements.

Abstract: A resistance change nonvolatile memory device, includes: a first wiring; an interlayer insulating layer formed over the first wiring; and a second wiring formed over the interlayer insulating layer, wherein the interlayer insulating layer is interposed between the first wiring and the second wiring and includes a hole having a width not greater than a width of the first wiring, wherein the resistance change nonvolatile memory device further includes a lower electrode formed at a bottom portion of the hole and contacting the first wiring; a resistance change layer formed on the lower electrode; and an upper electrode formed over the resistance change layer, wherein the lower electrode, the resistance change layer, and the upper electrode are formed inside the hole, wherein an entirety of the resistance change layer is disposed inside the hole.

Abstract: Systems and methods including bonding two or more separately formed circuit layers are provided using, for example, cold welding techniques. Processing techniques may be provided for combining inorganic and/or organic semiconductor devices in apparatus including, for example, microchips, optoelectronic devices, such as solar cells, photodetectors and organic light emitting diodes (OLEDs), and other apparatus with multi-layer circuitry. Methods of bonding preformed circuit layers may include the use of stamping and pressure bonding contacts of two or more circuit layers together. Such methods may find applicability, for example, in bonding circuitry to shaped substrates, including various rounded and irregular shapes, and may be used to combine devices with different structural properties, e.g. from different materials systems.

Abstract: The present invention provides a display device which inhibits deterioration in display quality caused by color mixture of luminescent layers. In a case where vapor deposition particles are deposited onto a substrate, P+2Lc?{(Ts×M+0.96×G×Wn)/(Ts?G)}+2Dm and 3 ?m?Dm ?5 ?m are satisfied, where “M” is a width of a mask opening, “Wn” is a width of an injection hole, “G” is a distance between the TFT substrate and a vapor deposition mask, “Ts” is a distance between the TFT substrate and a vapor deposition source, “P” is a width of a first pixel opening, and “Lc” is a width of a non-display region.

Abstract: An organic light emitting diode display device and a method of fabricating the organic light emitting diode display device are discussed. The organic light emitting diode display device includes, a plurality of first electrodes extending in a first direction and a second direction; a common line to adjacent plurality of first electrodes; a pixel definition layer disposed at boundaries of the plurality of first electrodes; an adhesive pattern disposed on the common line; a wall on the adhesive pattern and overlapping the common line; an organic layer on the plurality of first electrodes and on the wall; and a second electrode on the organic layer and contacting the common line in a portion under an overhang of the wall, wherein the organic layer is spaced apart from the adhesive pattern by a distance, and wherein the distance is covered by a portion of the second electrode.