Abstract: The present invention is concerned with a device for charged particle transportation and manipulation. Embodiments provide a capability of combining positively and negatively charged particles in a single transported packet. Embodiments contain an aggregate of electrodes arranged to form a channel for transportation of charged particles, as well as a source of power supply that provides supply voltage to be applied to the electrodes, the voltage to ensure creation, inside the said channel, of a non-uniform high-frequency electric field, the pseudopotential of which field has one or more local extrema along the length of the channel used for charged particle transportation, at least, within a certain interval of time, whereas, at least one of the said extrema of the pseudopotential is transposed with time, at least within a certain interval of time, at least within a part of the length of the channel used for charged particle transportation.

Abstract: An ion guide for mass spectrometry comprising an electrode arrangement of at least two electrodes, at least one of which is an RF electrode, arranged adjacent to each other but spaced apart on a planar surface of a dielectric material and arranged at a distance from an ion flow path, wherein a portion of the dielectric surface is exposed between an adjacent pair of the spaced apart electrodes and wherein at least one electrode of said adjacent pair of electrodes is arranged to overhang the exposed portion of surface between them such that there is no direct line of sight from the ion flow path to the exposed portion of dielectric surface. The device enables RF guiding of ions accompanied by much reduced charging-up of dielectric surfaces and reduced amount of collisions of neutral species with electrodes.

Abstract: A field terminator includes a plurality of electrode plates positioned around a guide axis at a radial distance therefrom. The plates generate a quadrupole DC field such that a polarity on each plate is opposite to a polarity on the plates adjacent thereto. The plates may be positioned at an axial end of a quadrupole ion guide such as a mass filter. In addition to an RF field, the ion guide may generate a quadrupole DC field. The DC field of the plates may be opposite in polarity to that of the ion guide.

Abstract: A method of constructing an ion guide is disclosed comprising providing an elongated spine member and a plurality of plates. Each plate comprises an aperture therethrough for receiving the spine member and at least one electrode for use in guiding ions. The apertures of the plates are arranged around the spine member and the plates are arranged along the spine member. The plates are then locked in position on the spine member such that the plates are fixed axially with respect to the spine member and so that the electrodes of the plates are arranged so as to form an array of electrodes for use in guiding ions.

Abstract: A liquid sampling, atmospheric pressure, glow discharge (LS-APGD) device as well as systems that incorporate the device and methods for using the device and systems are described. The LS-APGD includes a hollow capillary for delivering an electrolyte solution to a glow discharge space. The device also includes a counter electrode in the form of a second hollow capillary that can deliver the analyte into the glow discharge space. A voltage across the electrolyte solution and the counter electrode creates the microplasma within the glow discharge space that interacts with the analyte to move it to a higher energy state (vaporization, excitation, and/or ionization of the analyte).

Abstract: MALDI-TOF MS systems have solid state lasers and successive and varied delay times between ionization and acceleration (e.g. extraction) to change focus masses during a single sample signal acquisition without requiring tuning of the MS by a user. The (successive) different delay times can change by 1 ns to about 500 ns, and can be in a range that is between 1-2500 nanoseconds.

Abstract: A flight-of-time mass spectrometer is offered which can provide a variable range of collisional energies that can be made wider than heretofore. Also, a method of controlling this spectrometer is offered. The spectrometer has an ion source, a first mass analyzer, an ion gate, a potential lift, a collisional cell, a second mass analyzer, a detector, and a potential control portion for controlling the potential on the potential lift. When the precursor ions selected by the ion gate enter the potential lift, the potential control portion sets the potential on the conductive box at V1. When the potential on the potential lift is varied, the potential control portion varies the potential on the potential lift from V1 to V2 while precursor ions are traveling through the potential lift.

Abstract: A lamp assembly for the lamp assembly adapted for use in a substrate thermal processing chamber to heat the substrate to temperatures up to at least about 1100° C. is disclosed. In one embodiment, the lamp assembly comprises a bulb enclosing at least one radiation generating filament attached to a pair of leads, the bulb having an inner surface and an outer surface, a lamp base configured to receive the pair of leads and at least a portion of the bulb having a surface treatment adapted to reflect light away from the lamp base. In another embodiment, a sleeve covers the lamp base, which has a cross-sectional area less than about 1.2 times the cross-sectional area of the bulb.

Abstract: Embodiments of the present invention generally relate to a tubular lamp with a coiled filament having an overwind wrapped around the coil. In one embodiment, the tubular lamp has a coiled coil filament, and the coiled coil has an overwind wrapped around the coiled coil.

Abstract: A composition and method for removing copper-containing post-etch and/or post-ash residue from patterned microelectronic devices is described. The removal composition includes water, a water-miscible organic solvent, an amine compound, an organic acid, and a fluoride ion source. The compositions effectively remove the copper-containing post-etch residue from the microelectronic device without damaging exposed low-k dielectric and metal interconnect materials.

Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).

Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a film on a substrate by performing a cycle a predetermined number of times, wherein the cycle includes non-simultaneously performing: supplying a precursor gas to the substrate in a process chamber; exhausting the precursor gas in the process chamber through an exhaust system; confining a reaction gas, which differs in chemical structure from the precursor gas, in the process chamber by supplying the reaction gas to the substrate in the process chamber while the exhaust system is closed; and exhausting the reaction gas in the process chamber through the exhaust system while the exhaust system is opened.

Abstract: A method of preparing graphene includes supplying a gas on a metal catalyst, the gas including CO2, CH4, and H2O, and reacting and cooling the resultant.

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method for reducing substrate bowing resulting from the formation of strained SiGe layers having a high percentage of germanium (“high concentration SiGe”) on silicon substrates. During the epitaxial growth of the high concentration SiGe layer, carbon dopant atoms may be introduced to the crystalline lattice structure of the SiGe, forming a SiGe:C layer. The carbon dopant atoms may reduce tensile strain in the SiGe:C layer during annealing, thereby reducing substrate bowing.

Abstract: A process of fabricating a nanostructure is disclosed. The process is effected by growing the nanostructure in situ within a trench formed in a substrate and having therein a metal catalyst selected for catalyzing the nanostructure growth, under the conditions in which the growth is guided by the trench. Also disclosed are nanostructure systems comprising a nanostructure, devices containing such systems and uses thereof.

Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: forming a first doped region having a first conductivity in a substrate; forming a second doped region having a second conductivity different from the first conductivity in the substrate, the second doped region disposed laterally adjacent to and spaced apart from the first doped region; and oxidizing a semiconductive layer disposed between the substrate and the second doped region to form an oxidized isolation layer.

Abstract: A plurality of mandrels is formed on a silicon substrate. The mandrels are spaced apart at a given pitch, wherein at least one of the plurality of mandrels is formed having a first width, and at least another one of the plurality of mandrels is formed having a second width, and wherein the first width is greater than the second width. At least one structure is formed by removing at least a portion of the plurality of mandrels in a sidewall image transfer process without using a cut mask.

Abstract: A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the semiconductor body with protons and irradiating the semiconductor body with electrons. After the process of irradiating with protons and after the process of irradiating with electrons, the semiconductor body is subjected to heat treatment in order to attach the protons to vacancies by means of diffusion.

Abstract: The method for performing activation of n-type or p-type dopants in a GaN-base semiconductor includes the following steps: providing a substrate including a GaN-base semiconductor material layer, performing the following successive steps at least twice: implanting electric dopant impurities in the semiconductor material layer, performing heat treatment so as to activate the electric dopant impurities in the semiconductor material layer, a cap layer covering the semiconductor material layer when the heat treatment is performed, two implantation steps of electric dopant impurities being separated by a heat treatment step.

Abstract: The present disclosure provides a method for forming a Lateral Double-Diffused MOSFET (LDMOS). The method includes providing a semiconductor substrate having a first conductivity type; forming a first shallow trench isolation (STI) structure in the semiconductor substrate; and applying a first ion implantation to form a drift region of a second conductivity type into the semiconductor substrate with the drift region surrounding the first STI structure. The method also includes applying a counter-doping implantation to form a counter-doped region having the first conductivity in the drift region and forming a body region on one side of the drift region in the semiconductor substrate. The method further includes forming a gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region another end of the gate structure extends to an area on the first STI region.

Abstract: An embodiment for realizing a power device with trench-gate structure integrated on a semiconductor substrate, and including etching the semiconductor substrate to make a first trench having first side walls and a first bottom; and further etching said semiconductor substrate to make a second trench inside the first trench, realized in a self-aligned way and below this first trench, the first trench and the second trench defining the trench-gate structure with a bird beak-like transition profile suitable for containing a gate region.

Abstract: In an embodiment, this disclosure relates to a method of creating an alignment feature within a sidewall image transfer process by the addition of a block mask. The presence of the alignment feature would enable better overlay and alignment for subsequent lithographic stacks.

Abstract: A tungsten film forming method for forming a tungsten film on a surface of a target substrate by an ALD (atomic layer deposition) method comprises adding a reduction gas to allow an ALD reaction to mainly occur when a tungsten chloride gas is supplied. In the ALD method, the tungsten chloride gas as a tungsten source gas and the reduction gas for reducing the tungsten chloride gas are alternately supplied into a chamber which accommodates the target substrate and is maintained under a depressurized atmosphere, with a purge process for purging an inside of the chamber performed between the supply of the tungsten chloride gas and the supply of the reduction gas.

Abstract: Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed.

Abstract: A method is for treating a doped gallium nitride substrate of a first conductivity type, having dislocations emerging on the side of at least one of its surfaces. The method may include: a) forming, where each dislocation emerges, a recess extending into the substrate from the at least one surface; and b) filling the recesses with doped gallium nitride of the second conductivity type.

Abstract: Various embodiments herein relate to methods and apparatus for performing anisotropic ion beam etching to form arrays of channels. The channels may be formed in semiconductor material, and may be used in a gate-all-around device. Generally speaking, a patterned mask layer is provided over a layer of semiconductor material. Ions are directed toward the substrate while the substrate is positioned in two particular orientations with respect to the ion trajectory. The substrate switches between these orientations such that ions impinge upon the substrate from two opposite angles. The patterned mask layer shadows/protects the underlying semiconductor material such that the channels are formed in intersecting shadowed regions.

Abstract: A method for slope control of ion energy is described. The method includes receiving a setting indicating that an etch operation is to be performed using a radio frequency (RF) pulse signal. The RF pulse signal includes a first state and a second state. The first state has a higher power level than the second state. The method further includes receiving a pulse slope associated with the RF pulse signal. The pulse slope provides a transition between the first state and the second state. Also, the pulse slope is other than substantially infinite for reducing an amount of ion energy during the etch operation. The method includes determining power levels and timings for achieving the pulse slope and sending the power levels and the timings to an RF generator to generate the RF pulse signal.

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

Abstract: A method for forming patterns for semiconductor device includes following steps. A substrate is provided. The substrate includes a hard mask layer and a sacrificial layer formed thereon. A plurality of spacer patterns parallel with each other are formed on the substrate. A plurality of first blocking layers are formed in the sacrificial layer after forming the spacer patterns. A plurality of second blocking layers exposing at least a portion of the sacrificial layer and at least a portion the first blocking layer are formed on the substrate after forming the first blocking layer. Next, the sacrificial layer and the hard mask layer are etched with the spacer patterns, the first blocking layers and the second blocking layer being used as etching masks to form a patterned hard mask layer on the substrate.

Abstract: The present invention provides a slurry for chemical mechanical polishing comprising water-soluble clathrate compound (a), polymer compound (b) having an acidic group optionally in a salt form as a side chain, polishing abrasive grain (c) and water (d), wherein the content of the water-soluble clathrate compound (a) is 0.001 mass %-3 mass % of the total amount of the slurry, the polymer compound (b) has a weight average molecular weight of not less than 1,000 and less than 1,000,000, and the content of the polymer compound (b) is 0.12 mass %-3 mass % of the total amount of the slurry, and a polishing method for substrate using the slurry.

Abstract: A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad.

Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.

Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.

Abstract: One or more embodiments are directed to semiconductor packages that are assembled using a sacrificial material, that when removed, separates the assembled packages into individual packages. The sacrificial material may be removed by a blanket technique such that a mask, pattern, or alignment step is not needed. In one embodiment the sacrificial material is formed on the lead frame on a connecting bar of a lead frame between adjacent leads. After the molding step, the connecting bar is etched away exposing a surface of the sacrificial material. The sacrificial material is removed, thereby separating the assembled packages into individual packages.

Abstract: A cleaning method using vaporized solvent is provided. A solvent-containing vapor is generated, wherein the solvent-containing vapor comprises a solvent. The solvent-containing vapor is conducted to a substrate having debris or contaminants to clean the substrate, wherein the solvent-containing vapor condenses to form a liquid on a surface of the substrate. The liquid phase of the solvent-containing vapor is changed to a solid phase. The solid phase of the solvent-containing vapor is changed back to a liquid phase. The substrate is spun dried to remove the solvent-containing vapor in liquid phase and any debris or contaminants.

Abstract: A semiconductor substrate can include two or more electrodes, located directly or indirectly on the semiconductor substrate, separated from each other and capacitively coupled to the semiconductor substrate. At the two or more electrodes, non-zero frequency time-varying electrical energy can be received. The time-varying electrical energy can be capacitively coupled via the two or more electrodes to trigger a displacement current to activate free carriers confined within the semiconductor substrate to generate heat in the semiconductor substrate. A temperature associated with the semiconductor substrate can be sensed, using a temperature sensor located in association with the semiconductor substrate. A temperature of the semiconductor substrate can be established or adjusted. This can include controlling the electrical energy received at the two or more electrodes using information received from the temperature sensor.

Abstract: A baking apparatus for baking a wafer is provided. The baking apparatus includes a wafer chuck configured to hold the wafer, and a heating device disposed over the wafer chuck and configured to heat the wafer. The baking apparatus also includes a carrying arm configured to transport the wafer over the wafer chuck. The wafer chuck is in physical contact with the center area of the bottom surface of the wafer when the wafer is held by the wafer chuck.

Abstract: A semiconductor die encapsulation or carrier-mounting method and apparatus for manufacturing a semiconductor product, wherein a first tool part for holding multiple semiconductor dies is provided and the semiconductor dies are placed on the first tool part, one of the first and a second tool part including displaceable insert members applying a pressure by each displaceable insert member on a surface area of the semiconductor die, and the first and second tool parts are brought together to define a space between the first and second tool parts with the semiconductor products being arranged within the space. The pressure applied by the displaceable insert members is monitored and regulated to a predetermined pressure, and subsequently, the first and second tool parts are separated and the processed semiconductor dies removed.

Abstract: A substrate liquid processing apparatus includes a cup 50 configured to receive a processing liquid supplied onto a substrate. The cup includes a ring-shaped first exhaust space 530 in contact with a top opening 50A, and a ring-shaped second exhaust space 540 which is in contact with an exhaust port 52 and is disposed adjacent to the first exhaust space, and the first exhaust space and the second exhaust space communicate with each other intermittently or continuously along an entire circumference thereof. Further, the cup has an inner wall that confines an inner periphery of the second exhaust space, and the inner wall includes a first wall portion 581 serving as an upper part of the inner wall, and a second wall portion which serves as a lower part of the inner wall and is located at an inner position than the first wall portion in a radial direction.

Abstract: A thermal processing apparatus is provided in accordance with some embodiments. The thermal processing apparatus includes a heating source for transmitting incident radiation to a work piece having a circuit pattern formed on a front surface; a radiation sensor configured to receive light radiated from the front surface of the work piece; and a controller coupled to the radiation sensor, the controller being designed to control the heating source to reduce temperature variation of the work piece.

Abstract: In an embodiment, the present invention discloses cleaned storage processes and systems for high level cleanliness articles, such as extreme ultraviolet (EUV) reticle carriers. A decontamination chamber can be used to clean the stored workpieces. A purge gas system can be used to prevent contamination of the articles stored within the workpieces. A robot can be used to detect the condition of the storage compartment before delivering the workpiece. A monitor device can be used to monitor the conditions of the stocker.

Abstract: An end effector of a wafer transfer system includes synchronously movable blades operable to hold and release wafers. The end effector comprises an end effector housing including a first blade mount coupled to a first blade, a second blade mount coupled to a second blade, and an actuator operable to move the blade mounts on respective linear rails. The actuator includes a longitudinally movable piston coupled to the respective blade mounts by respective actuator links. The actuator links are pivotally coupled to the longitudinally movable piston at respective first ends thereof and to the first and second blade mounts at respective second ends thereof wherein moving the piston towards a retracted position causes the blades to synchronously move laterally towards each other and moving the piston towards the retracted position causes the blades to synchronously move laterally away from each other so as to hold or release a wafer.

Abstract: A load port unit can prevent or control leakage of inert gas from an EFEM system to the outside. The load port unit used in the EFEM system is provided with an air inlet that opens on a side facing a mini-environment between the upper end of an opener driving unit and the lower end of the pod. The width of the air inlet opening is larger than the width of the opening of the pod. With this arrangement, surplus gas is sucked from the pod when gas purging is performed on the pod.

Abstract: An article transport carriage includes a carriage main body configured to travel along a travel path, a support portion configured to support a bottom surface of an article from below, a projecting and retracting actuator for projecting and retracting the support portion between a projected position and a retracted position, a pressure applying portion located directly above the article supported by the support portion in the retracted position, and a distance changing actuator for changing the distance in the vertical direction between the support portion and the pressure applying portion between a pressure applying distance and a spaced apart distance.

Abstract: The present disclosure relates to a material handling method of performing by means of an automatic mechanical material handling equipment controlled by a control system at least a first and a second access task for accessing respectively at least a first and at least a second article stored in a material handling storage system, the first and second access tasks having been assigned a first and a second execution priority respectively.

Abstract: Embodiments provided herein generally relate to an electrostatic chuck (ESC). The ESC may comprise a reduced number of stress initiation points, such as holes through the ESC, which may improve the mechanical integrity of the ESC. Electrodes disposed within the ESC may be connected to electrical contacts and a power source via conductive leads, which may be coupled or formed along a peripheral edge of the ESC. Thus, the need for holes formed in the ESC may be reduced or eliminated. In addition, gas channels may be formed on a top surface, a bottom surface, or both. The gas channels may reduce or eliminate the need for a gas channel formed through the ESC and may facilitate heat transfer between a substrate support, the ESC, and a substrate coupled to the ESC.

Abstract: Implementations described herein provide a chucking circuit for a pixilated electrostatic chuck which enables both lateral and azimuthal tuning of the RF coupling between an electrostatic chuck and a substrate placed thereon. In one embodiment, a chucking circuit for an electrostatic chuck (ESC) has one or more chucking electrodes disposed in a dielectric body of the ESC, a plurality of pixel electrodes disposed in the dielectric body, and a chucking circuit having the one or more chucking electrodes and the plurality of pixel electrodes, the chucking circuit operable to electrostatically chuck a substrate to a workpiece support surface of the ESC, the chucking circuit having a plurality of secondary circuits, wherein each secondary circuit includes at least one capacitor of a plurality of capacitors, each secondary circuit is configured to independently control an impedance between one of the pixel electrodes and a ground.

Abstract: An apparatus for processing wafer-shaped articles includes a rotary chuck adapted to hold a wafer shaped article thereon. The rotary chuck includes a peripheral series of pins configured to contact an edge region of a wafer-shaped article. Each of the pins projects upwardly from the rotary chuck, and each of the pins is individually secured to the rotary chuck by a respective connecting mechanism. Any selected one of the pins can be removed from the rotary chuck by disconnecting its corresponding connecting mechanism without removing any structure of the rotary chuck that surrounds any others of the pins.