Abstract: A system and method for providing intermediate reactive species from a remote plasma unit to a reaction chamber are disclosed. The system includes a pressure control device to control a pressure at the remote plasma unit as intermediate reactive species from the remote plasma unit are provided to the reaction chamber.

Abstract: Disclosed is a plasma processing apparatus capable of more accurately controlling plasma. The plasma processing apparatus includes a shower head provided within a processing chamber, in which a substrate accommodated therein is processed, to be faced to a mounting table for mounting the substrate and supply gas from a plurality of gas discharging holes provided on a facing surface that faces the mounting table toward a substrate in a shower pattern; a plurality of exhaust holes that passes through a surface located at an opposite side to the facing surface of the shower head; a circular plate-like body that is disposed parallel to the opposite surface in a exhaust space that communicates with the exhaust holes distributed at the opposite surface and made of a conductive material; and a moving unit configured to move the plate-like body to change a distance between the exhaust holes and the plate-like body.

Abstract: The present invention is a plasma generation source and a thing that is in its application and it is for getting high quality thin film by generating even high density plasma in high vacuum and like this plasma generation source applying like this plasma generation source to sputtering system, neutral particle beam source, thin film deposition system combining sputtering system and neutral particle beam source. According to the present invention, it generates plasma by using microwave through the microwave irradiating equipment and magnetic field by more than one pair of the belt type magnets and above goal can be accomplished maximizing plasma confinement effect by inducing electron returning trajectory in accordance with above continuous structure on belt type magnet.

Abstract: Embodiments described herein relate to methods for determining a cleaning endpoint. A first plasma cleaning process may be performed in a clean chamber environment to determine a clean time function defined by a first slope. A second plasma cleaning process may be performed in an unclean chamber environment to determine a clean time function defined by a second slope. The first and second slope may be compared to determine a clean endpoint time.

Abstract: The present invention relates to an electron multiplier and others to effectively suppress luminescence noise, even in compact size, in which each of multistage dynodes has a plurality of columns each having a peripheral surface separated physically, and in which each column is processed in such a shape that an area or a peripheral length of a section parallel to an installation surface on which the electron multiplier is arranged becomes minimum at a certain position on the peripheral surface in the column of interest.

Abstract: A mass spectrometry (MS) system may be cleaned by generating plasma and contacting an internal surface of the system to be cleaned with the plasma. The system may be switched between operating in an analytical mode and in a cleaning mode. In the analytical mode a sample is analyzed, and plasma may or may not be actively generated. In the cleaning mode the plasma is actively generated, and the sample may or may not be analyzed.

Abstract: A dual-ionization mass spectrometer includes a first mass spectrometer module forming a hard ionization mass spectrometer, a second mass spectrometer forming a soft ionization mass spectrometer, a vacuum ultraviolet light source positioned between the first and second modules, a housing encompassing the first and second sets of plates and the light source, and an inlet positioned to receive a sample of an analyte and provide it to at least one of the sets of plates. A method of detecting a substance includes receiving a sample of an analyte into a housing through an inlet, performing soft ionization mass spectrometry on the sample with a soft ionization mass spectrometer in the housing, performing hard ionization spectrometry on the sample with a hard ionization spectrometer in the housing if needed, and generating a detection result from at least one of the soft ionization spectrometry and the hard ionization spectrometry.

Abstract: A guide apparatus includes a vacuum compartment provided at a background pressure and having a gas inlet opening arranged for jetting a gas in the form of a free jet stream containing entrained ions into a vacuum chamber along a predetermined jetting axis. At least one duct housed within the vacuum chamber has a guide bore positioned coaxially with the jetting axis for receiving the free jet stream such that a supersonic free jet is formed in the duct with a jet pressure ratio P1/P2 restrained to a value that does not exceed (A/a)3 to form a subsonic laminar gas flow inside of the duct for guiding the entrained ions, where P1 is the pressure at an exit end of the gas inlet opening, P2 is the background pressure, A is the cross sectional area of the bore, and a is the cross sectional area of the gas inlet opening.

Abstract: Aspects and embodiments of the present invention are directed to spectrometry systems and for apparatus and methods for delivering dopants to same. In one example, there is provided a dopant delivery device configured to supply dopants to a spectrometry system comprising a tube including a first chamber and a second chamber, a first dopant source included in the first chamber, and a second dopant source included in the second chamber.

Abstract: The invention relates to methods and devices for analysis of samples using laser ablation inductively coupled plasma mass spectrometry (LA-ICP-MS). The invention provides methods and devices in which individual ablation plumes are distinctively captured and transferred to the ICP, followed by analysis by mass cytometry.

Abstract: Certain embodiments described herein are directed to systems including a cell downstream of a mass analyzer. In some instances, the cell is configured as a reaction cell, a collision cell or a reaction/collision cell. The system can be used to suppress unwanted ions and/or remove interfering ions from a stream comprising a plurality of ions.

Abstract: A curved ion guide includes four curved rod electrodes arranged around a curved central axis, two deflecting auxiliary electrodes which face each other across the axis, and two focusing auxiliary electrodes which are located on a curved surface orthogonal to the plane P and including the axis and which face each other across the axis. Ions are focused by the effect of an electric field created by radio-frequency voltages applied to the curved rod electrodes, and a deflecting electric field having the effect of curving ions along the axis is created by direct-current voltages applied to the deflecting auxiliary electrodes. Furthermore, a focusing direct-current electric field having the effect of pushing ions from the vicinity of the focusing auxiliary electrodes toward the axis is created by a direct-current voltage having the same polarity as that of the ions and applied to the focusing auxiliary electrodes.

Abstract: Techniques are provided for generating charged droplets of liquid entrained within a gas flow within a vacuum chamber and for controlling the gas flow. The gas flow with the entrained charged droplets of liquid is jetted into the vacuum chamber along a predetermined jetting axis. The gas jet is received within a gas conduit housed within the vacuum chamber and having a conduit bore coaxial with the predetermined jetting axis. The received gas jet is caused to be restrained to form a laminar gas flow entrained with charged droplets inside of the gas conduit for guiding the entrained charged droplets therealong.

Abstract: The present invention relates to a method for improving the wettability of a rotating electrode with a liquid medium in a discharge lamp, in particular for the production of EUV radiation or soft X-rays, and a correspondingly designed gas discharge lamp. In the method, the edge surface of the rotating electrode to which the liquid medium is applied is microstructured by means of external processing. This microstructure significantly improves the wettability of the edge surface for the liquid medium. Furthermore, the distribution of the liquid medium over the edge surface can be controlled selectively by suitable choice of the microstructure.

Abstract: The invention relates to an illuminant having a gas volume and a coaxial HF energy coupling device for the excitation thereof using surface waves. It is provided in this case that the coaxial HF energy coupling device (3) has a central conductor (4) guided in the gas volume (2).

Abstract: The present disclosure provides one embodiment of a method. The method includes applying a first cleaning fluid to a substrate, thereby cleaning the substrate and forming a protection layer on the substrate; and applying a removing process to the substrate, thereby removing the protection layer from the substrate. The first cleaning fluid includes a cleaning chemical, a protection additive and a solvent.

Abstract: A method for polishing a polymer surface is provided by an embodiment of the present invention. The method includes: curing the polymer surface; polishing the polymer surface cured through a CMP process. By using the method for polishing a polymer surface provided by embodiments of the present invention, the mentioned problems in the prior art are solved. The uniformity of the polymer surface can be improved to <1% through a CMP process, which can meet the requirements of high density and small linewidth integration.

Abstract: The present invention makes it possible to increase the reliability of a semiconductor device. A manufacturing method of a semiconductor device according to the present invention includes a step of removing a patterned resist film and the step of removing a patterned resist film includes the steps of: (A) introducing at least a gas containing oxygen into a processing room; (B) starting electric discharge for transforming the gas containing oxygen into plasma; and (C) introducing a water vapor or an alcohol vapor into the processing room. On this occasion, the step (C) is applied either simultaneously with or after the step (B).

Abstract: Provided are a polymer for an underlayer film, used in semiconductor and display manufacturing processes, an underlayer film composition for semiconductor and display manufacturing processes, containing the same, and a method for forming an underlayer film for semiconductor and display manufacturing processes using the underlayer film composition. The polymer according to the present invention is a polymer including a repeating unit represented by the following Chemical Formula 1: in Chemical Formula 1, Ar, R1 to R6, L, and R? and R? are the same as those in the detailed description of the present invention.

Abstract: A sol composition for producing a porous low-k dielectric material is provided. The composition can include at least one silicate ester, a polar solvent, water, an acid catalyst for silicate ester hydrolysis, an amphiphilic block copolymer surfactant, and a nonmetallic catalyst that reduces dielectric constant in the produced material. The composition can further include a metallic ion at a lower parts-per-million concentration than the nonmetallic catalyst, and/or the composition can further include a cosolvent. A method of preparing a thin film on a substrate using the sol composition is also provided.

Abstract: Provided herein are methods of depositing conformal silicon nitride films using atomic layer deposition by exposure to a halogen-free, N—H-bond-free, and carbon-free silicon-containing precursor such as disilane, purging of the precursor, exposure to a nitrogen plasma, and purging of the plasma at low temperatures. A high frequency plasma is used, such as a plasma having a frequency of at least 13.56 MHz or at least 27 MHz. Methods yield substantially pure conformal silicon nitride films suitable for deposition in semiconductor devices, such as in trenches or features, or for memory encapsulation.

Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.

Abstract: High quality ammonothermal group III metal nitride crystals having a pattern of locally-approximately-linear arrays of threading dislocations, methods of manufacturing high quality ammonothermal group III metal nitride crystals, and methods of using such crystals are disclosed. The crystals are useful for seed bulk crystal growth and as substrates for light emitting diodes, laser diodes, transistors, photodetectors, solar cells, and for photoelectrochemical water splitting for hydrogen generation devices.

Abstract: Described herein are semiconductor structures comprising laterally varying II-VI alloy layer formed over a surface of a substrate. Further, methods are provided for preparing laterally varying II-VI alloy layers over at least a portion of a surface of a substrate comprising contacting at least a portion of a surface of a substrate within a reaction zone with a chemical vapor under suitable reaction conditions to form a laterally varying II-VI alloy layer over the portion of the surface of the substrate, wherein the chemical vapor is generated by heating at least two II-VI binary compounds; and the reaction zone has a temperature gradient of at least 50-100° C. along an extent of the reaction zone. Also described here are devices such as lasers, light emitting diodes, detectors, or solar cells that can use such semiconductor structures.

Abstract: A hot wire device and method for depositing semiconductor material onto a substrate in a deposition chamber in which the ends of at least two filaments are clamped into a filament holder and heated by supplying current, wherein a voltage for generating an electrical current is applied in temporal succession to filaments made of differing materials so that a number of differing semiconductors corresponding to the number of consecutively heated filament materials can be consecutively deposited onto the substrate without opening the chamber.

Abstract: In a method of forming an epitaxial layer, an etching gas may be decomposed to form decomposed etching gases. A source gas may be decomposed to form decomposed source gases. The decomposed source gases may be applied to a substrate to form the epitaxial layer on the substrate. A portion of the epitaxial layer on a specific region of the substrate may be etched using the decomposed etching gases. Before the etching gas is introduced into the reaction chamber, the etching gas may be previously decomposed. The decomposed etching gases may then be introduced into the reaction chamber to etch the epitaxial layer on the substrate. As a result, the epitaxial layer on the substrate may have a uniform distribution.

Abstract: The present invention relates to a method of defining poly-silicon growth direction. The method of defining poly-silicon growth direction comprises Step 1, forming a buffer layer on a substrate; Step 2, forming an amorphous silicon thin film on the buffer layer; Step 3, forming regular amorphous silicon convex portions on the amorphous silicon thin film; and Step 4, transferring the amorphous silicon thin film into poly-silicon with an excimer laser anneal process. The growth direction of the poly-silicon as being formed can be controlled according to the present method of defining poly-silicon growth direction. Accordingly, the grain size of the poly-silicon can be raised.

Abstract: The present disclosure advances the art by providing a method and system for forming electronic devices. In particular, and by example only, methods are described for forming devices for harvesting energy in the terahertz frequency range on flexible substrates, wherein the methods provide favorable accuracy in registration of the various device elements and facilitate low-cost R2R manufacturing.

Abstract: A method of forming a semiconductor device includes forming a dielectric layer over a substrate. The method includes forming a layer set over the dielectric layer, wherein the layer set comprises a plurality of layers. The method further includes forming a bottom antireflective coating (BARC) layer over the layer set. The method further includes etching the layer set to form a tapered opening in the layer set, wherein etching the layer set comprises etching at least one layer comprising a silicon-rich photoresist material layer and a second material layer different from the silicon-rich photoresist material, and the tapered opening has sidewalls at an angle with respect to a top surface of the dielectric layer. The method further includes etching the dielectric layer using the layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the layer set.

Abstract: Methods of forming high etch selectivity, low stress ashable hard masks using plasma enhanced chemical vapor deposition are provided. In certain embodiments, the methods involve pulsing low frequency radio frequency power while keeping high frequency radio frequency power constant during deposition of the ashable hard mask using a dual radio frequency plasma source. According to various embodiments, the low frequency radio frequency power can be pulsed between non-zero levels or by switching the power on and off. The resulting deposited highly selective ashable hard mask may have decreased stress due to one or more factors including decreased ion and atom impinging on the ashable hard mask and lower levels of hydrogen trapped in the ashable hard mask.

Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate and forming spacer features on sidewalls of the lines. The method further includes shrinking the spacer features using a wet process. After the shrinking of the spacer features, the method further includes removing the lines thereby providing the shrunk spacer features over the substrate.

Abstract: Substrates may be bonded according to a method comprising contacting a first bonding surface of a first substrate with a second bonding surface of a second substrate to form an assembly in the presence of an steam atmosphere under suitable conditions to form a bonding layer between the first and second surfaces, wherein the first bonding surface comprises a polarized surface layer; the second bonding surface comprises a hydrophilic surface layer; the first and second bonding surfaces are different.

Abstract: A method of doping a substrate. The method may include implanting a dose of a helium species into the substrate through a surface of the substrate at an implant temperature of 300° C. or greater. The method may further include depositing a doping layer containing a dopant on the surface of the substrate, and annealing the substrate at an anneal temperature, the anneal temperature being greater than the implant temperature.

Abstract: This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The lining oxide layer peripherally encloses the second side surface of the semiconductor fin. The silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface.

Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.

Abstract: An IC structure including: a first replacement gate stack for the pFET, the first replacement gate stack including: an interfacial layer in a first opening in the dielectric layer; a high-k layer over the interfacial layer in the first opening; a pFET work function metal layer over the high-k layer in the first opening; and a first gate electrode layer over the pFET work function metal layer and substantially filling the first opening; and a second replacement gate stack for the nFET, the second gate stack laterally adjacent to the first gate stack and including: the interfacial layer in a second opening in the dielectric layer; the high-k layer over the interfacial layer in the second opening; a nFET work function metal layer over the high-k layer in the second opening; and a second gate electrode layer over the nFET work function metal layer and substantially filling the second opening.

Abstract: A method for eliminating interlayer dielectric (ILD) dishing and controlling gate height uniformity is provided. Embodiments include forming a plurality of polysilicon gates over a substrate, each gate having spacers formed on sides of the polysilicon gates and a nitride cap formed on an upper surface; forming a gapfill material between adjacent polysilicon gates; forming an oxide over the gapfill material between the adjacent polysilicon gates; removing the nitride caps; removing a portion of the oxide between the adjacent polysilicon gates, forming a recess; and forming an ILD cap layer in the recess between the adjacent polysilicon gates.

Abstract: Methods for depositing extremely low resistivity tungsten in semiconductor processing are disclosed herein. Methods involve annealing the substrate at various times during the tungsten deposition process to achieve uniform tungsten layers with substantially lower resistivity.

Abstract: A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiH4 base W film on a surface of a substrate to preprocess the surface. The method includes depositing a B2H6 base W layer on the preprocessed surface. The SiH4 base W film may be several atom layers thick. The film and base W layer may be deposited in a single ALD process, include reactive gas soak, reactive gas introduction, and main deposition operations. Forming the film may include introducing SiH4 gas into a reactive cavity during the gas soak operation, and introducing SiH4 and WF6 gas into the cavity during the gas introduction operation. The SiH4 and WF6 gases may be alternately introduced, for a number of cycles depending on the thickness of the tungsten layer to be deposited.

Abstract: A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.

Abstract: A method may include providing a patterned feature extending from a substrate plane of a substrate, the patterned feature including a semiconductor portion and a coating in an unhardened state extending along a top region and along sidewall regions of the semiconductor portion; implanting first ions into the coating, the first ions having a first trajectory along a perpendicular to the substrate plane, wherein the first ions form a etch-hardened portion comprising a hardened state disposed along the top region; and directing a reactive etch using second ions at the coating, the second ions having a second trajectory forming a non-zero angle with respect to the perpendicular, wherein the reactive etch removes the etch-hardened portion at a first etch rate, wherein the first etch rate is less than a second etch rate when the second ions are directed in the reactive etch to the top portion in the unhardened state.

Abstract: A fabrication method of a semiconductor piece includes forming a groove that has a first groove portion, and a second groove portion which is a groove portion formed to communicate with a lower part of the first groove portion and extends toward a lower part at a steeper angle than an angle of the first groove portion, has a shape without an angle portion between the first groove portion and the second groove portion, is positioned on the front side, and is formed by dry etching; affixing a retention member including an adhesive layer to the surface in which the groove on the front side is formed; thinning the substrate from the back side of the substrate in a state in which the retention member is affixed; and removing the retention member from the surface after the thinning.

Abstract: A stage unit may include a frame, a first guide device, a stage, a second guide device and a pad. The first guide device may be arranged over an upper surface of the frame and configured to guide the stage in a first direction. The stage may be movably connected to the first guide device. The second guide device may be arranged over an upper surface of the stage and configured to guide the pad in a second direction substantially perpendicular to the first direction. The pad may be movably connected to the second guide device and configured to support a substrate. Therefore, the substrate may be supported by and uniformly floated by the frame, the stage and the pad.

Abstract: A semiconductor device package may include: a semiconductor chip element; and a supporting structure on which the semiconductor chip element is mounted and including an electrical connection element for connecting the semiconductor chip element to an external terminal. The supporting structure may include: a first lead frame including a heat dissipation element; a second lead frame coupled to the first lead frame; and/or an insulator configured to electrically insulate the first and second lead frames from each other. Each of the first and second lead frames may include a mounting region on which the semiconductor chip element is mounted. The first lead frame may include: a first portion; and/or a second portion formed on the first portion and having a smaller width than that of the first portion. The insulator may be on the first portion around the second portion. The second lead frame may be on the insulator.

Abstract: An IC packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a metal pad and an insulating layer and the insulating layer has an opening to expose the meal pad. The method also includes forming an under-the-ball meal electrode on the exposed metal pad. The under-the-ball metal electrode has an electrode body and an electrode tail, the electrode body is located at a bottom portion of the under-the-ball metal electrode and is in contact with the metal pad, and the electrode tail is located at a top portion of the under-the-ball meal electrode. Further, the method includes forming a solder ball on the under-the-ball metal electrode.

Abstract: A blanket includes a releasable base; and a sacrificial layer being provided on the base and separated from the base in printing.

Abstract: A dryer comprising an enclosure and a transporter for transporting one or more components therethrough between a first and a second opening. The dryer includes one or more heating elements and a first and a second duct within the enclosure. The first and said second duct each include a plurality of openings configured for discharging heated air towards the one or more components. An exhaust stack in fluid communication with an interior of the enclosure includes an exhaust blower for extracting fluid from within the enclosure, and one or more heating elements for oxidizing the vaporized compounds. The supply and the exhaust blowers cooperatively operate to induce infiltration of air through the first and the second opening. A method for operating the dryer is also provided.

Abstract: An apparatus for treating a wafer-shaped article includes a rotary chuck configured to hold a wafer-shaped article of a predetermined diameter such that a surface of the wafer-shaped article facing the rotary chuck is spaced from an upper surface of the rotary chuck. A ring is mounted on the rotary chuck, and includes a first upper surface overlapping an outer peripheral edge of a wafer-shaped article when positioned on the rotary chuck and a second upper surface positioned radially inwardly of the first surface. The second upper surface is elevated relative to the first upper surface, to define an annular gap between the second upper surface and a wafer-shaped article when positioned on the spin chuck that is smaller than a distance between the first upper surface and a wafer-shaped article when positioned on the rotary chuck.

Abstract: A substrate processing apparatus includes a robot having: an end effector, a first link structure including a fixing portion having a front end to which the end effector is fixed, a support portion, and a first hole formed in the support portion, a second link structure including a second hole, and a shaft inserted into the first and second holes, the shaft including an upper end having a height equal to or smaller than a height of the substrate mounted on the end effector; a vacuum transfer chamber, wherein the robot is installed in the vacuum transfer chamber; at least one process chamber disposed adjacent to the vacuum transfer chamber and configured to thermally process the substrate transferred from the vacuum transfer chamber by the robot; a module including one or more process chambers; and a cooling mechanism installed above the first link structure or the shaft.