Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes a wafer chuck configured to hold a wafer, and a first nozzle configured to dispense first chemical liquid onto the wafer. The semiconductor apparatus also includes a second nozzle configured to dispense second chemical liquid onto the wafer at a first dispensing time after the first nozzle stops dispensing the first chemical liquid. The semiconductor apparatus also includes an image device configured to take images of the first nozzle and the second nozzle in sequence, and a processing module configured to analyze the images. The processing module adjusts the first dispensing time when a first defect image shows the first chemical liquid and the second chemical liquid existing in a space close to the first and the second nozzles and flowing to the wafer.

Abstract: A supporting portion of an article transport device supports a position detection device for detecting the position of a detection target object. A control device executes an update control to update target position information in accordance with an update instruction issued through a manual operation performed by an operator during a maintenance operation performed at an interval longer than a set period, and executes the update control on condition that an elapsed time since issuance of the update instruction has reached an automatic updating time that is a time shorter than the set period.

Abstract: A substrate transfer method includes a step of placing a first and a second substrate on a first and a second alignment part which are arranged to be vertically spaced from each other by using a first and a second pick. The method further includes a first positioning step of positioning the first pick at a first reception position determined based on an alignment position for the first substrate, a first receiving step of receiving the first substrate from the first alignment part by moving the first pick. The method further includes a second positioning step of positioning the second pick at a second reception position determined based on an alignment position for the second substrate, and a second receiving step of receiving the second substrate from the second alignment part by moving the second pick.

Abstract: A mounting table includes an electrostatic chuck, a base, and a cylindrical sleeve. The electrostatic chuck has a top surface to be exposed to plasma and a bottom surface opposite to the top surface, and a first through-hole is formed through the electrostatic chuck. The base is bonded to the bottom surface of the electrostatic chuck by a first adhesive, and a second through-hole is formed through the base. The second through-hole communicates with the first through-hole and has a diameter larger than a diameter of the first through-hole. The sleeve is bonded to the bottom surface of the electrostatic chuck by a second adhesive while communicating with the first through-hole.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes a process of applying liquid to one surface of a support substrate; a process of warping the support substrate by a volume change due to a phase transition of the liquid by solidifying the liquid; a process of attaching a semiconductor substrate having a linear expansion coefficient different from that of the support substrate to the support substrate in a heated state; and a process of warping the support substrate due to a linear expansion coefficient difference between the semiconductor substrate and the support substrate by cooling the support substrate to which the semiconductor substrate is attached. A warping direction due to the phase transition is opposite to a warping direction due to the linear expansion coefficient difference.

Abstract: A glass substrate transfer system and a robot arm thereof are provided. The robot arm includes: a substrate fork, a moving assembly and a vacuum chuck. The substrate fork is for taking a glass substrate. The moving assembly is connected with the substrate fork and for making the substrate fork to be moved in a working space. The vacuum chuck is disposed on the substrate fork and for sucking the glass substrate. The vacuum chuck is formed with a fluid path, and the fluid path is contained with a cooling fluid to dissipate heat of the vacuum chuck. The glass substrate transfer system and its robot arm provided by the present invention cool the vacuum chuck in time and thus can avoid affecting the product quality caused by the vacuum chuck being overheated, and the product yield is improved.

Abstract: A sample holder includes a substrate composed of ceramics, having a sample holding surface provided in an upper face thereof; a supporting member composed of metal, an upper face of the supporting member covering a lower face of the substrate; and a joining layer composed of indium or an indium alloy, the substrate and the supporting member being joined to each other via the joining layer. The joining layer has a layer region in at least one of a joining surface to the substrate and a joining surface to the supporting member, a content percentage of indium oxides of the layer region being higher than that of an intermediate region in a thickness direction of the joining layer.

Abstract: A method of manufacturing a semiconductor device that involves etching a trench in a semiconductor substrate, epitaxially growing a crystalline structure in the trench and forming semiconductor structures on either side of the crystalline structure. Crystalline oxides may include rare earth oxides, aluminum oxides or Perovskites.

Abstract: A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides.

Abstract: A method includes forming a plurality of fins on a semiconductor substrate by defining a plurality of trenches in the substrate. A first insulating material layer comprising silicon, oxygen and carbon is formed in the trenches between the plurality of fins. The first insulating material layer has an upper surface that is at a level that is below an upper surface of the fins. A second insulating material layer is formed above the first insulating material layer. The second insulating material layer is planarized to expose a top surface of the plurality of fins. The second insulating material layer is removed to expose the first insulating material layer.

Abstract: A method for transferring a useful layer onto a support includes the following processes: formation of a fragilization plane through the implantation of light species into a first substrate in such a way as to form a useful layer between this plane and a surface of the first substrate; application of the support onto the surface of the first substrate to form an assembly to be fractured having two exposed sides; thermal fragilization treatment of the assembly to be fractured; and initiation and self-sustained propagation of a fracture wave in the first substrate along the fragilization plane. At least one of the sides of the assembly to be fractured is in close contact, over a contact zone, with an absorbent element suitable for capturing and dissipating acoustic vibrations emitted during the initiation and/or propagation of the fracture wave.

Abstract: A method for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.

Abstract: One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas.

Abstract: Techniques for preventing leakage of contact material into air-gap spacers during contact formation. For example, a method comprises forming a contact trench on a semiconductor structure over an air-gap spacer and depositing a liner in the contact trench. The liner deposition material fills a portion of the air-gap spacer pinching off the contact trench to the air-gap spacer.

Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a thin film transistor on a base substrate, and an electrode structure on the thin film transistor, and the electrode structure includes a pixel electrode and a common electrode insulated from each other. The array substrate further includes: a black matrix disposed on the thin film transistor, an orthographic projection of the thin film transistor on the base substrate is located within an orthographic projection of the black matrix on the base substrate, and the black matrix is electrically connected with the common electrode for providing common electrode signals to the common electrode.

Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.

Abstract: One illustrative method disclosed herein includes, among other things, forming a first conductive structure and a second conductive structure that is conductively coupled to the first conductive structure. In this example, forming the second conductive structure includes forming a ruthenium cap layer on and in contact with an upper surface of the first conductive structure, with the ruthenium cap layer in position, forming a liner layer comprising manganese on and in contact with at least the surfaces of the second layer of insulating material, wherein an upper surface of the ruthenium cap layer is substantially free of the liner layer, and forming a bulk ruthenium material on and in contact with the liner layer, wherein a bottom surface of the bulk ruthenium material contacts the upper surface of the ruthenium cap layer.

Abstract: The present disclosure relates to an electrode manufacturing method, and a fuse device and manufacturing method therefor. The fuse device includes a fuse element including a phase change material, and a first electrode formed in contact with the fuse element. The phase change material may include doped or undoped chalcogenide. The first electrode may have a sublithographic dimension at a portion where the first electrode contacts the fuse element. When the phase change material has a layer thickness less than or equal to about 30 nm, and a pulse current less than or equal to about 3 mA is applied to the fuse element via the first electrode, the fuse element may undergo a phase change, so as to convert the fuse device into a blow-out state.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.

Abstract: Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding.

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

Abstract: A method for fabricating an electronic package is provided, including the steps of: providing at least a packaging structure, wherein the packaging structure has a packaging substrate having opposite first and second sides, an electronic element disposed on the first side of the packaging substrate and a plurality of conductors formed on the first side of the packaging substrate; encapsulating the packaging structure with an insulating layer, wherein the insulating layer covers the packaging substrate; and forming an RDL (Redistribution Layer) structure on the insulating layer, wherein the RDL structure is electrically connected to the conductors. Therefore, the area of the insulating layer is not required to correspond to the area of the packaging substrate, thus allowing the area of the packaging substrate to be reduced according to the practical need so as to reduce the width of the electronic package.

Abstract: A method of fabricating a semiconductor package is disclosed. The method includes disposing semiconductor chips on a support substrate, forming a protection layer covering top surfaces of the semiconductor chips, forming a molding layer covering the support substrate and the protection layer, and etching the molding layer to expose the protection layer.

Abstract: The manufacturing efficiency of a semiconductor device is improved. A method for manufacturing a semiconductor device includes a step of sealing a semiconductor chip using a mold die having a cavity, a gate part communicating with the cavity, and a vent part provided opposite to the gate part via the cavity, and extending in a first direction in a sealing step. Further, a lead frame has a first through hole provided at a position overlapping the cavity in the sealing step, and a second through hole provided outside the first through hole, and provided at a position overlapping the vent part in the sealing step. Whereas, in a second direction crossing with the first direction, the length of the second through hole is larger than the length (groove width) of the vent part.

Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and applying a pressure substantially uniformly along the second major surface to batch separate the layer of material in the singulation lines. In one embodiment, a fluid filled vessel can be used to apply the pressure.

Abstract: A method is provided for forming a fin cut that enables a single diffusion break in very dense CMOS structures formed using bulk semiconductor substrates. A dummy gate is removed from a finned structure to expose the top regions of the fins, the bottom fin regions being within a shallow trench isolation region. Selective vapor phase etching follows sequential ion implantation of the top and bottom fin regions to form a diffusion break cut region. The non-implanted regions of the substrate and the shallow trench isolation region remain substantially intact during each etching procedure. Double diffusion break cut regions are also enabled by the method.

Abstract: A method for forming a semiconductor device is provided. First, a dielectric layer is provided on a substrate, wherein a first recess and a second recess are formed in the dielectric layer. After a mask layer is filled into the first recess and the second recess, the mask layer in the second recess is removed away, thereby forming a patterned mask layer. Subsequently, a nitride treatment is performed to remove unwanted residue of the mask layer in the second recess.

Abstract: Techniques relate to forming an integrated circuit. Trench contacts are formed on top of at least one source and drain of an intermediate structure. An interlayer dielectric is formed on top of the intermediate structure. A trench is cut through the interlayer dielectric, through at least one of the trench contacts, down to a shallow trench isolation area. The trench is filled with a filling material. Upper contacts are formed on top of the trench contacts in the interlayer dielectric. A first metal layer pattern is patterned such that a separation is formed by a filling material width of the filling material. First metal layers are formed according to the first metal layer pattern, where tips of the first metal layers are aligned to the filling material that fills the trench, such that the tips of the first metal layers are separated by the filling material width.

Abstract: Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.

Abstract: Controlled recessing of materials in cavities and resulting devices are disclosed.

Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.

Abstract: Methods are disclosed including applying a layer of binder material onto an LED structure. A luminescent solution including an optical material suspended in a solution is atomized using a flow of pressurized gas, and the atomized luminescent solution is sprayed onto the LED structure including the layer of binder material using the flow of pressurized gas.

Abstract: A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.

Abstract: The present disclosure provides in various aspects an alignment monitoring structure and method for monitoring the alignment between a target gate conductor and the corresponding target contact in a semiconductor device, for example, in a CMOS. In accordance with some illustrative embodiments herein, a structure with a plurality of gate conductors disposed over the substrate so as to define a row of parallel gate conductors and a plurality of first contacts is provided, wherein each of the first contacts is disposed between two adjacent gate conductors so as to define a first lateral distance between a first gate conductor and the first contact and a second lateral distance between the first contact and a second gate conductor, and wherein the first lateral distance and the second lateral distance vary systematically along the row of parallel gate conductors.

Abstract: A common interconnect ring is provided at a periphery of a portion used to form a TFT array of an X-ray flat panel detector, and an X-ray flat panel detector TFT array substrate connected to signal lines and scanning lines via pairs of two protection diodes connected in parallel and having mutually-reverse polarities is manufactured. When inspecting the X-ray flat panel detector TFT array substrate, the same reference bias voltage as the amplifier of a detection circuit is applied from an external voltage application pad provided at the vicinity of a connection unit for the common interconnect ring and the protection diodes on the same side of the signal lines, a signal is provided to a scanning line connection pad to switch the thin film transistor ON, and an electrical signal flowing through the signal line is read from a signal line connection pad.

Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Abstract: A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

Abstract: An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound.

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.

Abstract: A power module and a thermal interface structure are provided herein. The thermal interface structure includes: a base and a plurality of filler particles distributed in the base. When the filler particles are under pressure, at least a part of the filler particles are deformed, and at least two adjacent filler particles partially contact with each other to form a heat-conducting path for transferring heat.

Abstract: The present disclosure relates to a substrate with an embedded sintered heat spreader and a process for making the same. According to an exemplary process, at least one cavity is created through the substrate. Sinterable paste including metal particulates and binder material is then dispensed into the at least one cavity. Next, the sinterable paste is sintered to create a sintered heat spreader, which is characterized by high thermal conductivity. The sintered heat spreader adheres to the inside walls of the at least one cavity, enhancing the overall thermal conductivity of the substrate.

Abstract: An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a semiconductor die having second stages of power amplifier disposed over a module substrate. The module substrate includes a plurality of layers, pluralities of vias, and pluralities of routing layers for heat dissipation and electrical connections.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device includes: a semiconductor element having a gate and source electrodes; an insulating substrate which is provided with an insulating plate, a first circuit plate and a second circuit plate, the first circuit plate provided in a main surface of the insulating plate to be electrically connected to the gate electrode, the second circuit plate provided in the main surface to surround the first circuit plate and to be electrically connected to the source electrode; a first terminal, being column-shaped and electrically and mechanically connected to the first circuit plate; and a second terminal which is provided with a cylindrical body portion and support portions, the body portion has a through hole into which the first terminal is inserted with a gap, the support portions disposed in end portions of the body portion and electrically and mechanically connected to the second circuit plate.

Abstract: Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules.

Abstract: Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die.

Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.