Patents Issued in March 7, 2017
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Patent number: 9589921Abstract: In one semiconductor device, a semiconductor chip has first and second pad electrodes disposed on the main surface thereof, insulating films that cover the main surface of the semiconductor chip, a rewiring layer that is disposed between the insulating films, and a plurality of external terminals disposed on the top of the insulating film. The plane size of the first pad electrode and the second pad electrode differ from one another, and the first pad electrode and the second pad electrode are connected to any of the plurality of external terminals via the rewiring layer.Type: GrantFiled: March 10, 2014Date of Patent: March 7, 2017Assignee: PS4 LUXCO S.A.R.L.Inventors: Mitsuaki Katagiri, Yu Hasegawa, Satoshi Isa
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Patent number: 9589922Abstract: An electronic module is provided, which comprises a first carrier; an electronic chip comprising at least one electronic component and arranged on the first carrier; a spacing element comprising a surface arranged on the electronic chip and being in thermal conductive connection with the at least one electronic component; a second carrier arranged on the spacing element; and a mold compound enclosing the electronic chip and the spacing element at least partially; wherein the spacing element comprises a material having a CTE value being matched with at least one other CTE.Type: GrantFiled: March 16, 2014Date of Patent: March 7, 2017Assignee: Infineon Technologies AGInventors: Christian Neugirg, Andreas Grassmann, Wolfram Hable, Ottmar Geitner, Frank Winter, Alexander Schwarz, Inpil Yoo
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Patent number: 9589923Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.Type: GrantFiled: August 31, 2015Date of Patent: March 7, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kenya Hironaga, Masatoshi Yasunaga, Tatsuya Hirai, Soshi Kuroda
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Patent number: 9589924Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar, wherein the conductive trace comprises a width WT and a thickness TT, the recess portion of the substrate comprises a width WR in the width direction of the conductive trace and a depth DR, and the ratio of WR to WT ranges from about 0.25 to about 1.8 and the ratio of DR to TT ranges from about 0.1 to about 3.Type: GrantFiled: August 28, 2014Date of Patent: March 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jiun Yi Wu, Yu-Min Liang
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Patent number: 9589925Abstract: Disclosed is a method for bonding with a silver paste, the method including: coating a silver paste on a semiconductor device or a substrate, the silver paste containing silver and indium; disposing the semiconductor on the substrate; and heating the silver paste to form a bonding layer, wherein the semiconductor device and the substrate are bonded to each other through the bonding layer, and wherein the indium is contained in the silver paste at 40 mole % or less.Type: GrantFiled: July 15, 2015Date of Patent: March 7, 2017Assignee: HYUNDAI MOTOR COMPANYInventors: Kyoung-Kook Hong, Hyun Woo Noh, Youngkyun Jung, Dae Hwan Chun, Jong Seok Lee, Su Bin Kang
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Patent number: 9589926Abstract: A method of manufacturing a semiconductor device that includes: preparing a pair of substrates that respectively include a device structure on one primary surface or another primary surface thereof; stacking the substrates so that said one primary surfaces face each other, exposing said another surfaces to the outside, and fixing entire peripheral outer edges of the substrates that have been stacked to each other; and thereafter, plating said exposed another primary surfaces of the stacked and fixed substrates.Type: GrantFiled: November 3, 2015Date of Patent: March 7, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventor: Shoji Sakaguchi
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Patent number: 9589927Abstract: An embodiment of a packaged RF amplifier device includes a device substrate, a transistor die coupled to the device substrate, and an isolation structure coupled to the transistor die. The transistor die has a top die surface, a bottom die surface, a semiconductor substrate, first and second transistors formed in the semiconductor substrate, a conductive structure at the top die surface and positioned between the first and second transistors, and a low resistance path that extends vertically through the semiconductor substrate between the conductive structure and the bottom die surface. The isolation structure is coupled to the conductive structure and extends into an area above the top die surface between the first and second transistors. The isolation structure may be a wirebond fence, a conductive wall, conductive pillars or vias, or a plated trench that extends vertically upward from the conductive structure. The device may be encapsulated with molding compound.Type: GrantFiled: September 25, 2014Date of Patent: March 7, 2017Assignee: NXP USA, INC.Inventors: Margaret A. Szymanowski, Kimberly J. Foxx, Robert A. Pryor
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Patent number: 9589928Abstract: A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.Type: GrantFiled: November 25, 2014Date of Patent: March 7, 2017Assignee: NXP USA, INC.Inventors: Zhigang Bai, Jinzhong Yao, Lan Chu Tan
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Patent number: 9589929Abstract: In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.Type: GrantFiled: March 14, 2013Date of Patent: March 7, 2017Assignee: Vishay-SiliconixInventors: Kyle Terrill, Frank Kuo, Sen Mao
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Patent number: 9589930Abstract: A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, wherein each of the semiconductor chips includes a plurality of bonding pads provided on a respective edge region thereof, wherein at least some of the plurality of bonding pads are functional pads, and wherein the functional pads occupy a region that is substantially less than an entirety of the respective edge region.Type: GrantFiled: December 31, 2014Date of Patent: March 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul Park, Kilsoo Kim, In Lee
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Patent number: 9589931Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.Type: GrantFiled: April 27, 2015Date of Patent: March 7, 2017Assignee: Etron Technology, Inc.Inventors: Bor-Doou Rong, Chun Shiah
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Patent number: 9589932Abstract: Representative methods are disclosed for fabricating device packages having a plurality of dies, a molding compound extending along sidewalls of the plurality of dies, and a polymer layer over and contacting the molding compound. The molding compound comprises a non-planar top surface, and a total thickness variation (TTV) of a top surface of the polymer layer is less than a TTV of the non-planar top surface of the molding compound. The device package further includes a conductive feature on the polymer layer, wherein the conductive feature is electrically connected at least one of the plurality of dies.Type: GrantFiled: June 6, 2016Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chung-Shi Liu
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Patent number: 9589933Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.Type: GrantFiled: June 23, 2014Date of Patent: March 7, 2017Assignee: Micron Technology, Inc.Inventors: Aibin Yu, Wei Zhou, Zhaohui Ma, Bret K. Street
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Patent number: 9589934Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.Type: GrantFiled: September 27, 2013Date of Patent: March 7, 2017Assignee: Intel CorporationInventor: Junfeng Zhao
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Patent number: 9589935Abstract: A package apparatus includes a first package module, a second package module and multiple conductive elements. The first package module includes a first molding compound layer, a first conductive pillar layer disposed in the first molding compound layer, a first internal component, and a first protection layer. The first internal component electrically connects to the first conductive pillar layer and disposed in the first molding compound layer. The first protection layer is disposed on the first molding compound layer and the first conductive pillar layer. The second package module includes a second molding compound layer, a second conductive pillar layer disposed in the second molding compound layer, and a second internal component. The second internal component electrically connects to the second conductive pillar layer and disposed in the second molding compound layer. The conductive elements are disposed between the first and the second conductive pillar layers.Type: GrantFiled: December 8, 2014Date of Patent: March 7, 2017Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chu-Chin Hu, Shih-Ping Hsu, E-Tung Chou
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Patent number: 9589936Abstract: Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer.Type: GrantFiled: February 10, 2015Date of Patent: March 7, 2017Assignee: Apple Inc.Inventors: Jun Zhai, Kunzhong Hu, Flynn P. Carson
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Patent number: 9589937Abstract: The invention provides a semiconductor cooling method that comprises: providing two wafers which require to be treated by a mixed bonding process, wherein each of the wafers being provided with several metallic device structure layers therein. A heat dissipation layer is set in at least one of the wafers and arranged in the free area above at least one of the metallic device structure layers, and the heat dissipation layer connects to the adjacent metallic device structure layer and the invention provides a method of heat dissipation that comprises providing at least two wafers to be bonded; and arranging some conducting wires on a surface of wafers. In addition, the method includes the steps of performing a bonding process to form a device with bonded wafers, wherein one end of the conducting wires locates in the region where the wafers generate heat, and another end extends to an external of wafers.Type: GrantFiled: July 29, 2015Date of Patent: March 7, 2017Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shaoning Mei, Jun Chen, Jifeng Zhu, Weihua Cheng
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Patent number: 9589938Abstract: Embodiments of the present disclosure include devices and methods of forming the same. An embodiment is a device including a solder resist coating over a first side of a substrate, an active surface of a die bonded to the first side of the substrate by a first connector, and a surface mount device mounted to the die by a second set of connectors, the surface mount device being between the die and the first side of the substrate, the surface mount device being spaced from the solder resist coating.Type: GrantFiled: December 28, 2015Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Ying-Ju Chen
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Patent number: 9589939Abstract: An optoelectronic semiconductor chip includes an interconnection layer with a first electrically conductive contact layer, a second electrically conductive contact layer and an insulation layer, which is formed of an electrically insulating material. Further, the optoelectronic semiconductor chip includes two optoelectronic semiconductor bodies, each of which include an active region that is intended to generate radiation. The insulation layer is arranged on a top of the second electrically conductive contact layer facing the optoelectronic semiconductor bodies. The first electrically conductive contact layer is arranged on a top of the insulation layer remote from the second electrically conductive contact layer. The optoelectronic semiconductor bodies are interconnected electrically in parallel by the interconnection layer.Type: GrantFiled: May 27, 2013Date of Patent: March 7, 2017Assignee: OSRAM Opto Semiconductors GmbHInventor: Norwin von Malm
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Patent number: 9589940Abstract: A light emitting device includes a substrate, a first light emitting element, a second light emitting element, a first conductive pattern, and a second conductive pattern. The first conductive pattern is provided on the substrate and includes a first element mounting portion and a first wire connecting portion. The second conductive pattern is provided on the substrate to form a first wiring gap between the first conductive pattern and the second conductive pattern. A first recess is provided between the first element mounting portion and the first wire connecting portion and is in communication with the first wiring gap. At least a part of an outer shape of the first element mounting portion is defined by the first wiring gap and the first recess on a third side of the first element mounting portion adjacent to the second conductive pattern.Type: GrantFiled: May 29, 2015Date of Patent: March 7, 2017Assignee: NICHIA CORPORATIONInventor: Yohei Minoda
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Patent number: 9589941Abstract: In an embodiment, a semiconductor structure includes a multi-chip package system (MCPS). The MCPS includes one or more dies, a molding compound extending along sidewalls of the one or more dies, and a redistribution layer (RDL) over the one or more dies and the molding compound. The semiconductor structure also includes at least one sensor coupled to the RDL, with the RDL interposed between the at least one sensor and the one or more dies. The semiconductor structure further includes a substrate having conductive features on a first side of the substrate. The conductive features are coupled to the RDL. The substrate has a cavity extending from the first side of the substrate to a second side of the substrate opposite the first side, and the at least one sensor is disposed in the cavity.Type: GrantFiled: January 15, 2016Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 9589942Abstract: A package structure includes a first substrate, a patterned solder mask, first thermal-conductive posts, a chip and a second substrate. The first substrate includes a first patterned metal layer, a second patterned metal layer, a first surface and a second surface. The first and second patterned metal layers are disposed on the first and second surfaces. The patterned solder mask disposed on the first and second patterned metal layers exposes part of the first and second patterned metal layers. The first thermal-conductive posts are disposed on the exposed first patterned metal layer and thermally coupled thereto. The chip is disposed on the first surface. The chip electrically connected to the first patterned metal layer is thermally coupled to the first thermal-conductive posts. Two opposite ends of each first thermal-conductive post are connected to the first and second substrates, and the first thermal-conductive posts are thermally coupled to the second substrate.Type: GrantFiled: March 31, 2015Date of Patent: March 7, 2017Assignee: Subtron Technology Co., Ltd.Inventor: Chien-Ming Chen
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Patent number: 9589943Abstract: The invention relates to a method for separating regions of a semiconductor layer and for introducing an outcoupling structure into an upper side of the semiconductor layer, the outcoupling structure being provided to couple light out of the semiconductor layer. The upper side of the semiconductor layer is covered by a mask having first openings for introducing the outcoupling structure and at least a second opening, which is provided to introduce a separating trench into the semiconductor layer. With the aid of an etching method, the outcoupling structure is introduced into the upper side of the semiconductor layer in the region of the first openings and simultaneously a separating trench passing through the semiconductor layer is introduced into the semiconductor layer via the second opening, and a region of the semiconductor layer is separated.Type: GrantFiled: September 26, 2013Date of Patent: March 7, 2017Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Lorenzo Zini, Bernd Boehm
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Patent number: 9589944Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.Type: GrantFiled: January 27, 2016Date of Patent: March 7, 2017Assignee: Apple Inc.Inventors: John A. Higginson, Andreas Bibl, Hsin-Hua Hu
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Patent number: 9589945Abstract: A semiconductor package includes a package base substrate, at least one first semiconductor chip disposed on the package base substrate, and at least one stacked semiconductor chip structure disposed on the package base substrate adjacent to the at least one first semiconductor chip. The at least one stacked semiconductor chip includes a plurality of second semiconductor chips. A penetrating electrode region including a plurality of penetrating electrodes is disposed adjacent to an edge of the at least one stacked semiconductor chip structure.Type: GrantFiled: July 21, 2015Date of Patent: March 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cha-jea Jo, Yun-hyeok Im, Tae-je Cho
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Patent number: 9589946Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip; a first wiring and a second wiring which are provided above a first surface of the first semiconductor chip; a first terminal connected to one end of the first wiring and one end of the second wiring, and connected to an outside; a second terminal connected to the other end of the first wiring; and a third terminal connected to the other end of the second wiring, and connected to the second terminal.Type: GrantFiled: September 3, 2015Date of Patent: March 7, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Maya Inagaki, Masaru Koyanagi, Mikihiko Ito
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Patent number: 9589947Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.Type: GrantFiled: December 10, 2014Date of Patent: March 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jihwan Hwang, Young Kun Jee, Jung-Hwan Kim, Tae Hong Min, Kwang-chul Choi
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Patent number: 9589948Abstract: A semiconductor device has first and second NMOS transistors and an internal circuit, all formed in the same semiconductor substrate. The first NMOS transistor has a gate connected to a power supply terminal configured for connection to a power supply, a source and a back gate connected to an internal ground node, and a drain connected to a ground terminal configured for connection to the power supply. The second NMOS transistor has a gate connected to the ground terminal, a source and a back gate connected to the internal ground node, and a drain connected to the power supply terminal. The internal circuit is configured to operate with a voltage between the power supply terminal and the internal ground node. During a normal connection state in which the power supply is normally connected to the semiconductor device, current flows through the internal circuit and the second NMOS transistor.Type: GrantFiled: August 27, 2013Date of Patent: March 7, 2017Assignee: SII SEMICONDUCTOR CORPORATIONInventor: Yuichiro Kitajima
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Patent number: 9589949Abstract: An apparatus having a plurality of power pads of an integrated circuit, a plurality of transistors, and one or more diodes is disclosed. Each transistors may have a drain that forms a junction with a conductive layer of the integrated circuit. The diodes may be coupled between two of the power pads. A first portion less than all of an electro-static discharge that passes through a first of the two power pads and the conductive layer may be transferred through a first of the drains in a first of the transistors. A second portion less than all of the electro-static discharge may be transferred sequentially through (a) at least one of the diodes and (b) a second of the drains in a second of the transistors.Type: GrantFiled: October 16, 2014Date of Patent: March 7, 2017Assignee: MACOM Technology Solutions Holdings, Inc.Inventors: James T. Harvey, Simon J. Mahon, Anna Dadello
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Patent number: 9589950Abstract: A display apparatus includes a timing controller configured to output a gate control signal through gate control lines, a gate driver configured to output gate signals in response to the gate control signal provided from the gate control lines, pixels configured to receive data voltages in response to the gate signals, and first and second static electricity prevention parts connected to the gate control lines in parallel configured to discharge a static electricity. Each of the first and second static electricity prevention parts is configured to form current paths, which are smaller in number than a number of the gate control lines, to discharge the static electricity and the static electricity configured to be discharged by the first static electricity prevention part has a polarity different from a polarity of the static electricity configured to be discharged by the second static electricity prevention part.Type: GrantFiled: April 10, 2015Date of Patent: March 7, 2017Assignee: Samsung Display Co., Ltd.Inventors: Kyunho Kim, Sung-In Kang, Woojin Lee
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Patent number: 9589951Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a substrate composed of silicon, a semiconductor layer composed of p-type nitride semiconductor provided on the substrate, and a transistor including a channel layer provided on the semiconductor layer. The semiconductor device further includes an n-type source region provided in the channel layer, and an n-type drain region provided in the channel layer separately from the source region in a plan view. Each of the source region and the drain region is in contact with the semiconductor layer.Type: GrantFiled: August 17, 2015Date of Patent: March 7, 2017Assignee: Renesas Electronics CorporationInventors: Toshiharu Nagumo, Takashi Hase, Kiyoshi Takeuchi, Ippei Kume
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Patent number: 9589952Abstract: A reverse conducting IGBT is provided with a trench gate member that is provided in an IGBT region and has a lattice-pattern layout, and a trench member that is provided in a diode region and has a stripe-pattern layout. The diode region of the semiconductor substrate includes an anode region of a first conductive type, a drift region of a second conductive type and a barrier region of the second conductive type. The barrier region is electrically connected to a top surface electrode via a pillar member that extends from a top surface of the semiconductor substrate.Type: GrantFiled: April 11, 2016Date of Patent: March 7, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Masaru Senoo
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Patent number: 9589953Abstract: A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-connected distributed diode, where the base region is connected neither to the collector electrode nor to the emitter electrode. The bipolar transistor has unusually high emitter-to-base and emitter-to-collector reverse breakdown voltages. In the case of a PNP-type RBJT, an N base region extends into a P? epitaxial layer, and a plurality of P++ collector regions extend into the base region. Each collector region is annular, and rings a corresponding diode cathode region. Parts of the epitaxial layer serve as the emitter, and other parts serve as the diode anode. Insulation features separate metal of the collector electrode from the base region, and from P? type silicon of the epitaxial layer, so that the diode cathode is separated from the base region. This separation prevents base current leakage and reduces power dissipation during steady state on operation.Type: GrantFiled: March 31, 2015Date of Patent: March 7, 2017Assignee: IXYS CorporationInventor: Kyoung Wook Seok
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Patent number: 9589954Abstract: Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film.Type: GrantFiled: August 5, 2015Date of Patent: March 7, 2017Assignee: Renesas Electronics CorporationInventors: Akira Mitsuiki, Tomoo Nakayama, Shigeaki Shimizu, Hiroyuki Okuaki
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Patent number: 9589955Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.Type: GrantFiled: October 1, 2015Date of Patent: March 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hoon Baek, Sun-Young Park, Sang-Kyu Oh, Ha-Young Kim, Jung-Ho Do, Moo-Gyu Bae, Seung-Young Lee
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Patent number: 9589956Abstract: A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second fin, the first fin arranged a first distance from the second fin, the first fin and the second fin extending from a first source/drain region through a channel region and into a second source/drain region on the substrate. The method further includes forming a third fin on the substrate, the third fin arranged in parallel with the first fin and between the first fin and the second fin, the third fin arranged a second distance from the first fin, the second distance is less than the first distance, the third fin having two distal ends arranged in the first source/drain region. A gate stack is formed over the first fin and the second fin.Type: GrantFiled: June 3, 2016Date of Patent: March 7, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce B. Doris, Terence B. Hook
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Patent number: 9589957Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.Type: GrantFiled: March 3, 2016Date of Patent: March 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Ju-Youn Kim
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Patent number: 9589958Abstract: A method is disclosed which cuts hard mask fins thinner than the target fin critical dimension and then enlarges the dimension of the fin hard mask critical dimension to meet the target fin critical dimension.Type: GrantFiled: January 22, 2016Date of Patent: March 7, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sivananda K. Kanakasabapathy, Fee Li Lie, Eric Miller, Stuart A. Sieg
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Patent number: 9589959Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.Type: GrantFiled: September 26, 2014Date of Patent: March 7, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mahalingam Nandakumar, Sunitha Venkataraman, David L. Catlett, Jr.
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Patent number: 9589960Abstract: A method for forming a semiconductor structure includes forming a trench in a semiconductor substrate; forming a first dielectric layer over a bottom surface and sidewalls of the trench; forming a second dielectric layer over the first dielectric layer; forming a sacrificial layer that fills the trench, over the second dielectric layer; etching the sacrificial layer and the second dielectric layer, and forming a sacrificial filler and a dielectric liner that are positioned in the trench; removing the sacrificial filler; forming a conductive layer that fills the trench, over the dielectric liner and the first dielectric layer; and etching the conductive layer to be buried in the trench.Type: GrantFiled: June 30, 2016Date of Patent: March 7, 2017Assignee: SK Hynix Inc.Inventor: Kyung-Kyu Min
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Patent number: 9589961Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.Type: GrantFiled: April 3, 2015Date of Patent: March 7, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
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Patent number: 9589962Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.Type: GrantFiled: June 17, 2014Date of Patent: March 7, 2017Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Wolfgang Mueller, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak
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Patent number: 9589963Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.Type: GrantFiled: December 8, 2014Date of Patent: March 7, 2017Assignee: Zeno Semiconductor, Inc.Inventor: Yuniarto Widjaja
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Patent number: 9589964Abstract: A method of fabricating a semiconductor device with conductive patterns comprises sequentially forming an etch-target layer and a middle mold layer on a substrate, forming a first upper mold pattern and a second upper mold pattern on the middle mold layer to have top surfaces at different levels, etching the middle mold layer using the first and second upper mold patterns as an etch mask to form first and second middle mold patterns, respectively, forming a third middle mold pattern between the first and second middle mold patterns, and etching the etch-target layer using the first to third middle mold patterns as an etch mask to form conductive patterns.Type: GrantFiled: June 24, 2015Date of Patent: March 7, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Seokhyun Lim, Hyun-Chul Yoon, Younghan Kim, Jin Il Oh, Soonwon Hwang
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Patent number: 9589965Abstract: Methods of forming polysilicon-filled deep trenches for an eDRAM are provided. The method may include forming a plurality of polysilicon-filled deep trenches in a substrate. An epitaxy-retarding dopant is introduced to an upper portion of the trenches. A plurality of fins are then formed over the substrate, with each polysilicon-filled deep trench including a corresponding fin extending thereover. A silicon layer is epitaxially grown over at least the polysilicon-filled deep trench. The dopant in the polysilicon-filled deep trenches acts to control the epitaxial growth of the silicon layer, diminishing or preventing shorts to adjacent fins and/or deep trenches at advanced technology nodes.Type: GrantFiled: January 22, 2016Date of Patent: March 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Melissa A. Smith, Sunit S. Mahajan, Herbert L. Ho
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Patent number: 9589966Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells comprises: a gate structure on the substrate; a first interlayer dielectric (ILD) layer around the gate structure; a first contact plug in the first ILD layer; a second ILD layer on the first ILD layer; and a second contact plug in the second ILD layer and electrically connected to the first contact plug.Type: GrantFiled: May 28, 2015Date of Patent: March 7, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Chao-Hung Lin, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
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Patent number: 9589967Abstract: The embodiments described herein provide an antifuse that includes a substrate material and an isolation trench formed in the substrate material, where the isolation trench has a first side and a second side opposite the first side. An electrode is positioned above the substrate material and proximate to the first side of the isolation trench. An insulating layer is disposed between the electrode and the substrate material. So configured, a voltage or current applied between the electrode and the substrate material causes a rupture in the insulating layer and creates a current path through the insulating layer and under the isolation trench to the substrate material proximate the second side of the isolation trench.Type: GrantFiled: January 21, 2014Date of Patent: March 7, 2017Assignee: NXP USA, INC.Inventors: Won Gi Min, Jiang-Kai Zuo
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Patent number: 9589968Abstract: An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.Type: GrantFiled: November 25, 2015Date of Patent: March 7, 2017Assignee: STMicroelectronics SAInventors: Stéphane Denorme, Philippe Candelier
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Patent number: 9589969Abstract: Semiconductor devices and manufacturing methods of the same are disclosed. The semiconductor device includes a die, a conductive structure, a bonding pad and a passivation layer. The conductive structure is over and electrically connected to the die. The bonding pad is over and electrically connected to the conductive structure. The passivation layer is over the bonding pad, wherein the passivation layer includes a nitride-based layer with a refractive index of about 2.16 to 2.18.Type: GrantFiled: January 15, 2016Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Wei Chang, Austin Hsu, Kung-Wei Lee, Chui-Ya Peng
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Patent number: 9589970Abstract: An antifuse one-time programmable (OTP) memory cell includes a semiconductor substrate, an isolation region, and a fin structure protruding from a top surface of the isolation region. The fin structure has an end portion with a sidewall surface above the top surface. A select gate transistor is disposed on the fin structure. The select gate transistor has a select gate traversing the fin structure, a select gate dielectric layer, a drain region, and a source region. A vertical program gate transistor is serially connected to the select gate transistor through the source region. The vertical program gate transistor has a program gate directly disposed on the isolation region and covering the sidewall surface of the end portion, and a program gate dielectric layer between the program gate and the sidewall surface.Type: GrantFiled: August 2, 2016Date of Patent: March 7, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yuan-Heng Tseng, Chih-Shan Wu