Patents Issued in March 7, 2017
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Patent number: 9589871Abstract: The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.Type: GrantFiled: April 13, 2015Date of Patent: March 7, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tang-Yuan Chen, Chin-Li Kao, Kuo-Hua Chen, Ming-Hung Chen, Dao-Long Chen
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Patent number: 9589872Abstract: An integrated dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a driver integrated circuit (IC) paddle configured to support a driver IC for controlling each of the control FETs and each of the sync FETs. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.Type: GrantFiled: February 5, 2013Date of Patent: March 7, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Eung San Cho, Dan Clavette
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Patent number: 9589873Abstract: A leadless chip carrier comprises a thermal pad for attaching to a printed circuit board (PCB) and an integrated circuit electrically connected to a plurality of electrical lead frame pads for connection to a plurality of corresponding pads on the PCB. The leadless chip carrier further comprises a non-collapsible conductive shim bonded to a first surface of the thermal pad and each of the plurality of electrical lead frame pads is attached to a volume of solder. The conductive shim provides a stand-off between the thermal pad and the PCB and improves the integrity of a joint between the thermal pad and the PCB.Type: GrantFiled: March 20, 2015Date of Patent: March 7, 2017Assignee: MICROSS COMPONENTS LIMITEDInventor: Peter Julian Tollafield
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Patent number: 9589874Abstract: An assembly is made of an integrated circuit chip and a plate. At least one channel is arranged between the chip and the plate. The channel is delimited by metal sidewalls at least partially extending from one surface of the chip to an opposite surface of the plate. The assembly is encapsulated in a body that includes an opening extending to reach the channel. The plate may be one of an interposer, an integrated circuit chip, a support of surface-mount type, or a metal plate.Type: GrantFiled: September 17, 2015Date of Patent: March 7, 2017Assignees: STMicroelectronics (Crolles 2) SAS, SOCPRA Sciences et Génie S.E.C.Inventors: Louis-Michel Collin, Luc Guy Frechette, Sandrine Lhostis
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Patent number: 9589875Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: September 9, 2015Date of Patent: March 7, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
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Patent number: 9589876Abstract: A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps.Type: GrantFiled: August 27, 2013Date of Patent: March 7, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Zigmund R. Camacho, Lionel Chien Hui Tay, Henry D. Bathan, Dioscoro A. Merilo, Jeffrey D. Punzalan
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Patent number: 9589877Abstract: A semiconductor device includes an expanded semiconductor chip having a first semiconductor chip and an expanded portion extending outward from a side surface of the first semiconductor chip, a second semiconductor chip provided so as to be connected to the expanded semiconductor chip via a plurality of first bumps, and a base provided so as to be connected to the expanded semiconductor chip via a plurality of second bumps. The first bumps are provided between the first semiconductor chip and the second semiconductor chip. The second bumps are provided between the expanded portion and the base.Type: GrantFiled: January 8, 2014Date of Patent: March 7, 2017Assignee: Panasonic CorporationInventors: Shigefumi Dohi, Kiyomi Hagihara
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Patent number: 9589878Abstract: A semiconductor package includes: an upper package to which an element is mounted, and which includes a metal pad portion; a metal post connected to the metal pad portion; and a lower package to which an element is mounted, and which is connected to the metal post.Type: GrantFiled: November 11, 2015Date of Patent: March 7, 2017Assignee: LG INNOTEK CO., LTD.Inventors: Sung Wuk Ryu, Dong Sun Kim, Hyun Seok Seo, Ji Haeng Lee
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Patent number: 9589879Abstract: A through via (144) contains a conductor (244, 276) passing through a substrate (140) for connection to an integrated circuit element. The through via consists of two segments (144.1, 144.2) formed from respective different sides (140.1, 140.2) of the substrate and meeting inside the substrate. Each segment is shorter than the entire via, so via formation is facilitated. The second segment is etched after deposition of an etch stop layer (214) into the first segment. Due to the etch stop layer, the first segment's depth does not have to be rigidly controlled. The conductor is formed by separate depositions of conductive material into the via from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the via depth, so the deposition is facilitated. Other embodiments are also provided.Type: GrantFiled: April 27, 2015Date of Patent: March 7, 2017Assignee: Invensas CorporationInventors: Valentin Kosenko, Sergey Savastiouk
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Patent number: 9589880Abstract: A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.Type: GrantFiled: October 9, 2013Date of Patent: March 7, 2017Assignee: INFINEON TECHNOLOGIES AGInventors: Srinivasa Reddy Yeduru, Karl Heinz Gasser, Stefan Woehlert, Karl Mayer, Francisco Javier Santos Rodriguez
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Patent number: 9589881Abstract: A display device includes a display panel and a chip-on-film (COF) bonded to the display panel. The chip-on-film includes a film on which a driving chip is mounted, a plurality of film lines on the film, and at least one dummy pattern on the film between an adjacent pair of films in the plurality of film lines.Type: GrantFiled: September 10, 2015Date of Patent: March 7, 2017Assignee: LG Display Co., Ltd.Inventor: Hyungseok Seo
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Patent number: 9589882Abstract: The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.Type: GrantFiled: December 17, 2015Date of Patent: March 7, 2017Assignee: Renesas Electronics CorporationInventor: Hiromitsu Takeda
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Patent number: 9589883Abstract: A double-sided chip on film (COF) packaging structure and a manufacturing method thereof are disclosed. The double-sided COF structure includes a metal layer, a first insulating layer, a second insulating layer, a chip, and an encapsulant. The first insulating layer and second insulating layer are disposed on a first surface and a second surface of metal layer respectively. The first surface and second surface are opposite. The first insulating layer includes a first part and a second part separated from each other. An accommodating space is existed between the first part and the second part and a part of the first surface is exposed. The chip is accommodated in the accommodating space and disposed on the exposed part of the first surface. The encapsulant fills the spaces between the chip and the first part and between the chip and the second part to form the double-sided COF packaging structure.Type: GrantFiled: November 4, 2015Date of Patent: March 7, 2017Assignee: Raydium Semiconductor CorporationInventor: Ching-Yung Chen
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Patent number: 9589884Abstract: An integrated circuit device may include the following elements: a first semiconductor substrate; a first transistor set positioned in the first semiconductor substrate; a first dielectric layer covering a gate electrode of the first transistor set; a first interconnect member positioned in the first dielectric layer and electrically connected to the first transistor set; a second semiconductor substrate; a second transistor set positioned in the second semiconductor substrate and structurally different from the first transistor set; a second dielectric layer connected to the first dielectric layer, positioned between the first dielectric layer and the second semiconductor substrate, and covering a gate electrode of the second transistor set; and a second interconnect member positioned in the second dielectric layer, electrically connected to a terminal of the second transistor set, and electrically connected to the first interconnect member.Type: GrantFiled: December 16, 2014Date of Patent: March 7, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Herb He Huang, Clifford Ian Drowley
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Patent number: 9589885Abstract: An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.Type: GrantFiled: August 26, 2015Date of Patent: March 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Jen Liao, Jung-Hsuan Chen, Chien Chi Tien, Ching-Wei Wu, Jui-Che Tsai, Hong-Chen Cheng, Chung-Hsing Wang
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Patent number: 9589886Abstract: A semiconductor device is provided having a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.Type: GrantFiled: July 6, 2015Date of Patent: March 7, 2017Assignee: Seiko Epson CorporationInventor: Haruki Ito
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Patent number: 9589887Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.Type: GrantFiled: September 23, 2015Date of Patent: March 7, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinpei Watanabe, Shinichi Uchida, Tadashi Maeda, Kazuo Henmi
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Patent number: 9589888Abstract: A storage device is provided including a flash memory, and a controller programming first bit data and second bit data into the flash memory and not backing up the first bit data when programming the first bit data and the second bit data in the same transaction and backing up the first bit data when programming the first bit data and the second bit data in different transactions, wherein the first bit data is less significant bit data than the second bit data, and each of the transactions is determined using a sync signal transmitted from a host.Type: GrantFiled: December 3, 2013Date of Patent: March 7, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Suk Choi, Kyu-Hyung Kim, Do-Sam Kim, Hyun-Sik Yun
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Patent number: 9589889Abstract: Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device's effective width improves targeting of both on-resistance and current-carrying capability.Type: GrantFiled: August 3, 2015Date of Patent: March 7, 2017Assignee: D3 SEMICONDUCTOR LLCInventor: Thomas E. Harrington, III
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Patent number: 9589890Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches.Type: GrantFiled: July 20, 2015Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Chieh Yao, Carlos H. Diaz, Cheng-Hsiung Tsai, Chung-Ju Lee, Chien-Hua Huang, Hsi-Wen Tien, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu
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Patent number: 9589891Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes line having a width greater than the PPI line.Type: GrantFiled: November 19, 2015Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Jie Chen, Ying-Ju Chen
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Patent number: 9589892Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate, a dielectric layer over the contact layer, a silicide layer over the exposed portion of the contact layer, a barrier layer along sidewalls of the opening, an alloy layer over the barrier layer, a glue layer over the alloy layer, and a conductive plug over the glue layer, wherein the dielectric layer has an opening, and the opening exposes a portion of the contact layer.Type: GrantFiled: May 20, 2016Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, Mei-Hui Fu, Wei-Jung Lin, You-Hua Chou, Chia-Lin Hsu, Hon-Lin Huang, Shih-Chi Lin
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Patent number: 9589893Abstract: A semiconductor device includes a semiconductor chip, which includes a substrate, a multilayer interconnect layer formed over the substrate, a first cell column disposed along an edge of the substrate in a plan view, the first cell column having a first I/O cell and a first power supply cell, second cell column disposed along the first cell column in plan view, the second cell column having a second I/O cell, a first pad supplying a first supply voltage to the first power supply cell, a first voltage supply wire disposed over the first cell column, a second voltage supply wire disposed over the second cell column, and a first connection wire crossing the first voltage supply wire and the second voltage supply wire.Type: GrantFiled: June 5, 2015Date of Patent: March 7, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masafumi Tomoda, Masayuki Tsukuda
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Patent number: 9589894Abstract: A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.Type: GrantFiled: March 31, 2014Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Daniel Edelstein, Takeshi Nogami, Christopher Parks, Tsong Lin Leo Tai
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Patent number: 9589895Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of creating a non-permeable edge seal around a whole wafer. The edge seal may be located between an inner region of a wafer comprising product chips and an outer edge of the wafer. The edge seal may comprise a fillet region adjacent the inner region, and a dielectric extension adjacent the fillet region. The dielectric extension region may be impermeable to moisture and composed of a dielectric layer on the wafer and a capping layer on the dielectric layer. The fillet region may comprise a lower metal fillet directly on the wafer, a dielectric layer on the lower metal fillet, an upper metal fillet on the dielectric layer, and a capping layer on the upper metal fillet. The fillet region may be adjacent to and in contact with a permeable layer formed on the product region.Type: GrantFiled: April 15, 2015Date of Patent: March 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Gregory Bazan, Thomas F. Houghton
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Patent number: 9589896Abstract: An electronic circuit structure comprising a substrate, a dielectric layer on top of the substrate and comprising a cavity having side-walls, a manganese or manganese nitride layer covering the side-walls, and a self-assembled monolayer, comprising an organic compound of formula Z-L-A, covering the manganese or manganese nitride layer, wherein Z is selected from the list consisting of a primary amino group, a carboxylic acid group, a thiol group, a selenol group and a heterocyclic group having an unsubstituted tertiary amine in the cycle, wherein L is an organic linker comprising from 1 to 12 carbon atoms and from 0 to 3 heteroatoms, and wherein A is a group attaching the linker to the manganese or manganese nitride layer.Type: GrantFiled: March 10, 2016Date of Patent: March 7, 2017Assignee: IMEC VZWInventor: Silvia Armini
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Patent number: 9589897Abstract: The present disclosure involves a method of fabricating a semiconductor device in a semiconductor technology node that is 5-nanometer or smaller. An opening is formed that extends through a plurality of layers over a substrate. A barrier layer is formed on surfaces of the opening. A liner layer is formed over the barrier layer in the opening. The barrier layer and the liner layer have different material compositions. The opening is filled with a non-copper metal material. The non-copper material is formed over the liner layer. In some embodiments, the non-copper metal material includes cobalt.Type: GrantFiled: August 18, 2015Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Chang Wu, Li-Lin Su
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Patent number: 9589898Abstract: A semiconductor device in which an air-gap located at a side of a bit line stack is extended to an upper part of the bit line stack is disclosed. An embodiment includes: a bit line stack; a plurality of storage node contacts located at both sides of the bit line stack; and an air-gap located between the bit line stack and the storage node contacts, and extended above the bit line stack.Type: GrantFiled: October 2, 2015Date of Patent: March 7, 2017Assignee: SK Hynix Inc.Inventor: Jae Houb Chun
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Patent number: 9589899Abstract: In a semiconductor device, a first gate structure having a first end portion is formed on a substrate. A second gate structure is formed on the substrate, and has a second end portion opposite to the first end portion of the first gate structure in a diagonal direction. A cross-coupling pattern is formed between the first and second gate structure, and electrically connects the first and second gate structures to each other. A first contact plug directly contacts an upper portion of the first end portion of the first gate structure and a first upper sidewall of the cross-coupling pattern. A second contact plug directly contacts an upper portion of the second end portion of the second gate structure and a second upper sidewall of the cross-coupling pattern. In the semiconductor device, a parasitic capacitance due to the cross-coupling structure may decrease.Type: GrantFiled: July 17, 2015Date of Patent: March 7, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hwi-Chan Jun, Dae-Hee Weon, Heon-Jong Shin, Yu-Sun Lee
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Patent number: 9589900Abstract: A package includes a device die, a molding material molding the device die therein, and a plurality of redistribution lines overlying the device die and the molding material. A laser mark pad is coplanar with one of the plurality of redistribution lines, wherein the laser mark pad and the one of the plurality of redistribution layers are formed of the same conductive material. A polymer layer is over the laser mark pad and the plurality of redistribution lines. A tape is attached over the polymer layer. A laser mark penetrates through the tape and the polymer layer. The laser mark extends to a top surface of the laser mark pad.Type: GrantFiled: September 15, 2014Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: An-Jhih Su, Hsien-Wei Chen
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Patent number: 9589901Abstract: A wafer can be provided to include a single crystalline semiconductor material with a predetermined crystal orientation. The wafer can include a laser mark at a determined position on a front surface or on a back surface of the wafer, where the determined position is configured to indicate the predetermined crystal orientation of the single crystalline semiconductor material.Type: GrantFiled: October 21, 2014Date of Patent: March 7, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Hyoung Koo, Samjong Choi, Dongjun Lee, Yongsun Ko
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Patent number: 9589902Abstract: A semiconductor wafer has formed thereon various types of semiconductor chips and enables different types of semiconductor chips having the same chip size to be easily distinguished. An excluded region is formed on an outer periphery of the semiconductor wafer, and a region inside the excluded region is divided into different types of regions by boundaries. Mark chips are respectively arranged in the vicinity of both ends of the boundaries.Type: GrantFiled: March 30, 2015Date of Patent: March 7, 2017Assignee: SII Semiconductor CorporationInventors: Yasunobu Matsumoto, Masaki Suzuki, Makoto Asou, Hiroshi Morita
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Patent number: 9589903Abstract: A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die, and a bottom dielectric layer over the device die and the molding material. A plurality of redistribution lines (RDLs) extends into the bottom dielectric layer and electrically coupling to the device die. A top polymer layer is over the bottom dielectric layer, with a trench ring penetrating through the top polymer layer. The trench ring is adjacent to edges of the package. The package further includes Under-Bump Metallurgies (UBMs) extending into the top polymer layer.Type: GrantFiled: May 15, 2015Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jie Chen, Hsien-Wei Chen
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Patent number: 9589904Abstract: A device includes a semiconductor chip and a bypass layer electrically coupled to a contact region of the semiconductor chip. The bypass layer is configured to change from behaving as an insulator to behaving as a conductor in response to a condition of the semiconductor chip.Type: GrantFiled: February 14, 2013Date of Patent: March 7, 2017Assignee: Infineon Technologies Austria AGInventor: Ralf Otremba
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Patent number: 9589905Abstract: A semiconductor package includes a substrate, a chip disposed over a top surface of the substrate, an electromagnetic interference (EMI) shielding layer disposed over the substrate such that the EMI shielding layer surrounds the chip, a ground pad disposed in the substrate to contact a bottom surface of the substrate, and a test pad disposed in the substrate to contact the bottom surface of the substrate and spaced apart from the ground pad. A method of testing the semiconductor package is performed using a loop circuit to which a current is applied, the loop circuit being formed by electrically coupling the ground pad, the EMI shielding layer, and the test pad.Type: GrantFiled: April 4, 2014Date of Patent: March 7, 2017Assignee: SK HYNIX INC.Inventors: Hyung Ju Choi, Jong Hyun Kim
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Patent number: 9589906Abstract: The present disclosure relates to a semiconductor device package and a manufacturing method thereof. The semiconductor package comprises a die pad, a row of leads, a component, a package body, and a conformal shield. The die pad has a top surface. The row of leads comprises a first lead and a second lead, and the row of leads is arranged along a side of the die pad. The first lead has a first lateral surface, and the second lead has a second lateral surface. The component is disposed on the top surface of the die pad. The package body encapsulates the component, the die pad, the first lead, and the second lead, exposes the first lateral surface of the first lead, and covers the second lateral surface of the second lead. The conformal shield covers the package body and connects to the first lateral surface of the first lead.Type: GrantFiled: February 27, 2015Date of Patent: March 7, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Daesung Lee, Ingyu Han, Chulhyun Park
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Patent number: 9589907Abstract: Provided is a resist film forming device which uses an electrostatic spray device which is capable of forming a thin film with a uniform thickness on a workpiece. A resist film forming device (100), which forms a resist film (108) on a substrate by electrostatic spraying, comprises: a nozzle (102) which, upon application of a prescribed voltage, sprays liquid particles which form the raw material for a resist film (108) toward a substrate (105) having stepped portions (105a); a driving means (111) for causing relative movement of the substrate (105) or the nozzle (102); and a control means (110) for controlling such that the resist film (108) is formed on the substrate (105) having the stepped portions (105a) by the liquid particles.Type: GrantFiled: November 11, 2013Date of Patent: March 7, 2017Assignee: Apic Yamada CorporationInventors: Kazuhiko Kobayashi, Keisuke Suda
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Patent number: 9589908Abstract: A method and apparatus are provided for manufacturing a packaged electronic device (200) which includes a carrier substrate (120) in which conductive interconnect paths (122) extend between first and second opposed surfaces, an integrated circuit die (125) affixed to the first surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, and an array of conductors (110), such as BGA, LGA, PGA, C4 bump or flip chip conductors, affixed to the second surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, where the array comprising a signal feed ball (112) and an array of shielding ground balls (111) surrounding the signal feed ball.Type: GrantFiled: September 29, 2015Date of Patent: March 7, 2017Assignee: NXP USA, INC.Inventor: Walter Parmon
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Patent number: 9589909Abstract: Radio frequency/electromagnetic interference (RF/EMI) shielding within redistribution layers of a fan-out wafer level package is provided. By using RDL metal layers to provide the shielding, additional process steps are avoided (e.g., incorporating a shielding lid or applying conformal paint on the package back side). Embodiments use metal filled trench vias in the RDL dielectric layers to provide metal “walls” around the RF sensitive signal lines through the dielectric layer regions of the RDL. These walls are coupled to ground, which isolates the signal lines from interference or noise generated outside the walls.Type: GrantFiled: October 23, 2015Date of Patent: March 7, 2017Assignee: NXP USA, INC.Inventors: Weng F. Yap, Eduard J. Pabst
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Patent number: 9589910Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die.Type: GrantFiled: March 18, 2013Date of Patent: March 7, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Reza A. Pagaila, Dioscoro A. Merilo
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Patent number: 9589911Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure with a metal crack stop and methods of forming the same. An IC structure according to embodiments of the present disclosure can include an insulator positioned over a substrate; a barrier film positioned over the insulator; an interlayer dielectric positioned over the barrier film; and a metal crack stop positioned over the substrate and laterally adjacent to each of the insulator, the barrier film, and the interlayer dielectric, wherein the metal crack stop includes a sidewall having a first recess therein, and wherein a horizontal interface between the barrier film and the interlayer dielectric intersects the sidewall of the metal crack stop.Type: GrantFiled: August 27, 2015Date of Patent: March 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Jim S. Liang, Atsushi Ogino, Roger A. Quon, Stephen E. Greco
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Patent number: 9589912Abstract: A first aspect of the disclosure provides for an integrated circuit structure. The integrated circuit structure may comprise a first metal structure in a first dielectric layer on a substrate in a crack stop area; and a first crack stop structure in a second dielectric layer, the first crack stop structure being over the first metal structure and including: a first metal fill contacting the first metal structure; and an air seam substantially separating the first metal fill and the second dielectric layer.Type: GrantFiled: August 27, 2015Date of Patent: March 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Jim S. Liang, Atsushi Ogino, Stephen E. Greco, Roger A. Quon
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Patent number: 9589913Abstract: An interposer and a method for stacking dies utilizing such an interposer in an integrated circuit are disclosed. The interposer includes a substrate and a plurality of vias defined in the substrate. At least one of the plurality of vias of the interposer is positioned to establish a connection with at least one of the plurality of vias of a first die. At least one additional die is positioned to establish a connection with the first die utilizing the connection established between the interposer and the first die through at least one of the vias.Type: GrantFiled: March 29, 2013Date of Patent: March 7, 2017Assignee: Rockwell Collins, Inc.Inventors: Sarah M. Shepard, Bret W. Simon, Alan P. Boone
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Patent number: 9589914Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.Type: GrantFiled: November 28, 2014Date of Patent: March 7, 2017Assignee: INFINEON TECHNOLOGIES AGInventors: Herbert Gietler, Robert Pressl
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Patent number: 9589915Abstract: A semiconductor device includes a substrate defined with a seal ring region and a circuit region, the substrate includes a seal ring structure and an integrated circuit structure, the seal ring structure is disposed in the seal ring region and includes a plurality of stacked conductive layers interconnected by a plurality of via layers, the integrated circuit structure is disposed in the circuit region and includes an active or a passive device; a metal pad disposed over the seal ring region and contacted with the seal ring structure; a passivation layer disposed over the substrate and covering the metal pad; a polymeric layer disposed over the passivation layer and the circuit region; and a molding disposed over the passivation layer and the polymeric layer, wherein the seal ring structure is covered by the molding.Type: GrantFiled: July 17, 2014Date of Patent: March 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Wen-Hsin Chan, Chen-Chih Hsieh
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Patent number: 9589916Abstract: A packaged RF power transistor includes an RF input lead, a DC gate bias lead, an RF power transistor comprising gate, source and drain terminals, and an input match network. The input match network includes a primary inductor electrically connected to the RF input lead, a secondary inductor electrically connected to the gate terminal and to the DC gate bias lead, and a tuning capacitor electrically connected to the RF input lead and physically disconnected from the gate terminal. The input match network is configured to block DC voltages between the RF input lead and the gate terminal and to propagate AC voltages in a defined frequency range from the RF input lead to the gate terminal. The tuning capacitor is configured to adjust a capacitance of the input match network based upon a variation in DC voltage applied to the RF input lead.Type: GrantFiled: February 10, 2015Date of Patent: March 7, 2017Assignee: Infineon Technologies AGInventors: Marvin Marbell, E J Hashimoto, Bill Agar
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Microwave monolithic integrated circuit (MMIC) having integrated high power thermal dissipating load
Patent number: 9589917Abstract: A Microwave Monolithic Integrated Circuit (MMIC) having an integrated high power load. The MMIC includes a microwave transmission line and a resistive load coupled to a terminating end of the microwave transmission line. The resistive load comprises a hollow resistive material disposed on sidewalls of a via passing through a substrate, the resistive material having an upper portion electrically connected to a terminating end of a strip conductor of the microwave transmission line strip conductor and a lower portion electrically connected to the ground plane.Type: GrantFiled: March 21, 2016Date of Patent: March 7, 2017Assignee: Raytheon CompanyInventors: Istvan Rodriguez, Christopher M. Laighton, Alan J. Bielunis -
Patent number: 9589918Abstract: A memory device structure includes circuitry formed over a substrate and at least one insulating portion formed over said circuitry, each of which includes a plurality of openings. The memory device also includes a plurality of electrical connections formed in respective openings of the plurality of openings of the at least one insulating portion, at least one bond pad formed within at least one of the at least one insulating portion, and a cap formed over the at least one bond pad.Type: GrantFiled: October 7, 2015Date of Patent: March 7, 2017Assignee: OVONYX MEMORY TECHNOLOGY, LLCInventors: John Moore, Joseph F. Brooks
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Patent number: 9589919Abstract: The present description relates to the field of fabricating microelectronic devices, wherein a microelectronic device may have a hexagonal confirmation for signal nodes and ground nodes which utilizes the cross-talk reduction by cancellation property of geometrically symmetry and orthogonality to reduce signal node to ground node ratio for increasing signaling density.Type: GrantFiled: December 22, 2011Date of Patent: March 7, 2017Assignee: Intel CorporationInventors: Raul Enriquez Shibayama, Jimmy A. Johansson, Kai Xiao
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Patent number: 9589920Abstract: An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges.Type: GrantFiled: August 26, 2015Date of Patent: March 7, 2017Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.Inventors: Dror Hurwitz, Alex Huang