Patents Issued in March 7, 2017
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Patent number: 9589971Abstract: An anti-fuse memory cell is provided. The anti-fuse memory cell includes a programmable transistor and a selection transistor. The programmable transistor includes a gate structure, a first doped region and a lightly doped region. The first doped region is divided into a first portion doped region, a second portion doped region and a third portion doped region. The first and second portion doped regions are respectively a source and a drain of the programmable transistor, and the third portion doped region is disposed between the first and second portion doped regions. The lightly doped region is distributed around a channel region of the programmable transistor, and adjacent to the first, second and third portion doped regions. The selection transistor includes a gate structure and a second doped region, and connected in series to the programmable transistor through the first portion doped region.Type: GrantFiled: September 12, 2016Date of Patent: March 7, 2017Assignee: Vanguard International Semiconductor CorporationInventors: Chia-Chiuan Chang, Jui-Lung Chen, Yu-Wen Chen, Hsuan-Chi Su, Ching-Hsiang Lin
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Patent number: 9589972Abstract: An ultraviolet-erasable nonvolatile semiconductor device has a protective film comprised of a silicon nitride film on which is laminated a silicon oxynitride film. The silicon nitride film has a thickness of 1000 ? or more and 2000 ? or less and the silicon oxynitride film has a thickness of about 7000 ? or more. The silicon nitride film and the silicon oxynitride film cooperate to prevent moisture from penetrating into the ultraviolet-erasable nonvolatile semiconductor device. The thickness of the silicon nitride film is set so that the time for erasing data in a nonvolatile semiconductor storage element through irradiation with ultraviolet rays is not increased.Type: GrantFiled: January 22, 2014Date of Patent: March 7, 2017Assignee: SII Semiconductor CorporationInventor: Tetsuo Someya
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Patent number: 9589973Abstract: A pillar-shaped semiconductor memory device includes a silicon pillar, and a tunnel insulating layer, a data charge storage insulating layer, a first interlayer insulating layer, and a first conductor layer, which surround an outer periphery of the silicon pillar in that order, and a second interlayer insulating layer that is in contact with an upper surface or a lower surface of the first conductor layer. A side surface of the second interlayer insulating layer facing a side surface of the first interlayer insulating layer is separated from the side surface of the first interlayer insulating layer with a distance therebetween, the distance being larger than a distance from the side surface of the first interlayer insulating layer to a side surface of the first conductor layer facing the side surface of the first interlayer insulating layer.Type: GrantFiled: July 27, 2016Date of Patent: March 7, 2017Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 9589974Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.Type: GrantFiled: January 24, 2014Date of Patent: March 7, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Jun Iijima, Yoshiaki Himeno, Takamasa Usui
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Patent number: 9589976Abstract: The present disclosure relates to an integrated circuit (IC), including, a flash memory device region, including a pair of split-gate flash memory cells arranged over a semiconductor substrate. The pair of split gate flash memory cells respectively have a control gate (CG) including a polysilicon gate and an overlying silicide layer. A periphery circuit including, one or more high-k metal gate (HKMG) transistors are arranged over the semiconductor substrate at a position laterally offset from the flash memory device region. The one or more HKMG transistors have a metal gate electrode with an upper surface that is lower than an upper surface of the silicide layer. A method of manufacturing the IC is also provided.Type: GrantFiled: April 16, 2015Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yuan-Tai Tseng, Chang-Ming Wu, Shih-Chang Liu
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Patent number: 9589977Abstract: The invention provides a non-volatile memory and a fabricating method thereof. The non-volatile memory includes a substrate, an embedded-type charge storage transistor, and a selection transistor. The substrate has an opening. The embedded-type charge storage transistor is disposed in the substrate. The embedded-type charge storage transistor includes a charge storage structure and a conductive layer. The charge storage structure is disposed on the substrate in the opening. The conductive layer is disposed on the charge storage structure and fills the opening. The selection transistor is disposed on the substrate at one side of the embedded-type charge storage transistor, wherein the selection transistor includes a metal gate structure. The non-volatile memory has excellent charge storage capacity.Type: GrantFiled: December 9, 2015Date of Patent: March 7, 2017Assignee: United Microelectronics Corp.Inventors: Ko-Chi Chen, Shen-De Wang
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Patent number: 9589978Abstract: In an example, a memory device includes a staircase comprising a flight of stairs and a plurality of pass transistors directly under the staircase. The stairs of the flight of stairs are respectively coupled to different tiers of memory cells, and a different pass transistor of the plurality of pass transistors is coupled to each of the stairs of the flight of stairs.Type: GrantFiled: February 25, 2016Date of Patent: March 7, 2017Assignee: Micron Technology, Inc.Inventor: Aaron S. Yip
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Patent number: 9589979Abstract: A memory device is described, which includes a block of memory cells comprising a plurality of stacks of horizontal active lines such as NAND string channel lines, with a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines to provide a gate-all-around structure. A memory film is disposed between the horizontal active lines in the plurality of stacks and the vertical slices in the plurality of vertical slices. A 3D, horizontal channel, gate-all-around NAND flash memory is provided. A method for manufacturing a memory involves a buttress process. The buttress process enables horizontal channel, gate-all-around structures.Type: GrantFiled: November 19, 2014Date of Patent: March 7, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventor: Shih-Ping Hong
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Patent number: 9589980Abstract: A semiconductor device includes first semiconductor patterns with protrusions formed on the sidewalls thereof, and second semiconductor patterns respectively coupled to the first semiconductor patterns and increasing in width away from joining surfaces where the first semiconductor patterns and the second semiconductor patterns are coupled.Type: GrantFiled: April 22, 2014Date of Patent: March 7, 2017Assignee: SK Hynix Inc.Inventors: Chan Sun Hyun, Wan Soo Kim, Myung Kyu Ahn, Young Bin Ko
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Patent number: 9589981Abstract: A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.Type: GrantFiled: June 15, 2015Date of Patent: March 7, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Ryoichi Honma, Toru Miwa, Hiroaki Koketsu, Johann Alsmeier
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Patent number: 9589982Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.Type: GrantFiled: September 15, 2015Date of Patent: March 7, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
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Patent number: 9589983Abstract: An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.Type: GrantFiled: June 3, 2016Date of Patent: March 7, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Russell Carlton McMullan
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Patent number: 9589984Abstract: A pixel structure located on a periphery of a display module includes a substrate, a flexible circuit board and a plurality of LED chips. The substrate has at least one scribing tolerance reserving zone and a display unit mounting zone. The flexible circuit board is disposed on the display unit mounting zone of the substrate. The LED chips are mounted on the flexible circuit board.Type: GrantFiled: June 3, 2015Date of Patent: March 7, 2017Assignee: E Ink Holdings Inc.Inventors: Yung-Sheng Chang, Chia-Chun Yeh
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Patent number: 9589985Abstract: A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate (1) and depositing a buffer layer (2); Step 2: depositing an a-Si layer (3); Step 3: depositing and patterning a silicon oxide layer (4); Step 4: taking the silicon oxide layer (4) as a photomask and annealing the a-Si layer (3) with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region (31) and a second poly-Si region (32); Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions (31) and (32), and forming an LDD area; Step 7: depositing and patterning a gate insulating layer (5); Step 8: forming a first gate (61) and a second gate (62); Step 9: forming via holes (70); and Step 10: forming a first source/drain (81) and a second source/drain (82).Type: GrantFiled: February 9, 2015Date of Patent: March 7, 2017Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventor: Gaiping Lu
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Patent number: 9589986Abstract: The invention provides an array substrate, a method therefor and a display device. The array substrate includes: a substrate, and a thin film transistor (TFT) and a pull-down capacitor disposed on the substrate. The TFT includes: a gate, a gate insulating layer, a channel layer, a source, a drain and a passivation layer. The passivation layer is disposed with a via hole corresponding to the drain, a pixel electrode is connected to the drain through the via hole. The pull-down capacitor includes: a first conductive layer, a first spacer layer, a filling layer, a second spacer layer and a second conductive layer successively stacked on the substrate. The sum of thicknesses of the filling layer and the first spacer layer is greater than the sum of thicknesses of the drain and the channel layer, to make the second conductive layer and the pixel electrode be located at different levels.Type: GrantFiled: January 21, 2015Date of Patent: March 7, 2017Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventor: Huan Liu
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Patent number: 9589987Abstract: An array substrate includes a base substrate (10) and a gate line (11) and a data line (12) provided on the base, the gate line (11) and the data line (12) define a pixel unit, and in the pixel unit, a thin film transistor (13) is provided, the thin film transistor (13) includes a gate electrode (131), a gate insulation layer (132), an active layer (133), a source electrode (134) and a drain electrode (135). The gate insulation layer (132) includes a first gate insulation portion (1321) and a second gate insulation portion (1322), the gate electrode (131) is located between the first gate insulation portion (1321) and the second gate insulation portion (1322), and the second gate insulation portion (1322) is located between the gate electrode (131) and the active layer (133).Type: GrantFiled: April 17, 2015Date of Patent: March 7, 2017Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Qiyu Shen
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Patent number: 9589988Abstract: With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. The increase in the numbers of gate lines and signal lines makes it difficult to mount an IC chip having a driver circuit for driving the gate line and the signal line by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit driving the pixel portion are provided over the same substrate. The pixel portion and at least a part of the driver circuit are formed using thin film transistors in each of which an oxide semiconductor is used. Both the pixel portion and the driver circuit are provided over the same substrate, whereby manufacturing costs are reduced.Type: GrantFiled: October 16, 2014Date of Patent: March 7, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Atsushi Umezaki
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Patent number: 9589989Abstract: An array substrate for a liquid crystal display (LCD) device include: a substrate; a gate line formed in one direction on one surface of the substrate; a data line crossing the gate line to define a pixel area; a thin film transistor (TFT) configured at a crossing of the gate line and the data line; a pixel electrode formed at a pixel region of the substrate; an insulating film formed on the entire surface of the substrate including the pixel electrode and the TFT, including a first insulating film formed of a high temperature silicon nitride film and a second insulating film formed of a low temperature silicon nitride film, and having a contact hole having an undercut shape exposing the pixel electrode; a pixel electrode connection pattern formed within the contact hole having an undercut shape and connected with the pixel electrode and the TFT; and a plurality of common electrodes separately formed on the insulating film.Type: GrantFiled: November 12, 2014Date of Patent: March 7, 2017Assignee: LG Display Co., Ltd.Inventors: Jeong-Oh Kim, Yong-Il Kim
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Patent number: 9589990Abstract: A thin-film transistor array substrate is disclosed. The array substrate includes a support substrate, a plurality of scan lines on the support substrate, and a plurality of data lines on the support substrate, where the plurality of scan lines are insulated and intersect with the plurality of data lines. The array substrate also includes a plurality of pixel units located near intersections of the scan lines and the data lines, a first metal layer on the support substrate, and an insulating layer on the first metal layer, where the insulating layer includes a plurality of via holes, each exposing a portion of the first metal layer. The array substrate also includes a semiconductor layer on the insulating layer and electrically connected to the first metal layer, and a second metal layer on the semiconductor layer and electrically connected to the semiconductor layer.Type: GrantFiled: June 24, 2015Date of Patent: March 7, 2017Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.Inventors: Yingteng Zhai, Yong Wu
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Patent number: 9589991Abstract: A thin-film transistor (TFT), a manufacturing method thereof, display substrate and a display device are disclosed. The TFT includes: an active layer, gate insulating layer, gate electrode, interlayer dielectric layer, source electrode and a drain electrode disposed on a base substrate in sequence. The source electrode and drain electrode are respectively connected with the active layer via a through hole exposing the active layer; the gate insulating layer at least includes a silicon oxide layer and a silicon nitride layer in a two-layer structure; the interlayer dielectric layer at least includes silicon oxide layers and silicon nitride layers in a four-layer structure; the silicon oxide layers and silicon nitride layers of the gate insulating layer and the interlayer dielectric layer are alternately arranged; and the dimension of one side of the through hole away from the base substrate is greater than that of one side close to the base substrate.Type: GrantFiled: December 29, 2014Date of Patent: March 7, 2017Assignee: BOE Technology Group Co., Ltd.Inventors: Zuqiang Wang, Chien Hung Liu
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Patent number: 9589992Abstract: The present invention relates to a display panel including a static electricity preventing pattern and a display device having the same. An aspect of the present invention provides a display device or a display panel in which a dummy pattern having a pattern identical to or similar to a line of a signal area is positioned between the signal area and a non-signal area, in a pad including the signal area and the non-signal area.Type: GrantFiled: November 13, 2015Date of Patent: March 7, 2017Assignee: LG Display Co., Ltd.Inventors: SoonJae Hwang, DuHwan Oh, HwaDong Han
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Patent number: 9589993Abstract: A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire.Type: GrantFiled: December 30, 2015Date of Patent: March 7, 2017Assignee: Samsung Display Co., Ltd.Inventors: Hyeon Jun Lee, Katsumi Abe, Young-Wook Lee
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Patent number: 9589994Abstract: A display panel whose TFT substrate comprises a substrate, a gate layer, a gate dielectric layer, a semiconductor layer, a first electrode layer, a first passivation layer, a second passivation layer, a via and a second electrode layer is provided. The gate layer is disposed on the substrate. The gate dielectric layer is disposed on the gate layer. The semiconductor layer is disposed on the gate dielectric layer. The first electrode layer is disposed on the semiconductor layer. The first and second passivation layers are sequentially disposed on the first electrode layer. The via penetrates the passivation layers to expose the first electrode layer. The second electrode layer is electrically connected to the first electrode layer through the via. The first and second passivation layers have first and second taper angles respectively. The difference between the first and second taper angles is below 30°.Type: GrantFiled: January 30, 2015Date of Patent: March 7, 2017Assignee: INNOLUX CORPORATIONInventors: Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan
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Patent number: 9589995Abstract: Disclosed are a method for manufacturing a TFT substrate having storage capacitors and the TFT substrate. The method includes: (1) forming a gate terminal and a first metal electrode; (2) forming a gate insulation layer and a gate insulation layer through-hole; (3) forming an oxide semiconductor layer; (4) subjecting a portion of the oxide semiconductor layer to N-type heavy doping to form a first conductor electrode thereby constituting a first storage capacitor; (5) forming an etch stop layer and a first etch stop layer through-hole; (6) forming source/drain terminals and a second metal electrode, thereby constituting a second storage capacitor connected in parallel to the first capacitor; (7) forming a protection layer, a protection layer through-hole, and a second etch stop layer through-hole; and (8) forming a pixel electrode and a second conductor electrode, thereby constituting a third storage capacitor connected in parallel to the second capacitor.Type: GrantFiled: August 15, 2014Date of Patent: March 7, 2017Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventors: Longqiang Shi, Chihyuan Tseng, Wenhui Li, Yutong Hu, Hejing Zhang, Xiaowen Lv, Chihyu Su
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Patent number: 9589996Abstract: A method for manufacturing a display device includes providing a first substrate, forming at least one first capacitor on the first substrate, providing a second substrate having a gate drive element formed thereon, and bonding the first substrate in alignment with the second substrate.Type: GrantFiled: June 12, 2015Date of Patent: March 7, 2017Assignees: SHANGHAI AVIC OPTO ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.Inventors: Huijun Jin, Dongliang Dun, Xin Xu, Wantong Shao, Chen Chen
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Patent number: 9589997Abstract: Since the gate electrode (1) and the capacitor electrode (2) are made into a double layer structure, the first layers (1a, 2a) in contact with the substrate (0) are made of ITO, and the second layers (1b, 2b) in contact with the gate insulating layer (3) are made of an metallic oxide layer, it becomes possible to form the gate electrode (1) and the capacitor electrode (2) having high optical transparency and high conductivity. Therefore, it becomes possible to improve the optical transparency of a thin film transistor and to improve the display performance of an image displaying apparatus for which the thin film transistor is used by using the above-described gate electrode (1) and the above-described capacitor electrode (2).Type: GrantFiled: September 20, 2012Date of Patent: March 7, 2017Assignee: Toppan Printing Co., Ltd.Inventors: Chihiro Imamura, Manabu Ito
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Patent number: 9589998Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.Type: GrantFiled: January 29, 2016Date of Patent: March 7, 2017Assignee: Samsung Display Co., Ltd.Inventors: Do-Hyun Kim, Yoon Ho Khang, Dong-Hoon Lee, Sang Ho Park, Se Hwan Yu, Cheol Kyu Kim, Yong-Su Lee, Sung Haeng Cho, Chong Sup Chang, Dong Jo Kim, Jung Kyu Lee
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Patent number: 9589999Abstract: The present invention discloses a LTPS TFT pixel unit and a manufacture method thereof. The method comprises steps of: providing a substrate and forming a buffer layer on the substrate; forming a semiconductor pattern layer and a first insulative layer on the buffer layer, and the semiconductor pattern layer and the first insulative layer are located in the same layer and heights of the semiconductor pattern layer and the first insulative layer are the same. With the aforesaid arrangement, the present invention can reduce the side effect of the LTPS TFT pixel unit and promote the electrical property thereof.Type: GrantFiled: January 28, 2015Date of Patent: March 7, 2017Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventor: Zuyou Yang
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Patent number: 9590000Abstract: A laser designator system using modulated CW laser diodes and a conventional high pixel count image sensor array, such as CCD or CMOS array. These two technologies, diode lasers and imaging sensor arrays are reliable, widely used and inexpensive technologies, as compared with prior art pulsed laser systems. These systems are distinguished from the prior art systems in that they filter the laser signal spatially, by collecting light over a comparatively long period of time from a very few pixels out of the entire field of view of the image sensor array. This is in contrast to the prior art systems where the laser signal is filtered temporarily, over a very short time span, but over a large fraction of the field of view. By spatially filtering the signal outputs of the individual pixels, it becomes possible to subtract the background illumination from the illuminated laser spot.Type: GrantFiled: December 14, 2010Date of Patent: March 7, 2017Assignee: SHILAT OPTICAL SYSTEMS LTD.Inventors: Avishay Guetta, Michael Yagudaev, Doron Korngut
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Patent number: 9590001Abstract: A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device.Type: GrantFiled: June 8, 2015Date of Patent: March 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Solomon Assefa, Marwan H. Khater, Edward W. Kiewra, Carol Reinholm, Steven M. Shank
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Patent number: 9590003Abstract: In pixels that are two-dimensionally arranged in a matrix fashion in the pixel array unit of a solid-state imaging element, a photoelectric conversion film having a light shielding film buried therein is formed and stacked on the light incident side of the photodiode. The present technique can be applied to a CMOS image sensor compatible with the global shutter system, for example.Type: GrantFiled: June 19, 2014Date of Patent: March 7, 2017Assignee: SONY CORPORATIONInventor: Kenichi Nishizawa
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Patent number: 9590004Abstract: A solid-state imaging device includes a plurality of pixels, wherein one or more of the plurality of pixels have a pupil dividing portion and a light receiving portion, the light receiving portion includes a plurality of photoelectric conversion regions, an element isolation region is provided between adjacent ones of the plurality of photoelectric conversion regions, and wherein a scatterer is provided within the pupil dividing portion and above the element isolation region, and the scatterer is formed from a material of a refractive index smaller than a refractive index of a material of the pupil dividing portion peripheral to the scatterer.Type: GrantFiled: November 29, 2012Date of Patent: March 7, 2017Assignee: CANON KABUSHIKI KAISHAInventor: Kazuya Nobayashi
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Patent number: 9590005Abstract: An image sensor includes first and second pluralities of photodiodes interspersed among each other in a semiconductor substrate. Incident light is to be directed through a surface of the semiconductor substrate into the first and second pluralities of photodiodes. The first plurality of photodiodes has greater sensitivity to the incident light than the second plurality of photodiodes. A metal film layer is disposed over the surface of the semiconductor substrate over the second plurality of photodiodes and not over the first plurality of photodiodes. A metal grid is disposed over the surface of the semiconductor substrate, and includes a first plurality of openings through which the incident light is directed into the first plurality of photodiodes. The metal grid further includes a second plurality of openings through which the incident light is directed through the metal film layer into the second plurality of photodiodes.Type: GrantFiled: January 25, 2016Date of Patent: March 7, 2017Assignee: OmniVision Technologies, Inc.Inventors: Yin Qian, Ming Zhang, Chen-Wei Lu, Jin Li, Chia-Chun Miao, Dyson H. Tai
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Patent number: 9590006Abstract: There is provided a solid-state imaging apparatus including a plurality of photoelectric conversion regions which photoelectrically convert light incident from a rear surface side of a semiconductor substrate, element isolation regions formed between the plurality of photoelectric conversion regions arranged in a matrix shape, and shielding members formed on upper surfaces of the element isolation regions. The element isolation regions have high impurity concentration regions of a high impurity concentration connected to at least a part of the shielding members.Type: GrantFiled: December 30, 2015Date of Patent: March 7, 2017Assignee: Sony CorporationInventor: Yusuke Tanaka
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Patent number: 9590007Abstract: Provided is a solid state imaging device including: a pixel portion where pixel sharing units are disposed in an array shape and where another one pixel transistor group excluding transfer transistors is shared by a plurality of photoelectric conversion portions; transfer wiring lines which are connected to the transfer gate electrodes of the transfer transistors of the pixel sharing unit and which are disposed to extend in a horizontal direction and to be in parallel in a vertical direction as seen from the top plane; and parallel wiring lines which are disposed to be adjacent to the necessary transfer wiring lines in the pixel sharing unit and which are disposed to be in parallel to the transfer wiring lines as seen from the top plane, wherein voltages which are used to suppress potential change of the transfer gate electrodes are supplied to the parallel wiring lines.Type: GrantFiled: March 24, 2016Date of Patent: March 7, 2017Assignee: Sony CorporationInventors: Toshifumi Wakano, Fumihiko Koga
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Patent number: 9590008Abstract: A radiation-emitting semiconductor chip includes a carrier and a semiconductor body having a semiconductor layer sequence, wherein an emission region and a protective diode region are formed in the semiconductor body having the semiconductor layer sequence; the semiconductor layer sequence includes an active region that generates radiation and is arranged between a first semiconductor layer and a second semiconductor layer; the first semiconductor layer is arranged on a side of the active region facing away from the carrier; the emission region has a recess extending through the active region; the first semiconductor layer, in the emission region, electrically conductively connects to a first connection layer, wherein the first connection layer extends in the recess from the first semiconductor layer toward the carrier; the second semiconductor layer, in the emission region, electrically conductively connects to a second connection layer.Type: GrantFiled: May 4, 2015Date of Patent: March 7, 2017Assignee: OSRAM Opto Semiconductors GmbHInventors: Jürgen Moosburger, Norwin von Malm, Patrick Rode, Lutz Höppel, Karl Engl
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Patent number: 9590009Abstract: A semiconductor light emitting element includes a base body, a first semiconductor layer, a second semiconductor layer, a first light emitting layer, a first conductive layer, a third semiconductor layer, a fourth semiconductor layer, a second light emitting layer, a second conductive layer, a first member, and a second member. The first member includes a first end portion and a second end portion. The first end portion is positioned between the base body and the first conductive layer and electrically connected to the first conductive layer, the second end portion not overlapping the second conductive layer. The second member includes a third end portion and a fourth end portion. The third end portion is positioned between the base body and the second conductive layer and electrically connected to the second conductive layer. The fourth end portion is electrically connected to the second end portion.Type: GrantFiled: August 11, 2015Date of Patent: March 7, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Jumpei Tajima, Hiroshi Ono, Toshihide Ito, Kenjiro Uesugi, Shinya Nunoue
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Patent number: 9590010Abstract: Perpendicular magnetic tunnel junction (pMTJ) devices employing a pinned layer stack with a thin top anti-parallel (AP2) layer and having a transitioning layer providing a transitioning start to a body-centered cubic (BCC) crystalline/amorphous structure below the top anti-parallel (AP2) layer, to promote a high tunnel magnetoresistance ratio (TMR) with reduced pinned layer thickness are disclosed. A first anti-parallel (AP) ferromagnetic (AP1) layer in a pinned layer has a face-centered cubic (FCC) or hexagonal closed packed (HCP) crystalline structure. A transitioning material (e.g., Iron (Fe)) is provided in a transitioning layer between the AP1 layer and an AFC layer (e.g., Chromium (Cr)) that starts a transition from a FCC or HCP crystalline structure, to a BCC crystalline/amorphous structure.Type: GrantFiled: March 24, 2016Date of Patent: March 7, 2017Assignee: QUALCOMM IncorporatedInventors: Matthias Georg Gottwald, Jimmy Jianan Kan, Chando Park, Xiaochun Zhu, Seung Hyuk Kang
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Patent number: 9590011Abstract: A semiconductor device includes a pillar-shaped resistance-changing layer and a reset gate insulating film that surrounds the pillar-shaped resistance-changing layer. A reset gate surrounds the reset gate insulating film, and the reset gate is electrically insulated from the pillar-shaped resistance-changing layer.Type: GrantFiled: June 15, 2016Date of Patent: March 7, 2017Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9590012Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.Type: GrantFiled: June 30, 2014Date of Patent: March 7, 2017Assignee: MICRON TECHNOLOGY, INC.Inventors: Jong Won Lee, Gianpaolo Spadini, Derchang Kau
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Patent number: 9590013Abstract: A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode.Type: GrantFiled: October 8, 2014Date of Patent: March 7, 2017Assignee: CROSSBAR, INC.Inventors: Sung Hyun Jo, Wei Lu
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Patent number: 9590014Abstract: Resistance variable memory cell structures and methods are described herein. A number of embodiments include a first resistance variable memory cell comprising a number of resistance variable materials in a super-lattice structure and a second resistance variable memory cell comprising the number of resistance variable materials in a homogeneous structure.Type: GrantFiled: October 7, 2015Date of Patent: March 7, 2017Assignee: Micron Technology, Inc.Inventors: Sachin V. Joshi, F. Daniel Gealy
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Patent number: 9590015Abstract: A vertically integrated reconfigurable and programmable diode/memory resistor (1D1R) and thin film transistor/memory resistor (1T1R) structures built on substrates are disclosed.Type: GrantFiled: November 10, 2014Date of Patent: March 7, 2017Assignee: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEYInventors: Yicheng Lu, Yang Zhang, Chieh-Jen Ku
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Patent number: 9590016Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.Type: GrantFiled: December 11, 2015Date of Patent: March 7, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masaki Yamato, Yasuhiro Nojiri, Shigeki Kobayashi, Hiroyuki Fukumizu, Takeshi Yamaguchi
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Patent number: 9590017Abstract: Arrangements of pixel components that allow for full-color devices, while using emissive devices that use blue color altering layers in conjunction with blue emissive regions, that emit at not more than two colors, and/or that use limited number of color altering layers, are provided. Devices disclosed herein also may be achieved using simplified fabrication techniques compared to conventional side-by-side arrangements, because fewer masking steps may be required.Type: GrantFiled: April 2, 2014Date of Patent: March 7, 2017Assignee: Universal Display CorporationInventors: Michael Hack, Michael Stuart Weaver, Julia J. Brown, Xin Xu
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Patent number: 9590018Abstract: An organic light emitting display device including an organic light emitting element disposed on an insulation substrate, and an ambient light reflection preventing unit disposed on the organic light emitting element, the ambient light reflection preventing unit including a first metal layer, a first dielectric layer disposed on the first metal layer, the first metal layer and the first dielectric layer contacting each other, and a photovoltaic unit including the first metal layer as a first electrode.Type: GrantFiled: June 18, 2015Date of Patent: March 7, 2017Assignee: Samsung Display Co., Ltd.Inventors: Seong Min Wang, Mu Gyeom Kim
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Patent number: 9590019Abstract: A display apparatus capable of controlling light transmittance includes: a transparent organic light emitting device comprising a first region including an emission region capable of emitting light and a second region adjacent to the first region in a horizontal direction and including a transmission region capable of transmitting external light therethrough; and a light transmission control device coupled to and facing the transparent organic light emitting device, the light transmission control device comprising a third region formed at a location corresponding to the first region and a fourth region adjacent to the third region in the horizontal direction and positioned to correspond to the second region, wherein the fourth region comprises a sealed cavity having a transmission control material layer therein, and the transmission control material layer is configured to be selectively driven by the light transmission control device.Type: GrantFiled: July 16, 2015Date of Patent: March 7, 2017Assignee: SAMSUNG DISPLAY CO., LTD.Inventor: Sangil Kim
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Patent number: 9590020Abstract: The present invention provides a manufacture method of an AMOLED back plate and a structure thereof. The manufacture method of the AMOLED back plate is: sequentially deposing a buffer layer (2), an amorphous silicon layer (2) on a substrate (1), and crystallizing and converting the amorphous silicon layer to be a polysilicon layer, and patterning the polysilicon layer, and then deposing a P type heavy doped micro silicon layer (P+uc-Si), and implementing a photo process to define a position of a channel (40), and etching the P type heavy doped micro silicon layer (P+uc-Si) to form a source/a drain (41), and thereafter, sequentially forming a gate isolation layer (5), a gate (61), an interlayer insulation layer (7), a metal source/a metal drain (81), a flat layer (9), an anode (10), a pixel definition layer (11) and a photo spacer (12); the source/the drain (41) and the gate (61) do not overlap in the horizontal direction and are mutually spaced.Type: GrantFiled: February 9, 2015Date of Patent: March 7, 2017Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventor: Yuanjun Hsu
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Patent number: 9590021Abstract: A thin-film transistor includes a gate, a first source, a second source, a first drain, a second drain, a first semiconductor layer, a second semiconductor layer, a first insulation layer, and a second insulation layer. The gate includes a first surface and a second surface that are opposite to each other. The first insulation layer is formed on the first surface and covers the first surface. The first semiconductor layer is formed on the first insulation layer. The first drain and the first source are formed on the first semiconductor layer in a spaced manner. The second insulation layer is formed on the second surface and covers the second surface. The second semiconductor layer is formed on the second insulation layer. The second drain and the second source re formed on the second semiconductor layer in a spaced manner. Also disclosed are an array substrate and a display device.Type: GrantFiled: January 8, 2015Date of Patent: March 7, 2017Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventor: Yuejun Tang
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Patent number: 9590022Abstract: An organic electroluminescence (EL) device is provided, including a transparent substrate and an array of pixels over the transparent substrate. Each of the pixels includes at least one first sub-pixel and at least one second sub-pixel, wherein the at least one first sub-pixel each includes a first organic light emitting diode for providing light in a first direction, and the second sub-pixel each includes a second organic light emitting diode for providing light in a second direction substantially opposite to the first direction.Type: GrantFiled: May 26, 2015Date of Patent: March 7, 2017Assignee: AU OPTRONICS CORPORATIONInventor: Shuo-Hsiu Hu