Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.

Abstract: A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective.

Abstract: The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of In, Ga, and Cd for a total of 0.05 to 5 at %, and a balance being made up of Ag and incidental impurities.

Abstract: A pillar structure is disposed on a substrate. The pillar structure includes a pad, a metal wire bump, a metal wire, and a metal plating layer. The pad is disposed on the substrate. The metal wire bump is disposed on the pad. The metal wire is connected to the metal wire bump. The metal wire extends in a first extension direction, the substrate extends in a second extension direction, and the first extension direction is perpendicular to the second extension direction. The metal plating layer covers the pad and completely encapsulates the metal wire bump and the metal wire.

Abstract: A press fitting head comprising an elastic member in a part where the press fitting head contacts a semiconductor device, and an alignment mark recognition area capable of detecting an optically readable marker provided on a surface to be contacted to the semiconductor device is provided. Additionally, a semiconductor manufacturing apparatus in which the press fitting head is applied is provided.

Abstract: The present disclosure provides an apparatus for removing a chip, including: a loading station; a heating head arranged to soften an anisotropic conductive film on a substrate of a display panel for fixing the chip; a base table arranged on the loading station and arranged to support the display panel; and a base seat arranged on the loading station and arranged to support the heating head, wherein the heating head is rotatably mounted onto the base seat and the heating head has a rotation axis perpendicular to a surface of the loading station facing towards the base table. With the above apparatus, the face of the heating head facing towards the chip contacts with the face of the chip facing towards the heating head more sufficiently. The force to which the portion of the chip is subject is reduced and the force applied to the chip becomes more uniform.

Abstract: The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed flip-chip package includes a substrate, a reinforcement layer over an upper surface of the substrate, a flip-chip die attached to the upper surface of the substrate by interconnects through the reinforcement layer, an air cavity formed between the substrate and the flip-chip die, and a protective layer encapsulating the flip-chip die and defining a perimeter of the air cavity. Herein, a first portion of each interconnect is encapsulated by the reinforcement layer and a second portion of each interconnect is exposed to the air cavity. The reinforcement layer provides reinforcement to each interconnect.

Abstract: A heating method includes an oxide film forming step and a heating step. The thickness of an oxide film is set in a first range that includes a first maximal thickness and a second maximal thickness and that is smaller than a second minimal thickness in the relationship with the laser absorption having a periodic profile. The first maximal thickness corresponds to a first maximal value a of the laser absorption. The second maximal thickness corresponds to a second maximal value of the laser absorption. The second minimal thickness corresponds to a second minimal value of the laser absorption, namely the minimal value of the laser absorption that appears between the second maximal value and a third maximal value, or the maximal value of the laser absorption that appears subsequent to the second maximal value.

Abstract: A method of forming a plurality of semiconductor packages includes providing an array of unsingulated semiconductor packages that are at least partially encapsulated in an encapsulant. The array of unsingulated semiconductor packages may be coupled with a lead frame or a substrate. A first plurality of singulation lines are simultaneously etched in the encapsulant through slits in an etch mask using a plasma etching process and a fixture coupled with the array. A second plurality of parallel singulation lines may also be etched. The first and second pluralities of singulation lines may include substantially straight or arcuate lines. The second plurality of parallel singulation lines may be substantially perpendicular to the first plurality of parallel singulation lines and be formed using the plasma etching process, the fixture, and an etch mask. The formation of singulation lines in the array singulates the array into a plurality of singulated semiconductor packages.

Abstract: Methods, systems and devices are disclosed for performing a semiconductor processing operation. In some embodiments this includes configuring a wire bonding machine to perform customized movements with a capillary tool of the wire bonding machine, etching bulk contaminants over one or more locations of a semiconductor device with the capillary tool, and applying plasma to the semiconductor device to remove residual contaminants.

Abstract: A semiconductor device includes a plurality of semiconductor dies stacked vertically to have a vertical height and a dielectric surrounding the stacked semiconductor dies. The semiconductor device further has a conductive post external to the stacked semiconductor dies and extending through the dielectric. In the semiconductor device, a height of the conductive post is greater than the vertical height.

Abstract: Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.

Abstract: Provided are a semiconductor package and method for manufacturing the same. The semiconductor package includes a first semiconductor chip. A first mold layer is disposed on sidewalls of the first semiconductor chip. A second mold layer is disposed on an upper surface of the first mold layer. A first lower via hole penetrates the first mold layer. A first upper via hole penetrates the second mold layer. A first metal pad is disposed between the first upper via hole and the first lower via hole.

Abstract: A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the first die includes pads; a first enclosure that covers the first die; an interlinkage that extends to the first enclosure to electrically couple with the pads; a first redistribution body electrically coupled to the interlinkage, and being partially exposed on a surface of the stacked package structure to provide outer pins for electrically coupling to external circuitry; a penetrating body that penetrates the first enclosure and substrate; a second die having an electrode electrically coupled to a first terminal of the penetrating body; and a second terminal of the penetrating body that is exposed on the surface of the stacked package structure to provide outer pins for electrically coupling to the external circuitry.

Abstract: A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion.

Abstract: A method for fabricating an LED light bar and an LED light bar are provided. The method includes: providing a transparent base, wherein at least one framework region for fixing LED chips is arranged on the transparent base, at least one milling groove parallel to the framework region is arranged at each of two sides of each framework region; arranging one or more LED chips on the at least one framework region; covering an upper surface and a lower surface of the transparent base where the LED chips are arranged with a packaging adhesive mixed with fluorescent powder, and filling up the milling groove with the packaging adhesive; and cutting the transparent base along the milling groove, to obtain an LED light bar surrounded by the adhesive.

Abstract: A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a first doped region formed in the drain region. The source region and the drain region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The first doped region is electrically connected to a ground potential.

Abstract: A semiconductor apparatus includes a semiconductor substrate, a semiconductor element, an edge termination region that surrounds the semiconductor element, a protective diode that has a first terminal and a second terminal, where the first terminal is positioned within the edge termination region and the second terminal is positioned outside the edge termination region, and a diffusion layer that has a floating potential, where the diffusion layer is provided in a gap portion between a region of the edge termination region that is aligned with the protective diode and the protective diode.

Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second semiconductor region on the first electrode and having a higher carrier concentration of the second conductivity type than the second semiconductor region; a fourth semiconductor region; a fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; and a second electrode provided on the fifth semiconductor region and the seventh semiconductor region.

Abstract: A method for fabricating a complementary bipolar junction transistor (BJT) integrated structure. The method includes forming a first backplate in a monolithic substrate below a first buried oxide (BOX) layer. Another forming step forms a second backplate in the monolithic substrate below the first BOX layer. The second backplate is electrically isolated from the first backplate. Another forming step forms an NPN lateral BJT above the first BOX layer and superposing the first backplate. The NPN lateral BJT is configured to conduct electricity horizontally between an NPN emitter and an NPN collector when the NPN lateral BJT is active. Another forming step forms a PNP lateral BJT superposing the second backplate. The PNP lateral BJT is configured to conduct electricity horizontally between a PNP emitter and a PNP collector when the PNP lateral BJT is active.

Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.

Abstract: A semiconductor device includes a singulated region of semiconductor material having a first major surface and a second major surface opposite to the first major surface. In one embodiment, the second major surface includes a recessed surface portion bounded by opposing sidewall portions extending outward from the region of semiconductor material in cross-sectional view. The sidewall portions have outer surfaces defining peripheral edge segments of the singulated region of semiconductor material. An active device region is disposed adjacent to the first major surface and a first conductive layer is disposed adjoining the recessed surface portion. The recessed surface portion provides a semiconductor device having improved electrical characteristics, and the sidewall portions provide a semiconductor device that is less susceptible to warpage, breakage, and other reliability issues.

Abstract: A semiconductor device with a small number of transistors is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a first wiring, and a second wiring. The first transistor includes a first gate and a second gate. The first gate and the second gate overlap with each other with a semiconductor therebetween. The first wiring and the second wiring are supplied with a high power supply potential and a low power supply potential, respectively. A first terminal of the first transistor is electrically connected to the first gate and the first wiring. A second terminal of the first transistor is electrically connected to the second gate. The second terminal of the first transistor is electrically connected to the second wiring through the second transistor and the third transistor. The first transistor, the second transistor, and the third transistor are preferably n-channel transistors.

Abstract: A semiconductor device includes first and second Fin FET and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In a cross section a maximum width of the separation plug is located at a height Hb, which is less than ¾ of a height Ha of the separation plug.

Abstract: A semiconductor device includes a channel region of a first conductivity type, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, a first region of a second conductivity type and a second region of the second conductivity type, which are formed along the gate electrode while facing each other with the gate electrode interposed between the first region and the second region, a semiconductor region of the second conductivity type on which the first region, the second region and the channel region are formed, and an element isolation region which surrounds the semiconductor region. The gate electrode extends beyond a boundary portion between the channel region and the element isolation region. A width of the first region is smaller than a width of the second region in a channel width direction of the first region and the second region.

Abstract: Semiconductor devices are provided. A semiconductor device includes a first insulating material in a first fin. The semiconductor device includes a second insulating material in a second fin. The first and second insulating materials have different respective sizes. For example, in some embodiments, the first and second insulating materials have different respective widths and/or depths in the first and second fins, respectively.

Abstract: A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel.

Abstract: A semiconductor device excellent in writing operation is provided. In a structure where a data voltage supplied to a source line is supplied to a node of a memory cell via a bit line, a switch is provided between memory cells connected to the bit line. During a period in which the data voltage is supplied to the node of the memory cell, the switch on the bit line, which is provided between the memory cells, is off. With such a structure, parasitic capacitance of the bit line during a period in which the data voltage is supplied to the node of the memory cell can be reduced. As a result, writing of the data voltage into the memory cell can be performed fast.

Abstract: At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion.

Abstract: A metal strap is formed in a middle-of-line (MOL) process for communication between an eDRAM and a FinFET. An oxide is deposited in a trench over the eDRAM to prevent development of an epitaxial film prior to formation of the metal strap. The result is an epiless eDRAM strap in a FinFET.

Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.

Abstract: In general, according to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first sub-conductive layer, a first insulating film. One portion of the first conductive layer overlaps at least one portion of the first sub-conductive layer in the first direction. One other portion of the first conductive layer overlaps at least one portion of the second conductive layer in the first direction. One portion of the first insulating film overlaps at least one portion of the second conductive layer in the second direction. The One portion of the first insulating film overlaps one portion of the first sub-conductive layer in the second direction. The second conductive layer overlap one other portion of the first insulating film in a direction intersecting the second direction.

Abstract: Although photolithography is the preferred pattern-transfer method for even the 10 nm electrically-programmable memory (EPM, which comprises only periodic patterns), imprint-lithography is the preferred method to form the sub-25 nm printed memory (which comprises at least one non-periodic data-pattern). Accordingly, the present invention discloses an imprinted memory.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate. After formation of memory film layers, a sacrificial cover material layer can be employed to protect the tunneling dielectric layer during formation of a bottom opening in the memory film layers. An amorphous semiconductor material layer can be deposited and optionally annealed in an ambient including argon and/or deuterium to form a semiconductor channel layer having a thickness less than 5 nm and surface roughness less than 10% of the thickness. Alternately or additionally, at least one interfacial layer can be employed on either side of the amorphous semiconductor material layer to reduce surface roughness of the semiconductor channel. The ultrathin channel can have enhanced mobility due to quantum confinement effects.

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

Abstract: A single-poly NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first LDD region merged with the source doping region, a commonly-shared doping region, and a second LDD region merged with the commonly-shared doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region. A drain-side extension modified region is disposed under the spacer and in proximity to the drain doping region.

Abstract: The semiconductor device may include a first sub-pipe gate having a pipe hole formed therein; a second sub-pipe gate disposed on the first sub-pipe gate and passed-through by vertical holes being coupled to the pipe hole, wherein a material of the second sub-pipe gate has a lower oxidation rate than that of a material of the first sub-pipe gate; a first oxidized layer formed within a portion of the first sub-pipe gate to conform to a contour of the pipe hole; and a second oxidized layer formed within a portion of the second sub-pipe gate to conform to a contour of the vertical holes and the contour of the pipe hole.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack. The non-volatile memory cell is formed in the semiconductor substrate, and a top surface of the non-volatile memory cell is coplanar with or below a top surface of the semiconductor substrate. The gate stack is formed on the semiconductor substrate.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate. After formation of memory film layers, a sacrificial cover material layer can be employed to protect the tunneling dielectric layer during formation of a bottom opening in the memory film layers. An amorphous semiconductor material layer can be deposited and optionally annealed in an ambient including argon and/or deuterium to form a semiconductor channel layer having a thickness less than 5 nm and surface roughness less than 10% of the thickness. Alternately or additionally, at least one interfacial layer can be employed on either side of the amorphous semiconductor material layer to reduce surface roughness of the semiconductor channel. The ultrathin channel can have enhanced mobility due to quantum confinement effects.

Abstract: According to one embodiment, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends in a stacking direction through the stacked body. The semiconductor body includes an upper end portion protruding above the stacked body. The stacked film is provided between the semiconductor body and the electrode layers. The stacked film includes a charge storage portion. The conductor is provided at an upper surface and a side surface of the upper end portion of the semiconductor body. The conductor electrically contacts the upper surface and the side surface. The interconnect is provided above the conductor. The interconnect is electrically connected to the conductor.

Abstract: According to one embodiment, a semiconductor device includes a stacked body; a columnar portion; a plate portion; and a blocking insulating film. The stacked body includes a plurality of electrode layers. The columnar portion includes a semiconductor body and a charge storage film. The plate portion includes a conductor and a sidewall insulating film. The sidewall insulating film is provided between the conductor and the insulator and between the conductor and the electrode layers. The conductor contacts the major surface of the substrate. The blocking insulating film is provided between the sidewall insulating film and the insulator, between the insulator and the electrode layers, and between the charge storage film and the electrode layers. The blocking insulating film includes a first blocking insulating layer and a second blocking insulating layer, the second blocking insulating layer being different from the first blocking insulating layer.

Abstract: A semiconductor device includes a first stack including a plurality of alternating layers of first interlayer insulating layers and first conductive patterns; a second stack including a plurality of alternating layers of second conductive patterns and second interlayer insulating layers, the second stack being positioned above the first stack; a plurality of pillar-structures each pillar structure passing through the first and second stacks; and a ring pattern layer disposed between the first and second stacks, the ring pattern layer comprising a plurality of ring patterns, each ring pattern surrounding each pillar-structure.

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

Abstract: Methods of selectively etching tungsten from the surface of a patterned substrate are described. The etch electrically separates vertically arranged tungsten slabs from one another as needed, for example, in the manufacture of vertical flash memory devices. The tungsten etch may selectively remove tungsten relative to films such as silicon, polysilicon, silicon oxide, aluminum oxide, titanium nitride and silicon nitride. The methods include exposing electrically-shorted tungsten slabs to remotely-excited fluorine formed in a capacitively-excited chamber plasma region. The methods then include exposing the tungsten slabs to remotely-excited fluorine formed in an inductively-excited remote plasma system. A low electron temperature is maintained in the substrate processing region during each operation to achieve high etch selectivity.

Abstract: A semiconductor device includes a first FinFET device and a second FinFET device. The first FinFET device includes a first gate, a first source, and a first drain. The first FinFET device has a first source/drain proximity. The second FinFET device includes a second gate, a second source, and a second drain. The second FinFET device has a second source/drain proximity that is smaller than the first source/drain proximity. In some embodiments, \the first FinFET device is an Input/Output (I/O) device, and the second FinFET device is a non-I/O device such as a core device. In some embodiments, the greater source/drain proximity of the first FinFET device is due to an extra spacer of the first FinFET device that does not exist for the second FinFET device.

Abstract: A display device includes a first substrate including a display region and a non-display region, the non-display region being positioned on an outside of the display region, a first dam in the non-display region of the substrate, the first dam including a first barrier and a first stopper, the first stopper being on the first barrier and having a concave groove formed thereon, and a first alignment layer covering the display region of the first substrate, at least a part of the first alignment layer extending to the non-display region and contacting a surface of the first stopper.