Abstract: An array substrate, an electro-static discharge method thereof and a display device are disclosed. The array substrate includes: a plurality of data lines, a plurality of gate lines, a power signal line, a charge release signal line, a plurality of electro-static discharge units and at least one short circuit ring unit. The charge release signal line and the power signal line are disposed in parallel, two electro-static discharge units are disposed between them to form an electro-static discharge circuit, each gate line and/or each data line is connected with the charge release signal line by one electro-static discharge unit; the short circuit ring unit is connected between the charge release signal line and the power signal line.

Abstract: A display device that includes a substrate having a display region and an adjacent peripheral region is provided, including; a plurality of sub-pixels provided within the display region; a plurality of data lines electrically connected to the sub-pixels; and a first electronic circuit group and a second electronic circuit group provided in the peripheral region, connected to the corresponding data lines. The first electronic circuit group includes a plurality of first electronic circuits, and the second electronic circuit group includes a plurality of second electronic circuits. Two adjacent first electronic circuits are arranged with a first interval therebetween, and the first interval has a first width. Two adjacent second electronic circuits are arranged with a second interval therebetween, and the second interval has a second width. The first width and the second width are different.

Abstract: The present disclosure provides an array substrate, a method for manufacturing the same, and a display device relating to the technical field of the array substrate. The array substrate includes a base, a plurality of leads and a plurality of inclined supporting surfaces, wherein the inclined supporting surfaces are strip-like and are inclined relative to the base, and a length direction of each of the inclined supporting surfaces is parallel to the base; and at least a part of the leads are inclined leads, and at least a part of each of the inclined leads is arranged on the corresponding inclined supporting surface and extends in the length direction of the inclined supporting surface.

Abstract: Provided are liquid crystal display and the method for manufacturing the same. According to an aspect of the present invention, there is provided a liquid crystal display device, including a first substrate; a gate electrode disposed on the first substrate; a semiconductor pattern layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the semiconductor pattern layer and facing each other, wherein a diffusion prevention pattern is disposed on the semiconductor pattern layer to prevent diffusion into the semiconductor pattern layer or to maintain uniform thickness of the semiconductor pattern layer.

Abstract: The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (52?) with ion doping process, and the oxide conductor layer (52?) is employed as being the pixel electrode of the LCD to replace the ITO pixel electrode in prior art; the method manufactures the source (81), the drain (82) and the top gate (71) at the same time with one photo process; the method implements patterning process to the passivation layer (8) and the top gate isolation layer (32) together with one photo process, to reduce the number of the photo processes to nine for shortening the manufacture procedure, raising the production efficiency and lowering the production cost.

Abstract: The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized.

Abstract: The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized.

Abstract: The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized.

Abstract: The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized.

Abstract: A forming method for an array substrate is provided. The method includes: providing a substrate; forming multiple scanning lines and multiple data lines on the substrate, where the scanning lines cross the data lines and are insulated from the data lines, and the first data lines are arranged in the same layer as the scanning lines; forming a first insulating layer on the first data lines and the scanning lines, and forming first via holes in the first insulating layer; and forming second data lines on the first insulating layer, where the second data lines electrically connect to the first data lines via the first via holes, first signal lines are insulated from the second data lines and the first signal lines are in a same layer with the second data lines.

Abstract: A preparation method of a poly-silicon thin film transistor (TFT) array substrate and an array substrate thereof are provided. The preparation method includes: forming a photoresist layer on a poly-silicon layer, and exposing and developing the photoresist layer with a gray tone mask to form patterns of a photoresist completely-reserved region, a photoresist partially-reserved regions and a photoresist completely-removed region; removing part of the poly-silicon layer located in the photoresist completely-removed region, to form patterns of active layers; ashing the photoresist so as to expose part of the active layer located in the photoresist partially-reserved regions and inject P+ions of high concentration into the part of the active layer, to form doping regions of patterns of source-drain electrodes of a P-type TFT; and stripping off remaining photoresist.

Abstract: A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate and depositing a buffer layer; Step 2: depositing an a-Si layer; Step 3: depositing and patterning a silicon oxide layer; Step 4: taking the silicon oxide layer as a photomask and annealing the a-Si layer with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region and a second poly-Si region; Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions, and forming an LDD area; Step 7: depositing and patterning a gate insulating layer; Step 8: forming a first gate and a second gate; Step 9: forming via holes; and Step 10: forming a first source/drain and a second source/drain.

Abstract: A mask and a method for manufacturing a thin film transistor of a pixel area of an array substrate using the mask are disclosed. The mask comprises a mask body having a pattern area. The pattern area includes a photoresist partially removing area for removing photoresist partially; a photoresist completely removing area for removing photoresist completely and a first photoresist reserving area located between the photoresist partially removing area and the photoresist completely removing area and adjoining the photoresist partially removing area and the photoresist completely removing area for reserving photoresist, the first photoresist reserving area being designed to adjust a profile of a part of the photoresist corresponding to the photoresist partially removing area after exposure and development.

Abstract: A semiconductor on insulator substrate includes an electrically conductive layer disposed between an electrically insulating handle layer and the semiconductor layer to facilitate the application of a back bias. The connection of the electrically conductive layer to a reference voltage reduces the effects of trapped or fixed charges associated with the handle layer on the threshold voltage of a transistor formed on the semiconductor layer. Silicon-based devices formed on glass, plastic, and quartz substrates are among the devices that can benefit from the application of a back bias.

Abstract: An integrated radiation sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second lateral bipolar junction transistors (BJTs) having opposite polarities. The first lateral BJT has a base that is electrically coupled to the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure. The second lateral BJT is configured to amplify the output signal of the first bipolar junction transistor. The first and second lateral BJTs, the sensing structure, and the substrate on which they are formed comprise a monolithic structure.

Abstract: The present disclosure relates to a solid state imaging element and an electronic device that make it possible to improve sensitivity to light on a long wavelength side. A solid state imaging element according to a first aspect of the present disclosure has a solid state imaging element in which a large number of pixels are arranged vertically and horizontally, the solid state imaging element includes a periodic concave-convex pattern on a light receiving surface and an opposite surface to the light receiving surface of a light absorbing layer as a light detecting element. The present disclosure can be applied to, for example, a CMOS and the like installed in a sensor that needs a high sensitivity to light belonging to a region on the long wavelength side, such as light in the infrared region.

Abstract: A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate. The isolation structure is present in the semiconductor substrate and adjacent to the radiation-sensing region. The doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner.

Abstract: A chip package includes a chip, a dam element, and a height-increasing element. The chip has an image sensing area, a first surface, and a second surface opposite to the first surface. The image sensing area is located on the first surface of the chip. The dam element is located on the first surface of the chip and surrounds the image sensing area. The height-increasing element is located on the dam element, such that the dam element is between the height-increasing element and the chip.

Abstract: An apparatus comprises a first semiconductor chip including a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines, a second semiconductor chip having a surface in contact with a surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines and a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion over a first side of a hard mask layer and a second portion over a second side of the hard mask layer, wherein the hard mask layer is a ring-shaped layer, and wherein the conductive plug is formed in a center opening of the ring-shaped layer.

Abstract: An image sensor includes a sensor portion and an ASIC portion bonded to the sensor portion. The sensor portion includes a first substrate having radiation-sensing pixels, a first interconnect structure, a first isolation layer, and a first dielectric layer. The ASIC portion includes a second substrate, a second isolation layer, and a second dielectric layer. The material compositions of the first and second isolation layers and the first and second dielectric layers are configured such that the first and second isolation layers may serve as barrier layers to prevent copper diffusion into oxide. The first and second isolation layers may also serve as etching-stop layers in the formation of the image sensor.

Abstract: Systems and methods are directed to vertical legs for an infrared detector. For example, an infrared imaging device may include a microbolometer array in which each microbolometer includes a bridge and a vertical leg structure that couples the bridge to a substrate such as a readout integrated circuit. The vertical leg structure may run along a path that is parallel to a plane defined by the bridge and may be oriented perpendicularly to the plane. The path may be disposed within, below, or above the plane defined by the bridge.

Abstract: A plurality of pixel regions are aligned in a matrix in a semiconductor substrate, and each of the plurality of pixel regions includes an active region, two photoelectric conversion elements, two floating capacitance regions, and a first transistor. Each of the plurality of pixel regions includes two transfer transistors each having each of the two photoelectric conversion elements and each of the two floating capacitance regions. The first transistor is arranged within the pixel region, between one floating capacitance region and the other floating capacitance region of the two floating capacitance regions with respect to a direction in which the one floating capacitance region and the other floating capacitance region are aligned.

Abstract: The present technology relates to a solid-state imaging apparatus, a manufacturing method therefor, and an electronic apparatus by which fine pixel signals can be suitably generated. A charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges, a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section, and a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section are provided. A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor.

Abstract: The present disclosure relates to an image sensor having autofocus function and associated methods. In some embodiments, the integrated circuit has a photodiode array with a plurality of photodiodes disposed within a semiconductor substrate and a composite grid overlying the photodiode array and having a first plurality of openings and a second plurality of openings extending vertically through the composite grid. The integrated circuit further has an image sensing pixel array with a plurality of color filters disposed in the first plurality of openings. The integrated circuit further has a phase detection pixel array having a plurality of phase detection components that are smaller than the plurality of color filters and that have a low refractive index (low-n) material with a refractive index (n) smaller than a refractive index of the plurality of color filters, wherein the phase detection components are disposed in the second plurality of openings.

Abstract: A solid-state imaging device includes: a pixel region in which a plurality of pixels composed of a photoelectric conversion section and a pixel transistor is arranged; an on-chip color filter; an on-chip microlens; and a multilayer interconnection layer in which a plurality of layers of interconnections is formed through an interlayer insulating film. The solid-state imaging device further includes a light-shielding film formed through an insulating layer in a pixel boundary of a light receiving surface in which the photoelectric conversion section is arranged.

Abstract: The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.

Abstract: An ultrasonic sensor pixel includes a substrate, a piezoelectric micromechanical ultrasonic transducer (PMUT) and a sensor pixel circuit. The PMUT includes a piezoelectric layer stack including a piezoelectric layer disposed over a cavity, the cavity being disposed between the piezoelectric layer stack and the substrate, a reference electrode disposed between the piezoelectric layer and the cavity, and one or both of a receive electrode and a transmit electrode disposed on or proximate to a first surface of the piezoelectric layer, the first surface being opposite from the cavity. The sensor pixel circuit is electrically coupled with one or more of the reference electrode, the receive electrode and the transmit electrode and the PMUT and the sensor pixel circuit are integrated with the sensor pixel circuit on the substrate.

Abstract: In the method of manufacturing a magnetoresistive sensor module, at first a composite arrangement out of a semiconductor substrate and a metal-insulator arrangement is provided, wherein a semiconductor circuit arrangement is integrated adjacent to a main surface of the semiconductor substrate into the same, wherein the metal-insulator arrangement is arranged on the main surface of the semiconductor substrate and comprises a structured metal sheet and insulation material at least partially surrounding the structured metal sheet, wherein the structured metal sheet is electrically connected to the semiconductor circuit arrangement. Then, a magnetoresistive sensor structure is applied onto a surface of the insulation material of the composite arrangement, and finally an electrical connection between the magnetoresistive sensor structure and the structured metal sheet is established, so that the magnetoresistive sensor structure is connected to the integrated circuit arrangement.

Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.

Abstract: A semiconductor device includes an active region defining an isolation region. First and second cell interconnection structures are on the active region and the isolation region, and have line shapes that are parallel to each other. An isolation pattern is on the active region and the isolation region. The isolation pattern is between the first and second cell interconnection structures. Contact structures are between the first and second cell interconnection structures. The contact structures are at both sides of the isolation pattern and overlap the active region. Insulating patterns are between the first and second cell interconnection structures. The insulating patterns are at both sides of the isolation pattern and overlap the isolation region. Common source regions are under the first and second cell interconnection structures. The common source regions are in the active region. An isolating gate pattern that has a line shape is under the isolation pattern.

Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.

Abstract: A magnetic tunnel junction (MTJ) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.

Abstract: A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends.

Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a source pattern, a drain pattern, a nano wire pattern and a gate. The source pattern may be formed on an upper surface of the semiconductor substrate. The drain pattern may be formed on the upper surface of the semiconductor substrate. The drain pattern may be spaced apart from the source pattern. The nano wire pattern may be arranged between the source pattern and the drain pattern. The gate may be configured to surround the nano wire pattern. The nano wire pattern may include an inner wire and an outer wire. The inner wire may include a first semiconductor material. The outer wire may include a second semiconductor material having a band gap greater than a band gap of the first semiconductor material. The outer inner may be formed on an outer surface of the inner wire.

Abstract: A programmable resistive memory having a plurality of programmable resistive cells. At least one of the programmable resistive cell includes a programmable resistive element and at least one selector. The selector can be built in at least one fin structure and at least one active region divided by at least one MOS gate into a first active region and a second active region. The first active region can have a first type of dopant to provide a first terminal of the selector. The second active region can have a first or a second type of dopant to provide a second terminal of the selector. The MOS gate can provide a third terminal of the selector. The first terminal of the selector can be coupled to the first terminal of the programmable resistive element. The programmable resistive element can be programmed by conducting current flowing through the selector to thereby change the resistance state.

Abstract: An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a plurality of first lines extending in a first direction; a plurality of second lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements disposed between the first lines and the second lines and located at intersections of the first lines and the second lines; and a plug connected to a first portion of each of the first lines, wherein the plug comprises a conductive layer and a material layer having a resistance value higher than that of the conductive layer.

Abstract: A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

Abstract: A 1-Selector n-Resistor memristive device includes a first electrode, a selector, a plurality of memristors, and a plurality of second electrodes. The selector is coupled to the first electrode via a first interface of the selector. Each memristor is coupled to a second interface of the selector via a first interface of each memristor. Each second electrode is coupled to one of the memristors via a second interface of each memristor.

Abstract: A method of producing a transistor array, comprising an array of addressing conductors each providing the source electrodes of a respective set of transistors and at least part of a conductive connection between a respective driver terminal and said source electrodes; wherein the method comprises: forming a conductor layer on a support; and displacing a plurality of portions of said conductor layer relative to other portions of said conductor layer to create from said conductor layer at least (i) said array of addressing conductors and an array of drain conductors at said first level, (ii) conductor element islands in transistor channel regions at a second level, and (iii) one or more further conductor elements at a third level.

Abstract: According to one embodiment, a photoelectric conversion device includes a first electrode, a second electrode, a photoelectric conversion layer provided between the first electrode and the second electrode, and a first layer provided between the second electrode and the photoelectric conversion layer, the first layer including a phenyl pyridine derivative. The phenyl pyridine derivative is represented by formula (1) below, Rings A, B, C, and D in the formula (1) are pyridine rings. Each of R1 to R11 in the formula (1) is one selected from the group consisting of hydrogen, a straight-chain alkyl group, a branched alkyl group, an aryl group, and an electron-withdrawing heteroaryl group.

Abstract: A top-emitting organic electroluminescent display panel, a manufacturing method, and a display device. The top-emitting organic electroluminescent display panel comprises: a substrate, a layer of white organic light emitting diodes and a thin film encapsulation layer arranged on the substrate in sequence. The thin film encapsulation layer comprises at least two inorganic thin film layers and at least one organic thin film layer. At least one organic thin film layer is a color filter layer, the color filter layer being arranged between the at least two inorganic thin film layers. Since one of the organic thin film layers in the thin film encapsulation layer is a color filter layer, the color filter layer does not have to be arranged above the thin film encapsulation layer separately, thus reducing the number of film lavers, simplifying the film layer structure, reducing manufacturing costs, and improving the luminous efficiency and the display effect.

Abstract: The present application discloses an array substrate comprising a sub-pixel having a first light emitting area and a second light emitting area structurally different from the first light emitting area. The sub-pixel comprises a first electrode on a base substrate; a first light emitting layer in the first light emitting area and a second light emitting layer in the second light emitting area, the first light emitting layer and the second light emitting layer made of a same material and on a side of the first electrode distal to the base substrate; and a first tuning layer between the first light emitting layer and the first electrode in the first light emitting area.

Abstract: An organic radiation-emitting component and a method for manufacturing an organic radiation-emitting component are disclosed. In an embodiment, the component includes a base substrate and a plurality of light-emitting units disposed on the base substrate, wherein the light-emitting units are arranged laterally offset with respect to one another, wherein the plurality of light-emitting units is divided into light-emitting units of a first type and light-emitting units of a second type, wherein a current flow through the light-emitting units of the first type is directed in an opposite direction to a current flow through the light-emitting units of the second type during operation, and wherein the light-emitting units are grouped in neighboring pairs, each neighboring pair consists of a light-emitting unit of a first type and a light-emitting unit of a second type, both first electrodes or both second electrodes of which are electrically connected to one another.

Abstract: A display apparatus includes a display area and a non-display area around the display area. A substrate includes a plurality of pixels. Each pixel includes a first area through which light is emitted and a second area through which external light is transmitted. The plurality of pixels is arranged in a matrix in the display area. The substrate includes a transmission area, through which external light is transmitted, in the non-display area. An encapsulation thin film seals the substrate.

Abstract: Embodiments relate to an organic light emitting display device according to the present disclosure including: a plurality of pixels which includes red, white, blue, and green sub-pixels; driving transistor, each of which is disposed in each sub-pixel; and organic light emitting diodes, each of which is disposed corresponding to each sub-pixel, wherein a first step portion, first and second bank layers, and a first step compensation portion are disposed between the white sub-pixel and a sub-pixel adjacent thereto, thereby having an effect of suppressing a short circuit defect and a light leakage defect. In addition, an organic light emitting display device according to the present disclosure includes: red, white, blue, and green sub-pixels; at least one step portion between the sub-pixels; first and second bank layers; and a step compensation portion, thereby having an effect of suppressing a short circuit defect and a light leakage defect.

Abstract: An organic EL element includes: a substrate that is light-transmissive; a pair of electrode layers (first electrode layer and second electrode layer) disposed above the substrate, at least one of the pair of electrode layers being light-transmissive; and a planar light-emitting layer disposed between the first electrode layer and second electrode layer. The first electrode layer is disposed in a first region in a plan view. The organic EL element further includes a buffer layer disposed, in a plan view, in a second region adjacent the first region. The buffer layer is for reducing a difference in an optical characteristic between the first region and the second region with respect to a predetermined light.

Abstract: A display device includes: a substrate; a plurality of light-emission elements arranged, on the substrate, in a first direction and a second direction intersecting each other, each of the light-emission elements having a first electrode layer, an organic layer including a luminous layer, and a second electrode layer which are laminated in that order; and a separation section disposed, on the substrate, between the light-emission elements adjacent to each other in the first direction, the separation section having two or more pairs of steps. The first electrode layers in the light-emission elements are separated from each other, and the organic layers as well as the second electrode layers in the light-emission elements adjacent to each other in the first direction are separated from each other by the steps included in the separation section.

Abstract: The present application discloses an array substrate comprising a pixel unit comprising a bottom emitting organic light emitting diode, a top emitting organic light emitting diode, a first drive thin film transistor, and a second drive thin film transistor. The first drive thin film transistor is connected to the bottom emitting organic light emitting diode for driving the bottom emitting organic light emitting diode to emit light. The second drive thin film transistor is connected to the top emitting organic light emitting diode for driving the top emitting organic light emitting diode to emit light.

Abstract: A display device includes a substrate including an outer area neighboring a border; and an insulating layer positioned over the substrate and including a plurality of openings positioned over the outer area. The openings are arranged to be spaced from each other in a direction. The display device further includes a wavy line extending in the direction and passing the plurality of openings.

Abstract: The present invention provides a method for manufacturing a TFT substrate and a structure thereof. The method for manufacturing a TFT substrate uses a gray tone mask to apply a single photolithographic process to simultaneously manufacture a gate insulation layer, a semiconductor layer, and a etch stop so as to reduce the number of the photolithographic processes used from ten processes to eight processes and reduce the number of masks used thereby simplifying the manufacturing process and effectively increasing the manufacturing efficiency and the yield rate. The TFT substrate structure of the present invention includes a gate insulation layer, a semiconductor layer, and an etch stop layer that are manufactured at the same time with a photolithographic process by using a gray tone mask so that the structure is simple, the manufacturing is easy, and the manufacturing efficiency and yield rate are effectively increased.