Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.

Abstract: A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

Abstract: Present embodiments provide for a CMOS structure and a fabrication method thereof. While the source-drain epitaxial material formed in each of the PMOS device region and the NMOS device region, deuterium gas is used as the carrier gas to store the deuterium atoms in the interstice of the source-drain epitaxial material as an impurity. Since the source-drain epitaxial material is used as a source-drain, which is quite near the gate, the deuterium atoms can diffuse out from the source-drain epitaxial material during the process of forming the gate dielectric layer and covalently bound to the dangling bonds at the interface between the gate dielectric layer and the substrate, so as to obtain more stable structure, avoid penetration of the carriers, and eliminate hot carrier effects, such that performance and resilience of the device are increased.

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract: A semiconductor device includes a substrate, an insulating structure, and a gate stack. The substrate has at least one semiconductor fin. The insulating structure is disposed above the substrate and separated from the semiconductor fin to form a gap therebetween. The insulating structure has a sidewall facing the semiconductor fin. The gate stack covers at least a portion of the semiconductor fin and is at least disposed in the gap between the insulating structure and the semiconductor fin. The gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer covers the semiconductor fin while leaves the sidewall of the insulating structure uncovered. The gate electrode is disposed above the high-? dielectric layer and at least in the gap between the insulating structure and the semiconductor fin.

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about le18 to about le20 atoms/cm3 and contacting the epitaxial contacts.

Abstract: The disclosure provides a method of manufacturing a thin film transistor on a base substrate by patterning an active layer comprising a metal oxynitride, and treating the active layer with a plasma comprising oxygen.

Abstract: A semiconductor device or the like capable of preventing malfunction of a driver circuit is provided. In a driver circuit for driving a power device used for current supply, a transistor including an oxide semiconductor is used as a transistor in a circuit (specifically, for example, a level shift circuit) requiring a high withstand voltage. In addition, a transistor (for example, a silicon transistor or the like) capable of higher operation than a transistor including an oxide semiconductor is preferably used as a transistor in a circuit (specifically, for example, a buffer circuit, a flip-flop circuit, or the like) requiring a lower withstand voltage than the level shift circuit.

Abstract: An oxide semiconductor layer is formed, a gate insulating layer is formed over the oxide semiconductor layer, a gate electrode layer is formed to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween, a first insulating layer is formed to cover the gate insulating layer and the gate electrode layer, an impurity element is introduced through the insulating layer to form a pair of impurity regions in the oxide semiconductor layer, a second insulating layer is formed over the first insulating layer, the first insulating layer and the second insulating layer are anisotropically etched to form a sidewall insulating layer in contact with a side surface of the gate electrode layer, and a source electrode layer and a drain electrode layer in contact with the pair of impurity regions are formed.

Abstract: An array substrate and a manufacturing method thereof, a display panel, and a display device are provided. The array substrate includes a substrate; a source-drain metallic layer and a first passivation metallic protective layer formed in sequence on the substrate, the source-drain metallic layer including a source electrode and a drain electrode not contacted with each other; a conductive protection layer formed on the substrate on which the first passivation metallic protection layer has been formed; and a pixel electrode formed on the substrate on which the conductive protection layer has been formed, the pixel electrode contacting the conductive protection layer.

Abstract: A semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, and an oxide insulating film covering the transistor. The multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide insulating film contains more oxygen than that in the stoichiometric composition, and in the transistor, by a bias-temperature stress test, threshold voltage does not change or the amount of the change in a positive direction or a negative direction is less than or equal to 1.0 V, preferably less than or equal to 0.5 V.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a diffusion region, a first oxide layer, a second oxide layer and a polysilicon layer. The diffusion region is formed in the substrate and has a source and a drain extended along a first direction. The first oxide layer is formed on the substrate. The second oxide layer is formed in the substrate and adjacent to the drain. The polysilicon layer is formed on the substrate and has a first region, a second region, and a third region. The second region is formed on an edge of the second oxide layer and between the first region and the third region. A width of the second region is less than a width of the first region and a width of the third region along the first direction.

Abstract: An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided.

Abstract: One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.

Abstract: A method of manufacturing an array substrate is discussed. The method includes forming a gate line on a substrate including a pixel region, forming a gate electrode on the substrate and connected to the gate line, and forming a gate insulating layer on the gate line and the gate electrode. The method further includes forming a data line on the gate insulating layer and crossing the gate line to define the pixel region, forming a source electrode and a drain electrode on the gate insulating layer and corresponding to the gate electrode, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode, and forming an oxide semiconductor layer on top of the source and drain electrodes.

Abstract: A thin film transistor array substrate includes a pixel electrode layout area, a data electrode layout area, a transparent pixel electrode layer formed in the pixel electrode layout area, a first metal layer, a first dielectric layer, an amorphous silicon layer, a second metal layer, a second dielectric layer formed in the pixel electrode layout area and the data electrode layout area. The first dielectric layer covers the first metal layer. The amorphous silicon layer, the second metal layer and the second dielectric layer are sequentially formed on the first dielectric layer. The transparent pixel electrode layer is connected to the second metal layer through a via hole formed in the pixel electrode area of the second dielectric layer. Moreover, a method for manufacturing the thin film transistor array and a liquid crystal display including the thin film transistor array substrate also are provided.

Abstract: The present disclosure relates to a thin film transistor, a method for manufacturing a thin film transistor and an array substrate. The thin film transistor comprises an active layer, a source and a drain, the source comprising a source first conductive layer and a source first buffer layer, the drain comprising a drain first conductive layer and a drain first buffer layer; at least a part of an upper surface of the source first buffer layer and at least a part of an upper surface of the drain first buffer layer being in contact with a lower surface of the active layer, at least a part of a side wall of the source first conductive layer and at least a part of a side wall of the drain first conductive layer being in contact with the active layer, the side wall of the source first conductive layer and the side wall of the drain first conductive layer in contact with the active layer being formed with an oxide layer.

Abstract: A Gate-All-Around (GAA) Field Effect Transistor (FET) can include a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, a height that is perpendicular to the horizontal direction, and a length that extends in the horizontal direction, where the width of the horizontal nanosheet conductive channel structure defines a physical channel width of the GAA FET. First and second source/drain regions can be located at opposing ends of the horizontal nanosheet conductive channel structure and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.

Abstract: Provided is a device with improved reverse-recovery immunity of a diode element. The device includes: a first conductivity-type drift layer; a second conductivity-type anode region provided in an upper portion of the drift layer; a second conductivity-type extraction region in contact with and surrounding the anode region; and a second conductivity-type field limiting ring region surrounding and separated from the extraction region at the upper portion of the drift layer, wherein the extraction region has a greater depth than the anode region and the field limiting ring region.

Abstract: A semiconductor device includes a substrate, a well region of a first-conductivity type disposed in the substrate, a first impurity region of a second-conductivity type and having a plurality of branches disposed in the well region, a second impurity region of the first-conductivity type and having a plurality of branches, and a third impurity region of the first-conductivity type disposed in the well region. The second-conductivity type is opposite to the first-conductivity type. A portion of the first impurity region overlaps a portion of the third impurity region. The plurality of branches of the second impurity region are disposed in the third impurity region, and a portion of the third impurity region is disposed between the first impurity region and the second impurity region.

Abstract: A field effect diode comprises: a substrate; a nucleation layer, a back barrier layer, a channel layer, a first barrier layer and a second barrier layer sequentially located on the substrate; and an anode and a cathode located on the second barrier layer, wherein a groove is formed in the second barrier layer, two-dimensional electron gas is formed at an interface between the first barrier layer and the channel layer except for a part of the interface under the groove when a reverse bias voltage or no external voltage is applied to the field effect diode, and is formed at all parts of the interface when a forward bias voltage is applied to the field effect diode.

Abstract: A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and first semiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive layer. A second semiconductor die is disposed adjacent to the first semiconductor die.

Abstract: The present invention relates to a method of manufacturing a photovoltaic device having an ultra-shallow junction layer. In the method, a crystalline silicon substrate is cleaned and a first doped semiconductor layer with 1.12 eV bandgap and 5˜80 nm of thickness is grown on the crystalline silicon substrate by high density plasma electron cyclotron resonance CVD in a preparation condition of a temperature of the crystalline silicon substrate ranging from 50° C. to 250° C. , about 500W of microwave power, deposition pressure below 50 mTorr, about 20 sccm of argon and hydrogen flow rate, SiH4 flow rate ranging from 1 sccm to 2 sccm, and 2% boroethane flow rate ranging from about 5 seem to 15 sccm. The photovoltaic device of the present invention has advantages of abrupt homo-junction, ultra-thin high-crystallinity silicon-based thin film, highly-doped concentration, high conductivity and high short-circuit current, thereby having improved efficiency.

Abstract: Deposition processes are disclosed herein for depositing thin films comprising a dielectric transition metal compound phase and a conductive or semiconducting transition metal compound phase on a substrate in a reaction space. Deposition processes can include a plurality of super-cycles. Each super-cycle may include a dielectric transition metal compound sub-cycle and a reducing sub-cycle. The dielectric transition metal compound sub-cycle may include contacting the substrate with a dielectric transition metal compound. The reducing sub-cycle may include alternately and sequentially contacting the substrate with a reducing agent and a nitrogen reactant. The thin film may comprise a dielectric transition metal compound phase embedded in a conductive or semiconducting transition metal compound phase.

Abstract: Provided is a method for fabricating a nanopatterned surface. The method includes forming a mask on a substrate, patterning the substrate to include a plurality of symmetry-breaking surface corrugations, and removing the mask. The mask includes a pattern defined by mask material portions that cover first surface portions of the substrate and a plurality of mask space portions that expose second surface portions of the substrate, wherein the plurality of mask space portions are arranged in a lattice arrangement having a row and column, and the row is not oriented parallel to a [110] direction of the substrate. The patterning the substrate includes anisotropically removing portions of the substrate exposed by the plurality of spaces.

Abstract: System and method of providing a photovoltaic (PV) cell having a cushion layer to alleviate stress impact between a front metal contact and a thin film PV layer. A cushion layer is disposed between an extraction electrode and a photovoltaic (PV) surface. The cushion layer is made of a nonconductive material and has a plurality of vias filled with a conductive material to provide electrical continuity between the bus bar and the PV layer. The cushion layer may be made of a flexible material preferably with rigidity that matches the substrate. Thus, the cushion layer can effectively protect the PV layer from physical damage due to tactile contact with the front metal contact.

Abstract: A photovoltaic or light detecting device is provided that includes a periodic array of dome or dome-like protrusions at the light impingement surface and three forms of reflector/back electrode at the device back. The beneficial interaction between an appropriately designed top protrusion array and these reflector/electrode back contacts (R/EBCs) serve (1) to refract the incoming light thereby providing photons with an advantageous larger momentum component parallel to the plane of the back (R/EBC) contact and (2) to provide optical impedance matching for the short wavelength incoming light. The reflector/back electrode operates as a back light reflector and counter electrode to the periodic array of dome or dome-like structures. A substrate supports the reflector/back electrode.

Abstract: The invention relates to a material comprising at least one compound having formula Bi1?xMxAg1?y??M?yOS1?zM?z, the methods for producing said material and the use thereof as a semiconductor, such as for photovoltaic or photochemical use and, in particular, for supplying a photocurrent. The invention further relates to photovoltaic devices using said compounds.

Abstract: Techniques for achieving band gap grading in CZTS/Se absorber materials are provided. In one aspect, a method for creating band gap grading in a CZTS/Se absorber layer includes the steps of: providing a reservoir material containing Si or Ge; forming the CZTS/Se absorber layer on the reservoir material; and annealing the reservoir material and the CZTS/Se absorber layer under conditions sufficient to diffuse Si or Ge atoms from the reservoir material into the CZTS/Se absorber layer with a concentration gradient to create band gap grading in the CZTS/Se absorber layer. A photovoltaic device and method of forming the photovoltaic device are also provided.

Abstract: An alloy composition for a subcell of a solar cell is provided that has a bandgap of at least 0.9 eV, namely, Ga1-xInxNyAs1-y-zSbz with a low antimony (Sb) content and with enhanced indium (In) content and enhanced nitrogen (N) content, achieving substantial lattice matching to GaAs and Ge substrates and providing both high short circuit currents and high open circuit voltages in GaInNAsSb subcells for multijunction solar cells. The composition ranges for Ga1-xInxNyAs1-y-zSbz are 0.07?x?0.18, 0.025?y?0.04 and 0.001?z?0.03.

Abstract: A photodetector includes a first doped region disposed in a semiconductor material and a second doped region disposed in the semiconductor material. The second doped region is electrically coupled to the first doped region, and the second doped region is of an opposite majority charge carrier type as the first doped region. The photodetector also includes a quantum dot layer disposed in a trench in the semiconductor material, and the quantum dot layer is electrically coupled to the second doped region. A transfer gate is disposed to permit charge transfer from the second doped region to a floating diffusion.

Abstract: Disclosed are a photoelectronic device using a hybrid structure of silica nanoparticles and graphene quantum dots and a method of manufacturing the same. The photoelectronic device according to the present disclosure has a hybrid structure including graphene quantum dots (GODs) bonded to surfaces of silica nanoparticles (SNPs), thereby increasing energy transfer efficiency.

Abstract: A multijunction solar cell and its method of manufacture including interconnected first and second discrete semiconductor regions disposed adjacent and parallel to each other in a single semiconductor body, including first top subcell, second (and possibly third) lattice matched middle subcells; and a bottom solar subcell adjacent to said last middle subcell and lattice matched thereto; wherein the interconnected regions form at least a four junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor region and the bottom solar subcell in the second semiconductor region.

Abstract: A photovoltaic cell is provided that can be used under high levels of solar concentration (?1000 suns). The present cell includes at least one junction produced on a substrate based on gallium antimonide, the at least one junction having two alloys based on an antimonide material (Ga1-xAlxAsySb1-y) lattice-matched on the substrate GaSb. If there are several junctions, two neighbouring junctions are separated by a tunnel junction.

Abstract: The disclosure describes multi-junction solar cell structures that include two or more graded interlayers.

Abstract: Multijunction photovoltaic cells having at least three subcells are disclosed, in which at least one of the subcells comprises a base layer formed of GaInNAsSb. The GaInNAsSb subcells exhibit high internal quantum efficiencies over a broad range of irradiance energies.

Abstract: A multijunction solar cell and its method of manufacture including interconnected first and second discrete semiconductor regions disposed adjacent and parallel to each other in a single semiconductor body, including first top subcell, second (and possibly third) lattice matched middle subcells; a graded interlayer adjacent to the last middle solar subcell; and a bottom solar subcell adjacent to said graded interlayer being lattice mismatched with respect to the last middle solar subcell; wherein the interconnected regions form at least a four junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor region and the bottom solar subcell in the second semiconductor region.

Abstract: A multijunction solar cell assembly and its method of manufacture including first and second discrete and different semiconductor body subassemblies which are electrically interconnected to form a five junction solar cell, each semiconductor body subassembly including first, second, third and fourth lattice matched subcells; wherein the average band gap of all four cells in each subassembly is greater than 1.44 eV.

Abstract: Thin-film photovoltaic devices and methods of their use and manufacture are disclosed. More particularly, polycrystalline CuIn(1-x)GaxSe2 (CIGS) based thin-film photovoltaic devices having independently tunable sublayers are disclosed. Also provided are methods of producing an n-doped graphene.

Abstract: A network of photovoltaic strips positioned in front of an image causes a decrease in the luminosity of said image, which is not uniform for all of the colours and causes an optical moiré phenomenon that is perceived by the observer when they change their viewing angle. In order to rectify said decrease in visual quality of the image, the invention describes a suitable positioning and dimension of the photovoltaic strips in relation to the inter-pixels of the image.

Abstract: An electronic device includes a substrate, an optical sensor coupled to the substrate, and an optical emitter coupled to the substrate. A lens is aligned with the optical emitter and includes an upper surface and an encapsulation bleed stop groove around the upper surface. An encapsulation material is coupled to the substrate and includes first and second encapsulation openings therethrough aligned with the optical sensor and the lens, respectively.

Abstract: Indentation approaches for foil-based metallization of solar cells, and the resulting solar cells, are described. For example, a method of fabricating a solar cell includes forming a plurality of alternating N-type and P-type semiconductor regions in or above a substrate. The method also includes locating a metal foil above the alternating N-type and P-type semiconductor regions. The method also includes forming a plurality of indentations through only a portion of the metal foil, the plurality of indentations formed at regions corresponding to locations between the alternating N-type and P-type semiconductor regions. The method also includes, subsequent to forming the plurality of indentations, isolating regions of the remaining metal foil corresponding to the alternating N-type and P-type semiconductor regions.

Abstract: A solar cell includes a metal layer and a chalcopyrite compound semiconductor layer in this order on a polyimide film. A manufacturing method according to the present invention includes the following steps in the order: cast applying a polyimide precursor solution onto a support base containing an alkali metal; imidizing the polyimide precursor by heating to form a stacked body including a polyimide film on the support base; forming a metal layer on the polyimide film of the stacked body; and forming a chalcopyrite compound semiconductor layer on the metal layer.

Abstract: A method of preparing two dimension bent X-ray crystal analyzers in strips feature is provided. A crystal wafer in strips is bonded to a curved substrate which offers the desired focus length. A crystal wafer in strips is pressed against the surface of the substrate forming curved shape by anodic bonding or glue bonding. The bonding is permanently formed between crystal wafer and its substrate surface, which makes crystal wafer has same curvature as previously prepared substrate.

Abstract: A wafer-holding apparatus for electroplating of a solar cell wafer is provided. The wafer has chamfered corners and comprises a plurality of busbar areas, wherein at least one busbar area is near an edge of the wafer. The wafer-holding apparatus includes a plurality of wafer-holding mechanisms for maintaining contact with a wafer. One of the plurality of wafer-holding mechanisms can be longer than at least one other wafer-holding mechanism, thereby facilitating secure contact with the busbar area near the edge of the wafer, which is shorter than other busbar areas on the wafer due to the chamfered corners.

Abstract: A laser processing system can be utilized to produce high-performance interdigitated back contact (IBC) solar cells. The laser processing system can be utilized to ablate, transfer material, and/or laser-dope or laser fire contacts. Laser ablation can be utilized to remove and pattern openings in a passivated or emitter layer. Laser transferring may then be utilized to transfer dopant and/or contact materials to the patterned openings, thereby forming an interdigitated finger pattern. The laser processing system may also be utilized to plate a conductive material on top of the transferred dopant or contact materials.

Abstract: A method for manufacturing a light emitting device includes a) forming a first light confinement layer having a plurality of openings on or above one main surface of an oriented polycrystalline substrate, said oriented polycrystalline substrate including a plurality of oriented crystal grains; b) stacking an n-type layer, an active layer, and a p-type layer; c) forming a second light confinement layer on said first light confinement layer so that said second light confinement layer covers said plurality of first columnar structures and said second columnar structure; d) forming a transparent conductive film on said second light confinement layer; e) forming a pad electrode on said transparent conductive film; and f) forming a cathode electrode electrically connected to ends of said plurality of first columnar structures closer to said oriented polycrystalline substrate.

Abstract: A semiconductor structure includes a nanocrystalline core comprising a first semiconductor material, and at least one nanocrystalline shell comprising a second, different, semiconductor material that at least partially surrounds the nanocrystalline core. The nanocrystalline core and the nanocrystalline shell(s) form a quantum dot. An insulator layer encapsulates the quantum dot to create a coated quantum dot, and at least one additional insulator layer encapsulates the coated quantum dot.

Abstract: Light-emitting devices and methods, wherein, in some embodiments, the devices each include a first mirror having a first face, wherein the first mirror includes a metal and, in some embodiments, is a grown-epitaxial metal mirror (GEMM); and an epitaxial structure, wherein the epitaxial structure is lattice matched with and in contact with at least a first portion of the first face of the first mirror, wherein the epitaxial structure includes an active region configured to emit light at a wavelength ?, and wherein the active region is located a first non-zero distance away from the first face of the first mirror such that there is plasmonic coupling between the active region and the first mirror.

Abstract: A non-polar blue light LED epitaxial wafer based on an LAO substrate comprises the LAO substrate, and a buffer layer, a first non-doped layer, a first doped layer, a quantum well layer, an electron barrier layer and a second doped layer that are sequentially arranged on the LAO substrate. A preparation method of the non-polar blue light LED epitaxial wafer includes: a) adopting the LAO substrate, selecting a crystal orientation, and cleaning a surface of the LAO substrate; b) annealing the LAO substrate, and forming an AlN seed crystal layer on the surface of the LAO substrate; and c) sequentially forming a non-polar m face GaN buffer layer, a non-polar non-doped u-GaN layer, a non-polar n-type doped GaN film, a non-polar InGaN/GaN quantum well, a non-polar m face AlGaN electron barrier layer and a non-polar p-type doped GaN film on the LAO substrate by adopting metal organic chemical vapor deposition.