Abstract: A method for manufacturing a surface-mount electronic device includes making a first partial cut from a bottom of an assembly that includes a first semiconductor body that is disposed on a first die pad, a second semiconductor body that is disposed on a second die pad, and a plurality of terminal regions that is disposed between the first and second die pads. The first partial cut forms a recess by removing a portion of each of the terminal regions. The recess is defined by a transverse wall, a first sidewall, and a second sidewall. The first and second sidewalls and the transverse wall are coated with an anti-oxidation layer. A second partial cut is made from the top, where the second partial cut removes the transverse wall, separates the first and second semiconductor bodies, and has a width that is greater than a width of the first partial cut.

Abstract: A semiconductor device includes a lead frame including a die paddle and a lead, a semiconductor chip, and a clip. The semiconductor chip has a first side and a second side opposite to the first side. The first side is attached to the die paddle and the second side includes a first bond pad and a second bond pad. The clip electrically couples the first bond pad to the lead. The clip contacts the first bond pad at a first edge portion of the first bond pad adjacent to the second bond pad and defines a first cavity between a central portion of the first bond pad and the clip. Solder is within the first cavity to electrically couple the clip to the first bond pad. The semiconductor device includes a first opening to the first cavity to route flux away from the second bond pad during reflow soldering.

Abstract: A method of manufacturing a packaged semiconductor device includes patterning and plating silver nanoparticles in bonding areas of a lead frame, forming a hydrophilic group while oxidizing the silver nanoparticles, forming wire bonds on the silver nanoparticles, and encapsulating the wire bonds and the silver nanoparticles.

Abstract: An electronic chip is disclosed, including at least one electronic circuit and two or more contact-making pins, wherein the chip additionally has at least one fixing pin. A sensor arrangement is also disclosed for detecting at least one physical or chemical variable relating to a carrier. The sensor arrangement has at least one sensor element which is directly or indirectly coupled to the carrier, and also has an electronic interface arrangement with at least one leadframe, at least one electronic circuit connected to the leadframe, and also at least one electrically insulating housing part which is embodied in such a way that it performs at least one of the functions of (i) at least partly enclosing the at least one electronic circuit, and (ii) mechanically supporting at least parts of the leadframe to one another.

Abstract: A surface-mount electronic device includes a body of semiconductor material, and a lead frame that includes a plurality of contact terminals. The plurality of contact terminals is electrically connected to the semiconductor body. The contact terminals are formed of sintered material.

Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).

Abstract: A common connecting section for connection to terminals at the same potential in circuits is placed outside a mold section to allow a reduction in size of a semiconductor module 1. Since the common connecting section is a portion of a lead frame which would be placed within such a mold section in a conventional semiconductor module, the mold section can be reduced in size as compared with the conventional one, thereby reducing the amount of mold resin and the material cost.

Abstract: Leadless electronic packages for GaN-based half bridge power conversion circuits have low inductance internal and external connections, high thermal conductivity and a large separation between external connections for use in high voltage power conversion circuits. Some electronic packages employ “L” shaped power paths and internal low impedance die to die connections. Further embodiments employ an insulative substrate disposed within the electronic package for efficient power path routing and increased packaging density.

Abstract: Semiconductor packages are provided. A semiconductor package may include an embedding substrate including a cavity therein and a connection window in a bottom portion of the cavity. The semiconductor package may include a semiconductor chip disposed in the cavity and coupled to chip connectors, the chip connectors of the semiconductor chip inserted into the connection window. The semiconductor package may include a dielectric layer filling the cavity and the connection window and configured to expose end portions of the chip connectors and to substantially cover the semiconductor chip. Related memory cards and related electronic systems are also provided.

Abstract: A semiconductor package includes an output inductor placed over a support substrate, a power semiconductor die having a bottom surface situated on the support substrate and a top surface having an active region, where the output inductor is coupled to the active region on the top surface of the support substrate, and where the support substrate includes a plurality of bar vias. The output inductor is a packaged component having at least two leads in electrical connection with the active region of the power semiconductor die. The support substrate further includes routing conductors in electrical connection with the active region of the power semiconductor die. The power semiconductor die includes a control transistor and a sync transistor connected in a half-bridge.

Abstract: A chip packaging structure includes a chip, a passive component, and at least two metal lines. In the chip, first bonding pads, second bonding pads and connecting pads are disposed above an integrated circuit, and the second bonding pads and the connecting pads are separated from the integrated circuit. The second bonding pads are electrically connected to the corresponding connecting pads, respectively. The passive component is disposed on the chip, and includes two electrodes that are respectively electrically connected to and adhered to one of the corresponding connecting pad. The metal lines are disposed on the chip, and have one end thereof respectively connected to the second bonding pads, and the other end respectively connected to the first bonding pads.

Abstract: A driving circuit and a pin output order arranging method are disclosed. The driving circuit includes (M*N) pins and an arranging module. A first pin˜an N-th pin of the (M*N) pins, a (N+1)-th pin˜an 2N-th pin of the (M*N) pins, . . . , a [(M?1)*N+1]-th pin˜a (M*N)-th pin of the (M*N) pins are arranged along a first direction in a specific distance spaced to form a first row of pins˜an M-th row of pins. The first row of pins˜the M-th row of pins are staggered along a second direction in a staggering way or an aligning way. M and N are integers larger than 1. The arranging module correspondingly arranges the pin output order of the (M*N) pins according to different application modes of the driving circuit.

Abstract: A method of producing a semiconductor package includes planarizing a surface extending from at least part of connection regions to a pair of terminals by disposing a semiconductor element and a capacitor element such that the semiconductor element and the capacitor element do not overlap each other in plan view of the semiconductor element, and by filling a portion between the semiconductor element and the capacitor element with an insulator layer; directly connecting part of the connection regions and one of the pair of terminals to a first metal layer by forming the first metal layer on top of the connection regions, on top of the pair of terminals, and on top of the insulator layer; forming a dielectric layer on top of the first metal layer; and forming a capacitor layer by forming a second metal layer on top of the dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate; and a plurality of parallel first conductive layers formed on the substrate. The semiconductor structure also includes a composite magnetic structure having a plurality of magnetic layers and a plurality of insulation layers with a sandwich arrangement formed on a portion of the substrate and portions of surfaces of the plurality of first conductive layers. Further, the semiconductor structure includes a plurality of first conductive vias and a plurality of second conductive vias formed on the first conductive layers at both sides of the composite magnetic structure. Further, the semiconductor structure also includes a plurality of second conductive layers formed on a top surface of the composite magnetic structure, top surfaces of the first conductive vias, and top surfaces of the second conductive vias to form at least one coil structure wrapping around the composite magnetic structure.

Abstract: A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects are configured to provide a first signal. The fourth interconnect extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects are configured to provide a second signal different than the first signal.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming first patterns on a workpiece layer, and forming second patterns containing a first metal on side faces of the first patterns. The method further includes removing the first patterns after forming the second patterns, and forming third patterns on side faces of the second patterns by a chemical change of the first metal after removing the first patterns. The method further includes removing the second patterns after forming the third patterns, and processing the workpiece layer by using the third patterns as a mask after removing the second patterns.

Abstract: The present invention utilizes a barrier layer in the contact hole to react with an S/D region to form a silicide layer. After forming the silicide layer, a directional deposition process is performed to form a first metal layer primarily on the barrier layer at the bottom of the contact hole, so that very little or even no first metal layer is disposed on the barrier layer at the sidewall of the contact hole. Then, the second metal layer is deposited from bottom to top in the contact hole as the deposition rate of the second metal layer on the barrier layer is slower than the deposition rate of the second metal layer on the first metal layer.

Abstract: A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract: The invention relates to a method for marking wafers, in particular wafers for solar cell production: The method comprises the steps of manufacturing a position line (21a, 21b, 21c) on a peripheral surface of a silicon ingot or column, the ingot or column extending in an axial direction and having a longitudinal axis in the axial direction, wherein the position line extends in the axial direction along substantially the whole ingot or column and is inclined with respect to the longitudinal axis. By this position line it is possible to determine the position of a wafer cut from the ingot or column within the ingot or column, respectively. Further, an individual identification pattern (20a, 20b, 20c) of lines on the peripheral surface of the silicon ingot or column is manufactured, the individual identification pattern of lines extending in axial direction over substantially the whole ingot or column and providing an individual coding which allows to identify the silicon ingot or column.

Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a first wafer and a second wafer. The light source is configured to provide a first light directed to the first wafer and a second light directed to the second wafer. The light detection device is configured to detect reflected light intensity from the first wafer to find a position of at least one wafer alignment mark of the first wafer and to detect reflected light intensity from the second wafer to find a position of at least one wafer alignment mark of the second wafer.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. And, a plurality of doping regions are located beneath the first seal ring structure.

Abstract: Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

Abstract: A semiconductor device, including: an intermediate plate; a semiconductor element connected to one of surfaces of the intermediate plate by a brazing filler metal; a main plate connected to the other one of the surfaces of the intermediate plate by a brazing filler metal; and a resin layer, the intermediate plate having an external region extending to an outer side with respect to a region in which the intermediate plate is connected to the brazing filler metal, a first through-hole extending through the intermediate plate in the external region, the resin layer covering at least the brazing filler metal, the intermediate plate and a surface of the main plate in which the main plate faces the intermediate plate, the resin layer being also arranged inside the first through-hole.

Abstract: A laminate includes a core, a buildup layer having a top and a bottom, the bottom contacting the core and a solder mask contacting the top, the solder mask including at least one warpage control region formed on a top surface of the solder mask.

Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

Abstract: An integrated circuit (IC) structure for radio frequency circuits having a grounded die seal that mitigates the effects of parasitic coupling through the die seal. Embodiments include conductive grounding ties that each electrically couple one or more of the internal grounding pads on an IC die within the magnetic loop formed by the die seal ring to an adjacent extent of an IC die seal. Induced parasitic energy within the die seal ring is quickly coupled to ground through the corresponding grounding ties and grounding pads. Accordingly, very little, if any, induced parasitic energy is propagated around the die seal ring.

Abstract: A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife.

Abstract: A semiconductor device includes a semiconductor substrate, and a redistribution layer (RDL) over the semiconductor substrate and configured to receive a bump. The semiconductor device further includes a polymeric material over the RDL, and the polymeric material includes an opening to expose a portion of the RDL. In the semiconductor device, a barrier is covering a joint between the polymeric material and the RDL.

Abstract: A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

Abstract: An embodiment method includes providing a carrier having a recess and attaching a die to the carrier, wherein the die is at least partially disposed in the recess. The method further includes forming a molding compound over the carrier and around at least a portion of the die, forming fan-out redistribution layers over the molding compound and electrically connected to the die, and removing the carrier.

Abstract: A semiconductor chip may include a semiconductor substrate, a first central pad, a second central pad, a first peripheral pad, a second peripheral pad, a first pad line and a second pad line. The semiconductor substrate may have an active face. The first central pad and the second central pad may be arranged on a central region of the active face. The first peripheral pad and the second peripheral pad may be arranged on an edge region of the active face. The first pad line may be connected between the first central pad and the first peripheral pad. The second pad line may be connected between the second central pad and the second peripheral pad.

Abstract: The present invention relates to a terminal structure comprising; a base material 10; an external electrode 20 formed on the base material; an insulating coating layer 30 formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal layer 70 filling the opening and covering part of the insulating coating layer; and a dome-shaped bump 85 covering the under-bump metal layer, wherein in a cross section along a lamination direction, the under-bump metal layer has a convex shape toward the bump, and the thickness Tu0 of the under-bump metal layer at a center of the opening is equal to or greater than the thickness Tu1 of the under-bump metal layer at an end portion of the opening.

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract: A stacked semiconductor device is provided in the present invention. The stacked semiconductor device includes a first substrate and a second substrate. A first conductive pad is disposed on the first substrate. A conductive pillar contacts the first conductive pad. At least one first barrier layer is disposed inside the conductive pillar. The conductive pillar encapsulates the first barrier layer. The elastic modulus of the first barrier layer is different from the elastic modulus of conductive pillar. A second conductive pad is disposed on the second substrate. A solder bump is disposed between the first substrate and the second substrate. The solder bump electrically connects to the conductive pillar. The conductive pillar can optionally include a truncated cone.

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

Abstract: A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer is formed such a portion of the solder resist layer and a portion of the first conductive trace collectively have a T-shaped cross section.

Abstract: An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a semiconductor material wafer including a main surface; each chip includes respective integrated electronic components and respective contact pads facing the main surface; said contact pads are electrically coupled to the integrated electronic components; b) attaching at least one conductive ribbon to at least one contact pad of each chip; c) covering the main surface of the semiconductor material wafer and the at least one conductive ribbon with a layer of plastic material; d) lapping an exposed surface of the layer of plastic material to remove a portion of the plastic material layer at least to uncover portions of the at least one conductive ribbon, and e) sectioning the semiconductor material wafer to separate the chips.

Abstract: A bonding method for bonding a semiconductor chip to an underlying structure includes aligning an electrical contact of a lower surface of the semiconductor chip with an electrical connection member of an upper surface of the underlying structure, the electrical contact at least partially encased by a support material. The method further includes first heating the semiconductor chip and the underlying structure, deforming the electrical contact, and curing the support material encasing the deformed electrical contact. The method still further includes second heating the semiconductor chip and the underlying structure to bond the electrical contact of the semiconductor chip to the electrical connection member of the underlying structure while maintaining the support material in a cured state.

Abstract: An electrical apparatus includes a first electrical component; a second electrical component; and an In—Sn—Ag alloy connecting the first electrical component and the second electrical component, the In—Sn—Ag alloy containing AgIn2 and Ag2In, a Ag2In content being lower than a AgIn2 content.

Abstract: A first semiconductor structure having a first metallic structure that has a convex outermost surface and a second semiconductor structure having a second metallic structure that has a concave outermost surface are first provided. The first and second metallic structures are provided utilizing liner systems that have an opposite galvanic reaction to the metal or metal alloy that constitutes the first and second metallic structures such that during a planarization process the metal liners have a different removal rate than the metal or metal alloy that constitutes the first and second metallic structures. The first semiconductor structure and the second semiconductor structure are then bonded together such that the convex outermost surface of the first metallic structure is in direct contact with the concave outermost surface of the second metallic structure.

Abstract: A method for bonding of a first, at least partially metallic contact surface of a first substrate to a second, at least partially metallic contact surface of a second substrate, with the following steps, especially the following progression: application of a sacrificial layer which is at least partially, especially predominantly soluble in the material of at least one of the contact surfaces to at least one of the contact surfaces, bonding of the contact surfaces with at least partial solution of the sacrificial layer in at least one of the contact surfaces.

Abstract: According to a method for producing a circuit carrier arrangement, a carrier which has a surface section formed by an aluminum/silicon carbide metal matrix composite material is provided. A circuit carrier, which has an insulation carrier with a lower side onto which a lower metallization layer is applied, is also provided. A bonding layer, which contains a glass, is generated on the surface section. A material-fit connection between the bonding layer and the circuit carrier is produced by means of a connecting layer.

Abstract: A wire bonding apparatus comprises an ultrasonic transducer including a capillary, a flexible connecting frame having a first side to which the ultrasonic transducer is connected and at least one electrically-driven actuator which is connected to a second side of the flexible connecting frame that is opposite to the first side thereof, the actuator having a longitudinal actuation direction. An elongated slit located in the flexible connecting frame extends substantially transversely to the actuation direction of the at least one actuator to form at least one pivot point adjacent to an end of the slit about which the flexible connecting frame is rotatable when it is driven by the at least one actuator.

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.

Abstract: A bonding material stack for wafer-to-wafer bonding is provided. The bonding material stack may include a plurality of layers each including boron and nitrogen. In one embodiment, the plurality of layers may include: a first boron oxynitride layer for adhering to a wafer; a boron nitride layer over the first boron oxynitride layer; a second boron oxynitride layer over the boron nitride layer; and a silicon-containing boron oxynitride layer over the second boron oxynitride layer.