Abstract: The present disclosure provides a Gate driver On Array (GOA) unit, a method for manufacturing the GOA unit, a display substrate and a display device. The GOA unit includes a capacitor structure including: a first metal layer arranged on a substrate; an insulation layer arranged on the first metal layer, wherein the insulation layer is thinned out and has a first thickness, and the first thickness is less than a thickness of any other layer arranged on a same layer as the insulation layer in the display substrate; and a second metal layer arranged on the insulation layer.

Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

Abstract: A method of fabrication an array substrate which includes foaming an oxide semiconductor layer on a substrate; forming a gate insulating layer corresponding to a central portion of the oxide semiconductor layer; forming a first reactive metallic pattern and second reactive metallic patterns on the gate insulating layer and portions of the oxide semiconductor layer exposed outside the gate insulating layer, respectively; forming a gate electrode on the first reactive metallic pattern; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing heat treatment such that materials of the second reactive metallic patterns are diffused into the oxide semiconductor layer contacting the second reactive metallic patterns; forming an inter insulating layer on the gate electrode and having first contact holes that expose the second reactive metallic patterns; and forming source and drain electrodes on the inter insulating layer and contacting the second reactive metallic pa

Abstract: A mask set, a pixel unit and a manufacturing method thereof, an array substrate and a display device are provided to overcome the problem of low brightness of a display screen of a display device. In the pixel unit, the maximum size value of an overlapped area between an active layer and a drain electrode of a thin-film transistor (TFT) in the direction parallel to data line is less than the size value of one side, overlapped with the data line, in an overlapped area between the active layer and a source electrode; and the source electrode is the portion of the data line disposed in an overlapped area between the active layer and the data line. The pixel unit has the advantages of a larger opening area and higher light transmittance. Thus, the brightness of a display screen of the display device comprising the pixel units can be enhanced. Moreover, the problem of screen flicker can be avoided to some extent, and hence the display quality of images can be improved.

Abstract: A doping method for an array substrate and a manufacturing equipment. The doping method comprises: using a halftone mask to form a photoresist pattern layer on a gate insulation layer of a substrate; wherein, a polysilicon pattern layer is disposed on the substrate; the gate insulation layer covers the polysilicon pattern layer; the photoresist pattern layer corresponding to a heavily doping region forms a hollow portion; the photoresist pattern layer corresponding to a lightly doping region forms a first photoresist portion; the photoresist pattern layer corresponding to an undoped region forms a second photoresist portion; the first photoresist portion is thinner than the second photoresist portion; and performing one doping process to the polysilicon pattern layer such that the heavily doping region and the lightly doping region of the polysilicon pattern layer are formed simultaneously in order to reduce the manufacturing process of an LTPS array substrate.

Abstract: A method of manufacturing a solid-state image sensor, including a first transistor for transferring charges from a charge accumulation region to a first charge holding region and a second transistor for transferring charges from the first charge holding region to a second charge holding region, the method comprising forming, on the semiconductor substrate, a resist pattern having a opening on the first charge holding region, and injecting a impurity via the opening so as to make the first charge holding region be a buried type, wherein the impurity is injected such that an impurity region, which makes the first charge holding region be a buried type, is formed at a position away from an end of the gate electrode of the second transistor.

Abstract: Pixel arrays of an image sensor that include a first pixel and a second pixel adjacent the first pixel are provided. The first pixel may include a first photoelectric conversion device, a first charge storage device, a first floating diffusion node and a first transfer gate. The second pixel may include a second photoelectric conversion device, a second charge storage device, a second floating diffusion node and a second transfer gate. The pixel arrays may also include a storage gate on both the first charge storage device and the second charge storage device. The storage gate may have a unitary structure.

Abstract: A unit pixel formed on a substrate and configured to convert incident light to an electrical signal is provided. The unit pixel includes: a source having a source voltage supplied thereto and having a silicide layer for metal contact formed thereabove; a drain spaced apart from the source and having a silicide layer for metal contact formed thereabove; a channel formed between the source and the drain and having a current flowed therethrough; an insulating layer formed above the channel; and a floating gate having a nonsal structure in which no silicide layer is formed thereabove in order to facilitate an absorption of light, formed above the insulating layer so as to be placed between the source and the drain, and configured to control an amount of current flowing through the channel by an electric field generated by electron-hole pairs generated by the incident light.

Abstract: An imaging device that includes a substrate, a photoelectric conversion section disposed in the substrate, an element isolation region disposed adjacent to the photoelectric conversion section, a floating diffusion electrically connected to the photoelectric conversion section, an amplification transistor having a gate electrode and an active region, and a contact section disposed on the gate electrode of the amplification transistor. The contact section overlaps the active region of the amplification transistor. The floating diffusion is electrically connected to the gate electrode of the amplification transistor via the contact section. The width of the gate electrode of the amplification transistor is larger than a width of the active region of the amplification transistor. The photoelectric conversion section includes a first type impurity, and the element isolation region includes a second type impurity having a conductivity opposite to the first type impurity.

Abstract: A process of forming optical sensors includes sealing an imaging portion of each of a plurality of optical sensors on a sensor wafer with a transparent material. The operation of sealing leaves a bonding portion of each of the optical sensors exposed. The process further includes cutting the wafer into a plurality of image sensor dies after sealing the optical sensors such that each image sensor die includes one of the optical sensors sealed with a corresponding portion of the transparent material.

Abstract: A semiconductor package includes a substrate, an image sensor chip mounted on the substrate, a holder disposed on the substrate and surrounding the image sensor chip, and the holder has an inner surface facing the image sensor chip and an outer surface opposite to the inner surface. The semiconductor package further includes a transparent cover combined with the holder, and the transparent cover is spaced apart from and faces the substrate. The holder includes: a hole penetrating the holder from the inner surface to the outer surface. In addition, the semiconductor package further includes a first stopper disposed in the hole and a second stopper disposed at a position corresponding to the hole on the outer surface of the holder.

Abstract: An image sensing device includes: an active layer with a plurality of photo-sensing elements; a color pattern disposed over one of the photo-sensing elements, wherein the color pattern has a color selected from the group consisting of red (R), green (G), and blue (B); a microlens disposed on the color pattern; and a transmissive pattern being adjacent to the color pattern and over another one of the photo-sensing elements, wherein the transmissive pattern includes a color filter portion and a microlens portion, and an absolute value of a difference of refractive indexes between the microlens and the color pattern is less than 0.3, and there is no difference of refractive indexes between the microlens portion and the color filter portion of the transmissive pattern.

Abstract: Example embodiments relate to an image sensor supporting a global shutter for minimizing image distortion. An example image sensor includes a semiconductor layer having a first surface and a second surface that are opposite to each other; a photosensitive device, which is formed in the semiconductor layer near the first surface and accumulates charges based on light incident via the second surface; a charge storage device, which is formed in the semiconductor layer near the first surface and temporarily stores charges accumulated by the photosensitive device; a first transmission transistor, which transmits charges accumulated by the photosensitive device to the charge storage device and includes a first gate formed on the first surface of the semiconductor layer; and a leakage photogenerated charge drain region, which is formed in the semiconductor layer near the second surface, is apart from the charge storage device, and is arranged above the charge storage device.

Abstract: A solid-state imaging device is provided. The solid-state imaging device includes a plurality of arrayed pixels, an optical inner filter layer, and a light-blocking side wall. The plurality of arrayed pixels each includes a photoelectric conversion portion and a pixel transistor. The optical inner filter layer is provided for blocking infrared light and formed facing to a light-receiving surface of the photoelectric conversion portion of a desired pixel among the arrayed pixels. The light-blocking side wall is formed on a lateral wall of the optical inner filter layer.

Abstract: The invention relates to an optoelectronic module, more particularly to an optoelectronic chip-on-board module. The optoelectronic module comprises a substrate, wherein the substrate has a planar design. Furthermore, the optoelectronic module comprises a plurality of optoelectronic components that are arranged on the substrate. Furthermore, the optoelectronic module comprises a lens system having a plurality of lenses. The lens system comprises at least two lenses with different directivities.

Abstract: An image sensor package includes a die having an active side surface and a backside surface opposite to each other and having a bonding pad disposed on the active side surface, a through via penetrating the die and being electrically connected to the bonding pad, and a first dielectric layer disposed between the through via and the die. The first dielectric layer extends to cover the backside surface of the die. A redistribution line is disposed on the first dielectric layer and is electrically connected to the through via. The redistribution line extends onto the first dielectric layer on the backside surface of the die. A second dielectric layer is disposed on the first dielectric layer to cover the redistribution line and to extend onto an outer sidewall of the die. Related methods are also provided.

Abstract: A solid-state image pickup device capable of suppressing the generation of dark current and/or leakage current is provided. The solid-state image pickup device has a first substrate provided with a photoelectric converter on its primary face, a first wiring structure having a first bonding portion which contains a conductive material, a second substrate provided with a part of a peripheral circuit on its primary face, and a second wiring structure having a second bonding portion which contains a conductive material. In addition, the first bonding portion and the second bonding portion are bonded so that the first substrate, the first wiring structure, the second wiring structure, and the second substrate are disposed in this order. Furthermore, the conductive material of the first bonding portion and the conductive material of the second bonding portion are surrounded with diffusion preventing films.

Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region and a logic region. A first resist protect oxide (RPO) is formed over the pixel region, but not over the logic region. Silicide contacts are formed on the top of active devices formed in the pixel region, but not on the surface of the substrate in the pixel region, and silicide contacts are formed both on the top of active devices and on the surface of the substrate in the logic region. A second RPO is formed over the pixel region and the logic region, and a contact etch stop layer is formed over the second RPO. These layers help to reflect light back to the image sensor when light impinges the sensor from the backside of the substrate, and also helps prevent damage that occurs from overetching.

Abstract: A light emitting structure includes lower and upper semiconductor layers having different conductive types, and an active layer disposed between the lower and upper semiconductor layers. The light emitting structure is provided on the substrate. A first electrode layer provided on the upper semiconductor layer includes a first adhesive layer and a first bonding layer overlapping each other. A reflective layer is not provided between the first adhesive layer and the first bonding layer.

Abstract: According to one embodiment, a magnetoresistive memory device, includes a metal buffer layer provided on a substrate, a crystalline metal nitride buffer layer provided on the metal buffer layer, and a magnetoresistive element provided on the metal nitride buffer layer. The metal nitride buffer layer and the metal buffer layer contain a same material.

Abstract: A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends.

Abstract: A semiconductor diode includes a first semiconductor pattern including a first impurity, a first diffusion barrier pattern on the first semiconductor pattern, an intrinsic semiconductor pattern on the first diffusion barrier pattern, a second diffusion barrier pattern on the intrinsic semiconductor pattern, and a second semiconductor pattern including a second impurity on the second diffusion barrier pattern.

Abstract: A semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same are provided. A plurality of active lines are formed in a semiconductor substrate. A gate electrode having a lower height than each active line is formed on a sidewall of the active line. A first insulating layer having a height lower than that of the active line and higher than that of the gate electrode is buried between active lines, and a silicide layer is formed on an exposed upper surface and a lateral surface of the active line.

Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.

Abstract: The invention provides an organic electroluminescent display panel and a display device. The organic electroluminescent display panel of the invention includes a substrate, and a plurality of sub-pixel units of the same shape formed on the substrate, each sub-pixel unit including 6 sub-pixel elements of the same color, the geometric shape of each sub-pixel element being such that the center of the sub-pixel unit where it is located is taken as a vertex; the sub-pixel units are in 3 colors, any two adjacent sub-pixel units being different in color; the connecting lines of the centers of every two adjacent sub-pixel units among 3 sub-pixel units adjacent to each other form an equilateral triangle, 3 sub-pixel elements defined by that equilateral triangle form one pixel unit.

Abstract: An organic light-emitting diode (OLED) display and fabrication method thereof are provided. The OLED display includes an organic light-emitting layer comprising a plurality of primary color regions and a plurality of mixed color regions, wherein the primary color regions and the mixed color regions have the same light emitting direction. A color shift prevention layer is disposed above or under the organic light-emitting layer, the color shift prevention layer comprising a plurality of opaque patterns disposed on the light emitting direction of the corresponding mixed color regions. The color shift prevention layer incorporated in the OLED display is able to block the mixed light emitted from the mixed color regions of the organic light-emitting layer. Therefore, the color shift problem can be solved.

Abstract: A method of manufacturing an organic light emitting display device. The method according to one embodiment includes forming a first electrode over a substrate in which red, green, and blue pixel areas are defined; forming a first hole transporting layer on the first electrode; forming a second hole transporting layer in a position corresponding to the red pixel area; forming a first emission common layer; forming a third hole transporting layer on the first emission common layer in a position corresponding to the green pixel area; forming a second emission common layer; forming a fourth hole transporting layer on the second emission common layer in a position corresponding to the blue pixel area; forming a third emission common layer; forming an electron transporting layer on the third emission common layer; and forming a second electrode on the electron transporting layer.

Abstract: A method of forming a hole transport layer in which an amount of ink per unit surface area to be applied to a plurality of groove regions is set so as to decrease in an order R, G, B. Prior to applying the ink, a nozzle head is scanned across while applying only solvent to each of the groove regions. At this time, an amount of the solvent to be applied to the groove regions is set so as to increase in the order R, G, B.

Abstract: A touch organic light emitting diode (OLED) display device, including: a thin film transistor formed on one side of a substrate, a touch signal feedback layer formed on the thin film transistor, a luminous substrate provided on the touch signal feedback layer, and a touch signal receiving layer formed on the other side of the substrate. An anode layer of the luminous substrate is connected to a drain electrode of the thin film transistor. As to the touch-sensitive OLED display device, a touch screen and an OLED display portion are prepared integratedly, so that the weight and thickness of the display itself are greatly reduced, and the production cost is saved. A manufacturing method of the touch-sensitive OLED display device is further disclosed.

Abstract: A transparent organic light emitting display device having a pixel region on which an image is displayed and a transparent region through which external light passes. The transparent organic light emitting display device includes a first substrate, a second substrate opposing the first substrate, a display unit disposed between the first substrate and the second substrate, the display unit including an organic light emitting diode. A sealing unit is disposed between the first substrate and the second substrate to surround the display unit and to bond the first substrate to the second substrate. A filling unit is disposed in an inner side of the sealing unit to cover the display unit, the filling unit including a silicon filling material and a photochromic material.

Abstract: A flexible display panel comprises a display element (100) and a drive unit (50) disposed on a first surface (A) of a flexible base (20) and a supporting substrate (200) disposed on a second surface (B), opposite to the first surface (A), of the flexible base (20). The position of the supporting substrate (200) corresponds to a bonding position (C) of the drive unit (50). The flexible display panel can avoid a bonding alignment deviation caused by a deformation of the flexible display panel during a bonding process.

Abstract: An organic light-emitting diode (OLED) substrate, which includes a plurality of light-emitting sub-pixels and a pixel partition wall, wherein at least one layer among hole injection layers (HIL), hole transport layers (HTL) and organic light-emitting layers of at least two light-emitting sub-pixels has a different thickness; and upper surfaces of the HIL, the HTL and the organic light-emitting layer of any light-emitting sub-pixel are each parallel and level to an upper surface of one respective lyophilic film layer of the pixel partition wall. The OLED substrate can be used for improving the surface smoothness of each organic layer of the light-emitting sub-pixel. The embodiment of the present invention further provides a display device.

Abstract: An organic light-emitting display apparatus includes a pad electrode structure having excellent reliability due to the prevention of propagation of a crack to the pad electrode. The organic light-emitting display apparatus includes further an interlayer insulating layer on the pad electrode, a conductive barrier layer, and a planarization insulating layer. The interlayer insulating layer includes a plurality of openings that expose an upper surface of the pad electrode. The conductive barrier layer is on the plurality of openings and the interlayer insulating layer. The planarization insulating layer covers an edge of the conductive barrier layer. The planarization insulating layer is in the openings and covers an edge of the conductive barrier layer. An upper portion of the planarization insulating layer may be substantially planar with an upper portion of the conductive barrier layer on convex portions of the interlayer insulating layer.

Abstract: There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.

Abstract: A manufacturing method of a display device includes forming a pixel in a display area of a panel, forming a transistor circuit in a peripheral area of the panel, the peripheral area being located in the vicinity of the display area, forming a first pad in a part of the peripheral area, forming a second pad in a peripheral area of another panel adjacent to the part of the panel, the second pad being electrically connected to the transistor circuit, performing a driving inspection on the transistor circuit by use of the second pad, and separating the first pad and the second pad from each other after the driving inspection.

Abstract: A display apparatus including a pixel including a first thin-film transistor (TFT) and a second TFT connected to the first TFT, the display apparatus includes a substrate, a semiconductor layer disposed on the substrate and including an active region of the first TFT and an active region of the second TFT, a first gate layer disposed on the semiconductor layer and including a gate of the first TFT and a gate of the second TFT, a second gate layer disposed on the first gate layer and including a connection node connecting the gate of the first TFT to the active region of the second TFT, and a line layer disposed on the second gate layer and configured to supply a driving voltage to the pixel.

Abstract: A semiconductor device includes a first coil that is monolithically integrated in a first portion of a semiconductor body and that includes a first winding wrapping around a first core structure. A second coil is monolithically integrated in a second portion of the semiconductor body and includes a second winding wrapping around the second core structure. The first and second coils are magnetically coupled with each other. An insulator frame in the semiconductor body surrounds the first portion and excludes the second portion. High dielectric strength between the first and the second coils is achieved without patterning a backside metallization for connecting the turns of the windings and without being restricted to thin substrates.

Abstract: A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties.

Abstract: An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary.

Abstract: A semiconductor device includes a first semiconductor structure having a first active region pattern density. The semiconductor device further includes a second semiconductor structure having a second active region pattern density, wherein the second semiconductor structure comprises a first resistive element. The semiconductor device further includes a third semiconductor structure having a third active region pattern density, wherein the third semiconductor structure includes a second resistive element. The second semiconductor structure is adjacent to the first semiconductor structure and adjacent to the third semiconductor structure. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure do not overlap.

Abstract: An electricity storage device includes a first electrode, a second electrode, an electricity storage layer, and a p-type semiconductor layer. The electricity storage layer is placed between the first electrode and the second electrode. The electricity storage layer contains a mixture of an insulating material and n-type semiconductor particles. The p-type semiconductor layer is placed between the electricity storage layer and the second electrode. The n-type semiconductor particles contain at least one of a titanium-niobium composite oxide and a titanium-tantalum composite oxide.

Abstract: According to an embodiment of the invention there may be provided a die that may include a first capacitor layer that comprises (a) a first capacitor conductive plate, and (b) a first capacitor layer dielectric material that partially surrounds the first capacitor conductive plate; a first conductor; an intermediate metal layer that comprises (a) an intermediate metal layer conductor that is made of Copper, and (b) an intermediate metal layer dielectric material that partially surrounds the intermediate metal layer conductor; wherein the first conductor is positioned between a substrate of the die and the intermediate metal layer; a redistribution layer that comprises (a) a redistribution layer conductor that is electrically coupled to an interface pad of the die, (b) a second capacitor conductive plate, and (c) a redistribution layer dielectric material that partially surrounds the redistribution layer conductor and the second capacitor conductive plate; wherein a certain portion of the intermediate metal la

Abstract: A capacitor includes a bottom electrode and a top electrode positioned above the bottom electrode. The top electrode and the bottom electrode are conductively coupled to one another. A middle electrode is positioned between the bottom electrode and the top electrode. A lower dielectric layer is positioned between the bottom electrode and the middle electrode. An upper dielectric layer positioned between the middle electrode and the top electrode. A first contact is conductively coupled to the top electrode. A second contact is conductively coupled to the middle electrode.

Abstract: Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of fabricating devices are also provided herein.

Abstract: An IGBT includes an emitter electrode, base regions, an emitter region, a collector region, a collector electrode, a gate insulating film provided in contact with the silicon carbide semiconductor region, the emitter region, and the base region, and a gate electrode that faces the gate insulating film. A FWD includes a base contact region provided adjacent to the emitter region and electrically connected to the emitter electrode, and a cathode region disposed in the upper layer part on the other main surface side of the silicon carbide semiconductor region, provided adjacent to the collector region, and electrically connected to the collector electrode. The IGBT further includes a reduced carrier-trap region disposed in a principal current-carrying region of the silicon carbide semiconductor region located above the collector region and having a smaller number of carrier traps than the silicon carbide semiconductor region located above the cathode region.

Abstract: Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions.

Abstract: Improvements are achieved in the performance and reliability of a semiconductor device. In a trench in an n-type semiconductor substrate, a gate electrode for a trench-gate field effect transistor is formed via a gate insulating film. A p-type semiconductor region for channel formation is formed so as to be adjacent to the trench. Over the p-type semiconductor region, a source n+-type semiconductor region is formed so as to be adjacent to the trench. In the semiconductor substrate, a first p-type column is formed under the p-type semiconductor region. Under the first p-type column, a second p-type column is formed. The first p-type column is internally included in the second p-type column in plan view. The two-dimensional size of the second p-type column is larger than the two-dimensional size of the first p-type column.

Abstract: An integrated device includes a semiconductor body including an STI insulating structure that laterally delimits first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. A power component, formed in the second active area, includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region. The insulating region is arranged between the body region and the drain-contact region and has a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.

Abstract: The present invention provides a filed effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved.