Abstract: In order to provide an ion beam apparatus excellent in safety and stability even when a sample is irradiated with hydrogen ions, the ion beam apparatus includes a vacuum chamber, a gas field ion source that is installed in the vacuum chamber and has an emitter tip, and gas supply means for supplying a gas to the emitter tip. The gas supply means includes a mixed gas chamber that is filled with a hydrogen gas and a gas for diluting the hydrogen gas below an explosive lower limit.

Abstract: An X-ray diagnostic apparatus comprises an X-ray tube and processing circuitry. The X-ray tube includes a rotary anode. The processing circuitry is configured to derive an acquiring condition from a fluoroscopic image, and start to increase, in accordance with the acquiring condition derived, a rotating speed of the anode from a low rotating speed to a high rotating speed before the X-ray tube finishes emitting an X-ray to acquire the fluoroscopic image.

Abstract: A method of producing an implantation ion energy filter, suitable for processing a power semiconductor device. In one example, the method includes creating a preform having a first structure; providing an energy filter body material; and structuring the energy filter body material by using the preform, thereby establishing an energy filter body having a second structure.

Abstract: A multi charged particle beams exposure method includes assigning, with respect to plural times of shots of multi-beams using a charged particle beam, each shot to one of plural groups, depending on a total current value of beams becoming in an ON condition in a shot concerned in the multi-beams, changing the order of the plural times of shots so that shots assigned to the same group may be continuously emitted for each of the plural groups, correcting, for each group, a focus position of the multi-beams to a focus correction position for a group concerned corresponding to the total current value, and performing the plural times of shots of the multi-beams such that the shots assigned to the same group are continuously emitted in a state where the focus position of the multi-beams has been corrected to the focus correction position for the group concerned.

Abstract: The presently disclosed ion sources include one or more electromagnets for changing the distribution of plasma within a discharge space of an ion source. At least one of the electromagnets is oriented about an outer periphery of a tubular sidewall of the ion source and changes a distribution of the plasma in a peripheral region of the discharge space.

Abstract: A method for forming reliefs on the surface of a substrate, including a first implantation of ions in the substrate according to a first direction; a second implantation of ions in the substrate according to a second direction that is different from the first direction; at least one of the first and second implantations is carried out through at least one mask having at least one pattern; an etching of areas of the substrate having received by implantation a dose greater than or equal to a threshold, selectively to the areas of the substrate that have not received via implantation a dose greater than said threshold; the parameters of the first and second implantations being adjusted in such a way that only areas of the substrate that have been implanted both during the first implantation and during the second implantation receive a dose greater than or equal to said threshold.

Abstract: [OBJECT] To provide a radio-frequency power source capable of outputting radio-frequency power having a desired waveform changing at high speed. [SOLUTION] A radio-frequency power source 1 includes two DC-RF converting circuits 4A, 4B and an RF combining circuit 5 for combining the outputs from both DC-RF converting circuits 4A, 4B. The DC-RF converting circuits 4A, 4B amplify radio-frequency voltages va, vb inputted from a radio-frequency signal generating circuit 8, and output radio-frequency voltages vPA, vPB. The RF combining circuit 5 outputs radio-frequency voltage vPX at a ratio corresponding to the phase difference ? between the radio-frequency voltages vPA and vPB. A controlling circuit 9 switches the phase difference ? between ?1 and ?2. As a result, the power PX outputted from the RF combining circuit 5 becomes pulsed radio-frequency power having a high level period and a low level period.

Abstract: An apparatus for a semiconductor process includes an exhaust pipe coupled to a reaction chamber and a pump; a pressure control valve that is coupled to the exhaust pipe and configured to control a pressure value in the reaction chamber; a first pipe that is coupled to the exhaust pipe and etching gas source such that the first pipe is configured to provide an etching gas into the exhaust pipe; a second pipe that is coupled to the exhaust pipe and a radical generator such that the second pipe is configured to provide a radical into the exhaust pipe; and a third pipe that is coupled to the exhaust pipe and a diluted gas source such that the third pipe is configured to provide diluted gas into the exhaust pipe.

Abstract: When conducting imaging mass analysis for a region to be measured on a sample, an individual reference value calculating part obtains a maximum value in Pi/Ii of respective measuring points, and stores the value together with measured data as an individual reference value. When performing comparison analysis for a plurality of the data obtained from different samples, a common reference value determining part reads out corresponding a plurality of the individual reference values and determines a minimum value as a common reference value Fmin. A normalization calculation processing part normalizes the respective intensity values by multiplying the intensity values read out from an external memory device by a normalization coefficient long_Max×(Fmin/Pi) obtained from the common reference value Fmin, TIC values Pi at the respective measuring points, and a maximum allowable value long_Max of a variable storing the intensity values at the time of operation.

Abstract: Reflectron-electromagnetostatic cells for use in mass spectrometers are provided herein that cause ion packets to pass through the cell a plurality of times during fragmentation.

Abstract: A time of flight mass spectrometer that includes a first electrode; and a second electrode that is spaced apart from the first electrode. The ion source is configured to apply voltages to the first and second electrodes to produce an electric field in a region between the first and second electrodes so as to influence ions present in the region between the first and second electrodes when the mass spectrometer is in use. A shield is formed on the first electrode and/or second electrode.

Abstract: A method of static gas mass spectrometry is provided. The method includes the steps of: introducing a sample gas comprising two or more isotopes to be analyzed into a static vacuum mass spectrometer at a time, t0; operating an electron impact ionization source of the mass spectrometer with a first electron energy below the ionization potential of the sample gas for a first period of time that is following t0 until a time t1; and operating the electron impact ionization source with a second electron energy at least as high as the ionization potential of the sample gas for a second period of time that is after time t1. The first time period from t0 to t1 is a period corresponding to a period taken for the isotopes of the sample gas to equilibrate in the mass spectrometer. A constant ion source temperature is preferably maintained. Also provided is a static gas mass spectrometer.

Abstract: A method is described for the analysis of biological polymers, for example, intact proteins or oligonucleotides, by mass spectrometry. This method produces sample ions from a sample containing biological polymers, and ion species are selected that correspond to different charge states of a biological polymer molecule. The ion species are concurrently isolated from the sample ions to generate precursor ions in an ion trap mass spectrometer or in a quadrupole mass filter mass spectrometer. Precursor ions or product ions derived from the precursor ions may then be mass analyzed. The mass analysis step may include fragmenting the precursor ions to form product ions.

Abstract: Ions are injected into an orbital electrostatic trap. An ejection potential is applied to an ion storage device, to cause ions stored in the ion storage device to be ejected towards the orbital electrostatic trap. Synchronous injection potentials are applied to a central electrode of the orbital electrostatic trap and a deflector electrode associated with the orbital electrostatic trap, to cause the ions ejected from the ion storage device to be captured by the electrostatic trap such that they orbit the central electrode. Application of the ejection potential and application of the synchronous injection potentials are each started at respective different times, the difference in times being selected based on desired values of mass-to-charge ratios of ions to be captured by the orbital electrostatic trap.

Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate, a group III-Nitride or II-VI wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group III-Nitride or II-VI wurtzite layer. In some embodiments, each of the plurality of buffer structures may include a central member disposed over the semiconductor substrate, a lower lateral member disposed over the semiconductor substrate and extending laterally away from the central member, and an upper lateral member disposed over the central member and extending laterally from the central member in an opposite direction from the lower lateral member. The plurality of buffer structures may be positioned in a staggered arrangement to terminate defects of the group III-Nitride or II-VI wurtzite layer. Other embodiments may be described and/or claimed.

Abstract: Processes are provided herein for deposition of organic films. Organic films can be deposited, including selective deposition on one surface of a substrate relative to a second surface of the substrate. For example, polymer films may be selectively deposited on a first metallic surface relative to a second dielectric surface. Selectivity, as measured by relative thicknesses on the different layers, of above about 50% or even about 90% is achieved. The selectively deposited organic film may be subjected to an etch process to render the process completely selective. Processes are also provided for particular organic film materials, independent of selectivity.

Abstract: A method for manufacturing an array substrate comprises forming a pattern including an active layer, a gate insulating layer and a gate on a base substrate, and forming a pattern including an interlayer dielectric layer, a source, a drain and a pixel electrode through a single patterning process on the base substrate formed with the pattern of the active layer, the gate insulating layer and the gate. An array substrate and a display device are further provided.

Abstract: A method of producing an optoelectronic semiconductor chip includes in order: A) creating a nucleation layer on a growth substrate, B) applying a mask layer on to the nucleation layer, C) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by mask islands having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, D) further growing the coalescence layer with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer, E) growing a multiple quantum well structure on the coalescence layer, F) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for the total reflection of radiation generated in the multiple quantum well structure, and G) detaching the growth substrate and creating a roughening by etching.

Abstract: The present invention relates to a method of manufacturing semiconductor materials comprising interface layers of group III-V materials in combination with Si substrates. Especially the present invention is related to a method of manufacturing semiconductor materials comprising GaAs in combination with Si(111) substrates, wherein residual strain due to different thermal expansion coefficient of respective materials is counteracted by introducing added layer(s) compensating the residual strain.

Abstract: An epitaxial substrate for electronic devices, including: a Si-based substrate; an AlN initial layer provided on the Si-based substrate; and a buffer layer provided on the AlN initial layer, wherein the roughness Sa of the surface of the AlN initial layer on the side where the buffer layer is located is 4 nm or more. As a result, an epitaxial substrate for electronic devices, in which V pits in a buffer layer structure can be suppressed and longitudinal leakage current characteristics can be improved when an electronic device is fabricated therewith, is provided.

Abstract: A buffer layer is employed to fabricate diamond membranes and allow reuse of diamond substrates. In this approach, diamond membranes are fabricated on the buffer layer, which in turn is disposed on a diamond substrate that is lattice-matched to the diamond membrane. The weak bonding between the buffer layer and the diamond substrate allows ready release of the fabricated diamond membrane. The released diamond membrane is transferred to another substrate to fabricate diamond devices, while the diamond substrate is reused for another fabrication.

Abstract: A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.

Abstract: To provide a sputtering apparatus capable of forming a semiconductor film in which impurities such as hydrogen or water are reduced. The sputtering apparatus is capable of forming a semiconductor film and includes a deposition chamber, a gas supply device connected to the deposition chamber, a gas refining device connected to the gas supply device, a vacuum pump for evacuating the deposition chamber, a target disposed in the deposition chamber, and a cathode disposed to face the target. The gas supply device is configured to supply at least one of an argon gas, an oxygen gas, and a nitrogen gas. The partial pressure of hydrogen molecules is lower than or equal to 0.01 Pa and the partial pressure of water molecules is lower than or equal to 0.0001 Pa in the deposition chamber.

Abstract: The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer on the substrate filling in-between the fin structures in the logic region; forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region; exposing a portion of the fin structures and a portion of the epitaxial structure by removing a portion of the oxide layer; and forming a gate electrode on portions of the fin structures.

Abstract: The present invention generally relates to nanoscale wires and, in particular, to nanoscale wires with heterojunctions, such as tip-localized homo- or heterojunctions. In one aspect, the nanoscale wire may include a core, an inner shell surrounding the core, and an outer shell surrounding the inner shell. The outer shell may also contact the core, e.g., at an end portion of the nanoscale wire. In some cases, such nanoscale wires may be used as electrical devices. For example a p-n junction may be created where the inner shell is electrically insulating, and the core and the outer shell are p-doped and n-doped. Other aspects of the present invention generally relate to methods of making or using such nanoscale wires, devices, or kits including such nanoscale wires, or the like.

Abstract: A composition for manufacturing a semiconductor device includes at least one carbon-based compound that includes at least one of an alkyne group and an azide group, and a solvent. A method of manufacturing a semiconductor device includes forming a feature layer on a substrate, coating the feature layer with a composition including alkyne and azide, forming a carbon-containing layer including a triazole compound by performing a heat treatment on the coated composition, forming a photoresist film on the carbon-containing layer, forming photoresist patterns by exposing and developing the photoresist film, and patterning the carbon-containing layer and the feature layer using the photoresist patterns.

Abstract: An ion implantation system has a first chamber and a process chamber with a heated chuck. A controller transfers the workpiece between the heated chuck and first chamber and selectively energizes the heated chuck first and second modes. In the first and second modes, the heated chuck is heated to a first and second temperature, respectively. The first temperature is predetermined. The second temperature is variable, whereby the controller determines the second temperature based on a thermal budget, an implant energy, and/or an initial temperature of the workpiece in the first chamber, and generally maintains the second temperature in the second mode. Transferring the workpiece from the heated chuck to the first chamber removes implant energy from the process chamber in the second mode. Heat may be further transferred from the heated chuck to a cooling platen by a transfer of the workpiece therebetween to sequentially cool the heated chuck.

Abstract: Provided is a method of producing a semiconductor epitaxial wafer having enhanced gettering ability. The method of producing a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer that is located in a surface portion of the semiconductor wafer and that includes a constituent element of the cluster ions in solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. The first step is performed in a state in which a temperature of the semiconductor wafer is maintained at lower than 25° C.

Abstract: Disclosed are sulfur-containing compounds for plasma etching channel holes, gate trenches, staircase contacts, capacitor holes, contact holes, etc., in Si-containing layers on a substrate and plasma etching methods of using the same. The plasma etching compounds may provide improved selectivity between the Si-containing layers and mask material, less damage to channel region, a straight vertical profile, and reduced bowing in pattern high aspect ratio structures.

Abstract: Provided is an etching delay element for forming a protruding portion at an object by shielding part of the object against etching, the etching delay element being attached to a non-etching section of the object corresponding to the protruding portion and being made of a material that is etchable by an etchant.

Abstract: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.

Abstract: A method is described for vapor phase etching of oxide material including at least one of hafnia (HfO2) and zirconia (ZrO2), in the absence of plasma exposure of the oxide material. The method involves contacting the oxide material with an etching medium including at least one of phosphorus chloride and tungsten chloride under conditions producing a removable fluid reaction product, and removing the removable fluid reaction product. The etching process may be controllably carried out by use of pressure swings, temperature swings, and/or modulation of partial pressure of Hf or Zr chloride in the reaction, e.g., to achieve precision etch removal in the manufacture of semiconductor devices such as 3D NAND, sub-20 nm DRAMs, and finFETs.

Abstract: Processes are provided herein for deposition of organic films. Organic films can be deposited, including selective deposition on one surface of a substrate relative to a second surface of the substrate. For example, polymer films may be selectively deposited on a first metallic surface relative to a second dielectric surface. Selectivity, as measured by relative thicknesses on the different layers, of above about 50% or even about 90% is achieved. The selectively deposited organic film may be subjected to an etch process to render the process completely selective. Processes are also provided for particular organic film materials, independent of selectivity. Masking applications employing selective organic films are provided. Post-deposition modification of the organic films, such as metallic infiltration and/or carbon removal, is also disclosed.

Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.

Abstract: A method of manufacturing a semiconductor device may include forming a first stack structure by alternately stacking first material layers and second material layers, forming first holes penetrating the first stack structure and a first slit located between the first holes, forming channel patterns in the first holes and a dummy channel pattern in the first slit, selectively removing the dummy channel pattern from the first slit, and replacing the first material layers with third material layers through the first slit.

Abstract: Methods of forming vias in substrates having at least one damage region extending from a first surface etching the at least one damage region of the substrate to form a via in the substrate, wherein the via extends through the thickness T of the substrate while the first surface of the substrate is masked. The mask is removed from the first surface of the substrate after etching and upon removal of the mask the first surface of the substrate has a surface roughness (Rq) of about less than 1.0 nm.

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed.

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

Abstract: A substrate processing apparatus includes a process chamber and a transfer device configured to transfer a plurality of substrates to a substrate retainer. The transfer device includes a base; a first moving unit capable of linear motion; a first drive unit to drive the first moving unit. The first drive unit includes a first pulley group; a first motor coupled to a first pulley; and a first connecting member coupling the first belt and the first moving unit. A second moving unit is capable of linear motion. A second drive unit is in an enclosure of the first moving unit and drives the second moving unit. The second drive unit includes a second pulley group; a second belt wound on the second pulley group, a second motor coupled to drive a second pulley; and a second connecting member coupling the second belt and the second moving unit.

Abstract: Embodiments disclosed herein generally relate to methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a III-V epitaxial growth process or an etch clean process, and prior to additional processing. An oxygen containing gas is flowed to a substrate in a load lock chamber, and subsequently a non-reactive gas is flowed to the substrate in the load lock chamber. As such, hazardous gases and outgassing residuals are decreased and/or removed from the substrate such that further processing may be performed.

Abstract: The present disclosure generally relates to methods and apparatus for facilitating electrical feedthrough in plasma processing chambers. The apparatus includes an electrically insulating housing positioned on a backside of the substrate support to contain a secondary plasma therein. The secondary plasma facilitates an electrical connection between the substrate support and electrical power or ground located outside the processing chamber. The methods include utilizing a secondary plasma to electrically couple substrate support to and electrical power or ground located outside the processing chamber.

Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.

Abstract: A substrate processing method includes a first process of supplying a first gas to a substrate; and a second process of supplying a second gas to the substrate after the first process. When a distance from an edge of the substrate to a boundary between a processing space and a gas exhaust space is L, a cross sectional area of a space orthogonal to a flow of the second gas is S(x), a supply flow rate of the second gas is Q, a pressure within the processing space is P and a diffusion coefficient of the first gas to the second gas is D, at least one of the distance L, the cross sectional area S(x) and the supply flow rate Q in the second process is adjusted such that a Peclet number Pe calculated by expression (3) becomes larger than 1.

Abstract: A method for laminating glass panels includes (1) providing a TFT substrate and a CF substrate to be laminated, in which the CF substrate is coated with a seal resin and the TFT substrate carries liquid crystal dropped thereon; (2) aligning and laminating the TFT substrate and the CF substrate in a vacuum environment to complete a lamination process; (3) applying UV light to transmit through the TFT substrate for carrying out UV curing of the seal resin interposed between the CF substrate and the TFT substrate so as to complete a UV curing process; and (4) removing the laminated CF substrate and the TFT substrate that have been subjected to the UV curing process out of the vacuum environment.

Abstract: A transfer chamber for a processing system suitable for processing a plurality of substrates and a method of using the same is provided. The transfer chamber includes a lid, a bottom disposed opposite the lid, a plurality of sidewalls sealingly coupling the lid to the bottom and defining an internal volume, wherein the plurality of sidewalls form the faces of a dodecagon. An opening is formed in each of the faces, wherein the opening is configured for a substrate to pass therethrough. A transfer robot is disposed in the internal volume, wherein the transfer robot has effectors configured to support the substrate through one opening to another opening.

Abstract: Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.

Abstract: A semiconductor method is disclosed. The semiconductor method is performed upon semiconductor wafers, wherein each of the semiconductor wafers includes a first exposure field and a second exposure field, and each of the first exposure field and the second exposure field includes a first alignment mark and a second alignment mark. The method includes: determining a first alignment pattern for a first wafer by selecting one of the alignment marks of the first exposure field, and selecting one of the alignment marks of the second exposure field; performing the aligning operation upon the first semiconductor wafer by using the first alignment pattern; determining a second alignment pattern for a second wafer by selecting one of the alignment marks of the first exposure field, and selecting one of the alignment marks of the second exposure field, wherein the first alignment pattern is different from the second alignment pattern.

Abstract: A workpiece carrier suitable for high power processes is described. It may include a top plate to support a workpiece, a lift pin to lift a workpiece from a top plate, a lift pin hole through the top plate to contain the lift pin, and a connector to the lift pin hole to connect to a source of gas under pressure to deliver a cooling gas, for example helium, to the back side of the workpiece.

Abstract: A workpiece carrier suitable for high power processes is described. It may include a puck to carry the workpiece, a plate bonded to the puck by an adhesive, a mounting ring surrounding the puck and the cooling plate, and a gasket between the mounting ring and the plate, the gasket configured to protect the adhesive.