Patents Issued in December 7, 2017
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Publication number: 20170352367Abstract: According to one embodiment, a magnetic recording and reproducing device includes a magnetic recording medium, and a magnetic head including a first reproducing unit. The first reproducing unit includes a first magnetic field generator separated from the magnetic recording medium in a first direction, and a first stacked body. At least a portion of the first stacked body is provided between the magnetic recording medium and the first magnetic field generator in the first direction. The first stacked body includes a first magnetic layer, a second magnetic layer separated from the first magnetic layer in a second direction crossing the first direction, and a first intermediate layer provided between the first magnetic layer and the second magnetic layer. The first stacked body performs an operation of generating a first alternating magnetic field. The first magnetic field generator generates a first magnetic field.Type: ApplicationFiled: February 21, 2017Publication date: December 7, 2017Inventors: Taro Kanao, Hirofumi Suto, Koichi Mizushima, Rie Sato
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Publication number: 20170352368Abstract: A PMR writer is disclosed wherein magnetic flux return from a magnetic medium to a main pole is substantially greater through a trailing shield structure than through a leading return loop comprised of a leading shield, return path layer (RTP), and back gap connection (BGC). Magnetic impedance is increased between the RTP and main pole in the leading return loop by removing one or more layers in the BGC and replacing with dielectric material and non-magnetic metal to form a dielectric gap between the RTP and main pole. The non-magnetic metal may be Cu that is electrically isolated from coils within the write head. As a result, area density control and bit error rate are improved over a conventional dual write shield (DWS) structure comprising two flux return pathways. Moreover, adjacent track erasure is maintained at a level similar to a DWS design.Type: ApplicationFiled: August 24, 2017Publication date: December 7, 2017Inventors: Yaguang Wei, Yuhui Tang, Moris Dovek, Yue Liu
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Publication number: 20170352369Abstract: A tape head including a body exhibiting a tape-bearing area is provided. The body includes at least one transducer that is a read element or a write element, configured in the tape head so as for the tape head to read from or write to a magnetic tape, in operation. The tape-bearing area is essentially covered by an electrically conducting layer of material. This way, the exposed surface of the electrically conducting layer essentially forms the tape-bearing surface of the tape head, which surface contacts the magnetic tape, in operation. A tape head apparatus for recording or reproducing multi-track tapes including the tape head is also provided.Type: ApplicationFiled: August 24, 2017Publication date: December 7, 2017Inventors: Robert G. Biskeborn, Johan Engelen, Mark A. Lantz, Hugo E. Rothuizen
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Publication number: 20170352370Abstract: Systems and methods for compensating for hysteresis in a disc drive are described. In one embodiment, a method may use an inverse hysteresis model to linearize effects of hysteresis of a microactuator in the disc drive. The hysteresis model may be a Coleman-Hodgdon hysteresis model. The hysteresis of the microactuator may be characterized, and the inverse hysteresis model may be based at least in part on the characterization. The inverse hysteresis model may be used to implement a digital filter. The digital filter may be employed in series with the microactuator to linearize the effects of hysteresis.Type: ApplicationFiled: August 7, 2017Publication date: December 7, 2017Applicant: SEAGATE TECHNOLOGY LLCInventors: REED D. HANSON, KENNETH A. HAAPALA, DWIGHT R. KINNEY, XINGHUI HUANG
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Publication number: 20170352371Abstract: Systems and methods for compensating for magnetoresistive (MR) jog offset direct current (DC) drift in a disc drive are described. In one embodiment, a method may include determining an occurrence of NOS, for example, by monitoring disc slip, to determine when the method should proceed. An MR jog offset DC drift amount is determined for each head of the disc drive. One of several approaches may be employed for determining the MR jog offset DC drift amount. By determining an MR jog offset DC drift amount for each head, a compensation profile is determined for the drive. The determined compensation profile may then be used during operation of the disc drive to compensate for the DC drift. One of several approaches may be employed for compensating based on the compensation profile.Type: ApplicationFiled: November 2, 2016Publication date: December 7, 2017Applicant: SEAGATE TECHNOLOGY LLCInventors: Mingzhong DING, Xiong LIU, Xiang LU, Qiang BI, Kian Keong OOI
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Publication number: 20170352372Abstract: The present invention aims at providing a magnetic recording medium that can lower a Curie temperature (Tc) of a magnetic material, without increasing an in-plane coercive force and lowering magnetic properties. The magnetic recording medium is a magnetic recording medium comprising a substrate and a magnetic recording layer, the magnetic recording layer comprising an FePtRh ordered alloy, wherein a Rh content in the FePtRh ordered alloy is 10 at % or less.Type: ApplicationFiled: July 31, 2017Publication date: December 7, 2017Inventors: Tomohiro Moriya, Hitoshi Nakata, Takehito Shimatsu
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Publication number: 20170352373Abstract: In accordance with embodiments of the present disclosure, a sequential storage media drive may include a first reel for rotatably winding sequential storage media tape from an opposing second reel of a data cartridge, an enclosure for housing the first reel and housing the data cartridge when the data cartridge is inserted into the sequential storage media drive and an access door mechanically coupled to the enclosure, the access door configured to be translated from a closed position to an open position to allow a user to access the first reel from an exterior of the enclosure in the event the data cartridge of the sequential storage media tape becomes lodged in the sequential storage media drive.Type: ApplicationFiled: June 6, 2016Publication date: December 7, 2017Applicant: Dell Products L.P.Inventors: Elizabeth A. McTeer, Randy M. Ortiz
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Publication number: 20170352374Abstract: To enable an HDR image and an HDR image metadata to be stored in an MP4 file, and a reproduction device to reproduce an optimum HDR image based on metadata. In generating the MP4 file that stores HDR image data, the HDR image metadata is recorded in the MP4 file. An HDR image metadata storage box is set to a trak box or a traf box in the MP4 file, and the HDR image metadata is stored. The reproduction device acquires the HDR image metadata stored in the MP4 file, determines whether executing a conversion process of the HDR image read from. the MP4 file according to the acquired metadata and display function information of the display unit, and executes an output image generation process according to a determination result.Type: ApplicationFiled: November 13, 2015Publication date: December 7, 2017Inventors: RYOHEI TAKAHASHI, KOUICHI UCHIMURA
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Publication number: 20170352375Abstract: A method for recording parity data of data stripes within shingled media recording bands in a redundant array of independent disks can be accomplished using a plurality of shingled media recording (SMR) hard disk drives (HDD) each with a plurality of shingled data bands. A data stream received from a host computer system is sequentially stored to a plurality of block segments in successive order, one stripe at a time successively. Each of the shingled data bands possess n data blocks (or multiple data blocks that are grouped together as a data unit) that are successively ordered, each corresponding successive data block from all of the SMR HDDs defines a data stripe, accordingly n data blocks in each SMR HDD defines n stripes across the shingled data bands. A transaction group sync triggers a halt to writing the data stream. The rest of the data stripe is written with fill bits.Type: ApplicationFiled: May 31, 2017Publication date: December 7, 2017Inventor: Alan William Somers
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Publication number: 20170352376Abstract: An implementation of a system disclosed herein provides a method for managing data streams of sequential nature, wherein the method writes the sequential chunks (fragments) directly to an open band in the order these are received from the host and includes determining an end of the incoming data write request related to streaming data and in response to the determination of the end of the incoming data write request related to streaming data, copying remaining data from a current physical band mapped to logical block addresses LBAs related to the data write requests to the allocated (open) band.Type: ApplicationFiled: August 24, 2017Publication date: December 7, 2017Inventors: Anil Kashyap, Brian T. Edgar
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Publication number: 20170352377Abstract: Systems and methods for forward corrupted track detection and by-pass are described. In one embodiment, a storage system comprising a storage controller performs a read operation for a target track of a shingled magnetic recording (SMR) disk drive and detects a read operation failure of the read operation for the target track. The storage controller also performs a boundary track read operation on one or more tracks including or adjacent to the target track and detect a forward corruption area based on the boundary track read operation. In another embodiment, a method is provided that includes detecting a read operation failure of a read operation for a track of a disk drive and performing a boundary track read operation on one or more tracks including or adjacent to the target track. The method also includes detecting a forward corruption area based on the boundary track read operation.Type: ApplicationFiled: June 6, 2017Publication date: December 7, 2017Applicant: SEAGATE TECHNOLOGY LLCInventors: JUNGHWAN SHIN, JAE IK SONG, DONG HYUCK SHIN, EUN YEONG HONG
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Publication number: 20170352378Abstract: Disclosed is a system and method for controlling the playback speed, and user experience, of watching slow motion video content on a touch sensitive computing device such as a mobile phone, tablet or laptop with a touch sensitive screen. Key features of the disclosure are the simplicity of the user interface and the instant visual feedback given to the user.Type: ApplicationFiled: June 1, 2016Publication date: December 7, 2017Inventors: George Mitchard, James Tallantyre
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Publication number: 20170352379Abstract: A method for video editing using a mobile terminal and a remote computer is disclosed. A user selects a user video to edit using a mobile application of the mobile terminal. The user selects a visual effect and parameters of the visual effect using the mobile application. Subsequently, the mobile application provides a preview of the visual effect superimposed over the user video using a series of still images representing the visual effect. When the user confirms the preview, the mobile terminal generates a request for video editing and sends the request to a server. The request includes identification of the visual effect for combining the visual effect and the user video as confirmed by the preview. Based on the request from the mobile terminal, the server combines a video clip of the visual effect and the user video into a resulting video.Type: ApplicationFiled: June 24, 2016Publication date: December 7, 2017Inventors: Joo Hyun OH, Min JUNG, Byulsaim KWAK
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Publication number: 20170352380Abstract: A method, system and computer program product for interactively identifying same individuals or objects present in video recordings is disclosed. When a thumbnail in a set of thumbnails is selected, new information is obtained. The new information may be that an individual or object is present in the portion of the video recording associated with the thumbnail. A search can be carried out for the individual or object based on the new information. The search generates new match likelihoods for each of displayed thumbnails within a user interface page. The displayed thumbnails are re-ordered based on the new match likelihoods.Type: ApplicationFiled: December 2, 2016Publication date: December 7, 2017Applicant: Avigilon CorporationInventors: Moussa Doumbouya, Mahesh Saptharishi, Eric Sjue, Hannah Valbonesi
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Publication number: 20170352381Abstract: At least one video stream that is encoded video information, and a management information file indicating attributes relating to the entire recording medium, are recorded in a recording medium. The management information file includes attribute information indicating whether the dynamic range of luminance of an initial video stream, which is played first out of the at least one video stream when the recording medium is inserted into a playback device, is a first dynamic range, or a second dynamic range that is broader than the first dynamic range.Type: ApplicationFiled: August 22, 2017Publication date: December 7, 2017Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Hiroshi YAHATA, Tadamasa TOMA
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Publication number: 20170352382Abstract: At least one video stream that is encoded video information, and a management information file indicating attributes relating to the entire recording medium, are recorded in a recording medium. The management information file includes attribute information indicating whether the dynamic range of luminance of an initial video stream, which is played first out of the at least one video stream when the recording medium is inserted into a playback device, is a first dynamic range, or a second dynamic range that is broader than the first dynamic range.Type: ApplicationFiled: August 22, 2017Publication date: December 7, 2017Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Hiroshi YAHATA, Tadamasa TOMA
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Publication number: 20170352383Abstract: At least one video stream that is encoded video information, and a management information file indicating attributes relating to the entire recording medium, are recorded in a recording medium. The management information file includes attribute information indicating whether the dynamic range of luminance of an initial video stream, which is played first out of the at least one video stream when the recording medium is inserted into a playback device, is a first dynamic range, or a second dynamic range that is broader than the first dynamic range.Type: ApplicationFiled: August 22, 2017Publication date: December 7, 2017Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Hiroshi YAHATA, Tadamasa TOMA
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Publication number: 20170352384Abstract: At least one video stream that is encoded video information, and a management information file indicating attributes relating to the entire recording medium, are recorded in a recording medium. The management information file includes attribute information indicating whether the dynamic range of luminance of an initial video stream, which is played first out of the at least one video stream when the recording medium is inserted into a playback device, is a first dynamic range, or a second dynamic range that is broader than the first dynamic range.Type: ApplicationFiled: August 22, 2017Publication date: December 7, 2017Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Hiroshi YAHATA, Tadamasa TOMA
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Publication number: 20170352385Abstract: At least one video stream that is encoded video information, and a management information file indicating attributes relating to the entire recording medium, are recorded in a recording medium. The management information file includes attribute information indicating whether the dynamic range of luminance of an initial video stream, which is played first out of the at least one video stream when the recording medium is inserted into a playback device, is a first dynamic range, or a second dynamic range that is broader than the first dynamic range.Type: ApplicationFiled: August 22, 2017Publication date: December 7, 2017Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Hiroshi YAHATA, Tadamasa TOMA
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Publication number: 20170352386Abstract: An electrical feed-through, such as a PCB connector, involves at least one positioning protrusion protruding from a main body, and may further include multiple positioning protrusions protruding in respective directions from the main body. A data storage device employing such a feed-through comprises an enclosure base with which the feed-through is coupled, where the base comprises an annular recessed surface surrounding an aperture that is encompassed by the feed-through and is at a first level, and at least one recessed positioning surface at a higher level than the first level and extending in a direction away from the annular recessed surface. The positioning protrusion of the electrical feed-through physically mates with the recessed positioning surface of the base, such that the position of the feed-through is vertically constrained by the recessed positioning surface.Type: ApplicationFiled: June 6, 2016Publication date: December 7, 2017Inventors: Jiro Kaneko, Yuta Onobu
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Publication number: 20170352387Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.Type: ApplicationFiled: August 14, 2017Publication date: December 7, 2017Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H.S. Tang
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Publication number: 20170352388Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.Type: ApplicationFiled: June 12, 2017Publication date: December 7, 2017Inventors: Joe M. Jeddeloh, Brent Keeth
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Publication number: 20170352389Abstract: A word line voltage generator circuit, a semiconductor device, and an electronic device are provided. The word line voltage generator circuit includes a switch circuit connected to a high-level signal and a low-level signal and configured to output the high-level signal or the low-level signal as a word line voltage signal based on an input signal, and a drive signal control circuit configured to provide a drive signal connected to the switch circuit in response to the input signal. A voltage rising speed of the word line voltage signal is controlled by the drive signal.Type: ApplicationFiled: March 29, 2017Publication date: December 7, 2017Inventors: YIJIN KWON, HAO NI, ZIJIAN ZHAO, YU CHENG
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Publication number: 20170352390Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.Type: ApplicationFiled: June 17, 2017Publication date: December 7, 2017Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
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Publication number: 20170352391Abstract: The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments of the present disclosure include an apparatus comprising a shift register comprising an initial stage and a final stage. The shift register may be configured such that a clock signal may be initiated at the final stage of the shift register.Type: ApplicationFiled: June 3, 2016Publication date: December 7, 2017Inventor: Glen E. Hush
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Publication number: 20170352392Abstract: A stacked semiconductor device includes a plurality of semiconductor dies stacked in a vertical direction, first and second signal paths, a transmission unit and a reception unit. The first and second signal paths electrically connect the plurality of semiconductor dies, where each of the first signal path and the second signal path includes at least one through-substrate via. The transmission unit generates a first driving signal and a second driving signal in synchronization with transitioning timing of a transmission signal to output the first driving signal to the first signal path and output the second driving signal to the second signal path. The reception unit receives a first attenuated signal corresponding to the first driving signal from the first signal path and receives a second attenuated signal corresponding to the second driving signal from the second signal path to generate a reception signal corresponding to the transmission signal.Type: ApplicationFiled: April 5, 2017Publication date: December 7, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: HAE-SUK LEE, REUM OH, JIN-SEONG PARK, SEUNG-HAN WOO
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Publication number: 20170352393Abstract: Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.Type: ApplicationFiled: June 6, 2016Publication date: December 7, 2017Inventor: Pohrong Rita Chu
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Publication number: 20170352394Abstract: A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.Type: ApplicationFiled: June 5, 2017Publication date: December 7, 2017Inventors: Sumeet Kumar GUPTA, Ahmedullah AZIZ, Nikhil SHUKLA, Suman DATTA, Xueqing LI, Vijaykrishnan NARAYANAN
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Publication number: 20170352395Abstract: A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Inventors: Guenole Jan, Po-Kang Wang, John De Brosse, Yuan-Jen Lee
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Publication number: 20170352396Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.Type: ApplicationFiled: July 26, 2017Publication date: December 7, 2017Inventor: Eric S. Carman
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Publication number: 20170352397Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.Type: ApplicationFiled: June 3, 2016Publication date: December 7, 2017Inventors: Xinwei Guo, Daniele Vimercati
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Publication number: 20170352398Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a ferroelectric capacitor—e.g., that a ferroelectric capacitor may remain polarized at one of two states without a voltage applied across the ferroelectric capacitor—to activate a subset of sensing components corresponding to multiple memory cells with a common word line. For example, a first and second set of memory cells with a common word like may be selected for a read operation. A first set of sensing components corresponding to the first set of memory cells may be activated for the read operation, and a second set of sensing components that correspond to the second set of memory cells may be maintained in a deactivated state.Type: ApplicationFiled: June 28, 2017Publication date: December 7, 2017Inventor: Christopher John Kawamura
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Publication number: 20170352399Abstract: Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.Type: ApplicationFiled: June 5, 2017Publication date: December 7, 2017Applicant: Renesas Electronics CorporationInventors: Yoshisato YOKOYAMA, Yoshikazu SAITO, Shunya NAGATA, Toshiaki SANO, Takeshi HASHIZUME
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Publication number: 20170352400Abstract: A semiconductor memory device may include a row address generating circuit, a row active pulse generating circuit and a word line activating circuit. The row address generating circuit may generate a row address in response to a refresh command, a row active pulse, and a normal address. The row active pulse generating circuit may generate a row active pulse in response to a refresh signal and an active signal. The word line activating circuit may selectively enable a word line in response to the row address and the row active pulse.Type: ApplicationFiled: April 11, 2017Publication date: December 7, 2017Applicant: SK hynix Inc.Inventor: Jae Il KIM
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Publication number: 20170352401Abstract: A semiconductor integrated circuit is described. A. transmitter-receiver transmits and receives data to and from outside by a first external terminal and transmits a first control signal by a second external terminal. When another data is transmitted after the data is transmitted and when a data transmission interval from a time when the data is transmitted to a time when the another data is transmitted is equal to or smaller than a first threshold, the transmitter-receiver continuously outputs, from the first external terminal, a potential level of about ½ of a potential level obtained by adding a first potential level and a second potential level, during the data transmission interval, and changes the second potential level of the first control signal to the first potential level when the data transmission interval exceeds the first threshold.Type: ApplicationFiled: August 23, 2017Publication date: December 7, 2017Applicant: Renesas Electronics CorporationInventors: Masayasu KOMYO, Yoichi Iizuka
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Publication number: 20170352402Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.Type: ApplicationFiled: August 22, 2017Publication date: December 7, 2017Applicant: MICRON TECHNOLOGY, INC.Inventor: Noriaki Mochida
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Publication number: 20170352403Abstract: A memory controller of a memory device that uses a phase change memory and includes a memory cell array partitioned into a plurality of partitions is provided. A write request that request a data write to the memory device and a read request which request a data read from the memory device are inserted to a request queue. A scheduler, in a case that a conflict check condition including a first condition that a write operation is being performed in a first partition among the plurality of partitions is satisfied, creates a read command for a second partition based on a read request for the second partition when the request queue includes the read request for the second partition. The second partition is a partition, in which a read operation does not conflict with the write operation in the first partition, among the plurality of partitions.Type: ApplicationFiled: July 20, 2016Publication date: December 7, 2017Inventors: Jaesoo LEE, Myoungsoo JUNG, Gyuyoung PARK
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Publication number: 20170352404Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.Type: ApplicationFiled: October 7, 2016Publication date: December 7, 2017Inventors: Jae Seung LEE, Chang Hyun KIM, Yo Sep LEE
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Publication number: 20170352405Abstract: A semiconductor system includes a semiconductor device suitable for not performing an internal refresh operation when entering a self-refresh mode in response to a self-refresh command, and cutting off input of an auto-refresh command when exiting the self-refresh mode.Type: ApplicationFiled: August 22, 2017Publication date: December 7, 2017Applicant: SK hynix Inc.Inventors: Geun Ho CHOI, Man Keun KANG, Myung Kyun KWAK
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Publication number: 20170352406Abstract: A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.Type: ApplicationFiled: June 6, 2016Publication date: December 7, 2017Inventors: Bruce QUERBACH, Kuljit S. BAINS, John B. HALBERT
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Publication number: 20170352407Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sensing circuit for a memory and methods of use. The memory includes a self-referenced sense amp that is structured to calibrate its individual pre-charge based on a trip-point, with autonomous pre-charge activation circuitry that starts pre-charging a sense-line on each unique entry as soon as a sense has been performed or completed.Type: ApplicationFiled: June 7, 2016Publication date: December 7, 2017Inventors: Igor ARSOVSKI, Qing LI, Wei ZHAO, Xiaoli HU
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Publication number: 20170352408Abstract: An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a source terminal coupled to second supply node; and a stack of devices coupled to the first supply node, wherein at least one device in the stack is coupled to the second supply node, and wherein the stack of devices is controllable according to an operation mode.Type: ApplicationFiled: June 7, 2016Publication date: December 7, 2017Inventors: Amit AGARWAL, Steven K. HSU, Sri Harsha CHODAY
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Publication number: 20170352409Abstract: Methods of operating a memory device include applying a programming pulse to a plurality of memory cells selected for programming having an initial portion having a first voltage level and a subsequent portion having a second voltage level less than the first voltage level, inhibiting a particular memory cell of the plurality of memory cells from programming during the initial portion of the programming pulse while a different memory cell of the plurality of memory cells is enabled for programming, and inhibiting the different memory cell from programming during the subsequent portion of the programming pulse while the particular memory cell is enabled for programming.Type: ApplicationFiled: August 28, 2017Publication date: December 7, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Qiang Tang, Xiaojiang Guo, Ramin Ghodsi
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Publication number: 20170352410Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.Type: ApplicationFiled: July 10, 2017Publication date: December 7, 2017Inventor: Hernan A. Castro
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Publication number: 20170352411Abstract: The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase.Type: ApplicationFiled: July 31, 2017Publication date: December 7, 2017Inventor: Hernan A. Castro
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Publication number: 20170352412Abstract: Devices and methods for determining resistive states of resistive change elements in resistive change element arrays are disclosed. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements by sensing current flow. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements without the need for in situ selection devices or other current controlling devices. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can reduce the impact of sneak current when determining resistive states of resistive change elements.Type: ApplicationFiled: June 7, 2016Publication date: December 7, 2017Inventor: Qawi Harvard
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Publication number: 20170352413Abstract: Devices and methods for determining resistive states of resistive change elements in resistive change element arrays are disclosed. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements by sensing current flow. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements without the need for in situ selection devices or other current controlling devices. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can reduce the impact of sneak current when determining resistive states of resistive change elements.Type: ApplicationFiled: June 7, 2016Publication date: December 7, 2017Inventor: Qawi Harvard
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Publication number: 20170352414Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Inventors: Fabio Pellizzer, Roberto Bez, Ferdinando Bedeschi, Roberto Gastaldi
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Publication number: 20170352415Abstract: Devices and methods for determining resistive states of resistive change elements in resistive change element arrays are disclosed. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements by sensing current flow. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements without the need for in situ selection devices or other current controlling devices. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can reduce the impact of sneak current when determining resistive states of resistive change elements.Type: ApplicationFiled: June 7, 2016Publication date: December 7, 2017Inventor: Qawi HARVARD
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Publication number: 20170352416Abstract: Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.Type: ApplicationFiled: August 23, 2017Publication date: December 7, 2017Applicant: Micron Technology, Inc.Inventor: Stephen H. Tang